CN102136475A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN102136475A
CN102136475A CN2010101189718A CN201010118971A CN102136475A CN 102136475 A CN102136475 A CN 102136475A CN 2010101189718 A CN2010101189718 A CN 2010101189718A CN 201010118971 A CN201010118971 A CN 201010118971A CN 102136475 A CN102136475 A CN 102136475A
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layer
substrate
hole structure
forming
metal
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CN102136475B (en
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陈建桦
李德章
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本发明关于一种半导体封装结构及其制造方法。该半导体封装结构包括一基材、一第一电容、一第一保护层、一第一金属层及一第二保护层。该基材具有至少一穿导孔结构。该第一电容位于该基材的一第一表面。该第一保护层包覆该第一电容。该第一金属层位于该第一保护层上，且包括一第一电感。该第二保护层包覆该第一电感。藉此，可将该第一电感、该第一电容及该穿导孔结构一并整合至该半导体封装结构内，以缩减产品尺寸。

Figure 201010118971

The present invention relates to a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one through-hole structure. The first capacitor is located on a first surface of the substrate. The first protective layer covers the first capacitor. The first metal layer is located on the first protective layer and includes a first inductor. The second protective layer covers the first inductor. Thus, the first inductor, the first capacitor and the through-hole structure can be integrated into the semiconductor packaging structure to reduce the product size.

Figure 201010118971

Description

Semiconductor package and manufacture method thereof
Technical field
The present invention is about a kind of semiconductor package and manufacture method thereof, in detail, and about a kind of semiconductor package and manufacture method thereof of integrating passive component.
Background technology
With reference to figure 1, show the generalized section of known semiconductor encapsulating structure.This known semiconductor encapsulating structure 1 comprises a substrate 11, an encapsulation unit 12 and an adhesive body 13.This encapsulation unit 12 comprises several passive component (not shown).This encapsulation unit 12 is positioned on this substrate 11, and is electrically connected to this substrate 11.This adhesive body 13 coats this encapsulation unit 12.
The shortcoming of this known semiconductor encapsulating structure 1 is as follows.These passive components earlier via the semiconductor process integration in this encapsulation unit 12, then, this encapsulation unit 12 is again in the routing mode, or cover the crystal type (not shown), be electrically connected to this substrate 11, cause technology that these passive components are integrated in this semiconductor package 1 complicated, and raise the cost.
Therefore, be necessary to provide a kind of semiconductor package and manufacture method thereof, to address the above problem.
Summary of the invention
The invention provides a kind of manufacture method of semiconductor package, it may further comprise the steps: a base material (a) is provided, and this base material comprises at least one groove and at least one conductive hole structure, and this conductive hole structure is positioned at this groove; (b) form one first electric capacity on this base material, this first electric capacity comprises one first bottom electrode, one first dielectric layer and one first top electrode, this first bottom electrode is positioned on this base material, and this first dielectric layer is positioned on this first bottom electrode, and this first top electrode is positioned on this first dielectric layer; (c) form one first protective layer, to coat this first electric capacity, this first protective layer comprises several first openings, and these first openings appear this conductive hole structure, this first bottom electrode of part and this first top electrode of part; (d) form a first metal layer on this first protective layer, this first metal layer comprises one first inductance, and this first metal layer directly contacts this conductive hole structure, this first bottom electrode and this first top electrode; Reach and (e) form one second protective layer, to coat this first inductance.
By this, can simplify the technology of this first inductance and this first electric capacity.
The present invention provides a kind of semiconductor package in addition, and it comprises a base material, one first electric capacity, one first protective layer, a first metal layer and one second protective layer.This base material has a first surface, a second surface, at least one groove and at least one perforating holes structure, and this groove runs through this first surface and this second surface, and this perforating holes structure is positioned at this groove, and is revealed in the first surface and the second surface of this base material.This first electric capacity is positioned at the first surface of this base material, and comprise one first bottom electrode, one first dielectric layer and one first top electrode, this first bottom electrode is positioned at the first surface of this base material, and this first dielectric layer is positioned on this first bottom electrode, and this first top electrode is positioned on this first dielectric layer.This first protective layer coats this first electric capacity, and this first protective layer comprises several first openings, and these first openings appear this perforating holes structure, this first bottom electrode of part and this first top electrode of part.This first metal layer is positioned on this first protective layer, and comprises that one first inductance, this first metal layer directly contact this perforating holes structure, this first bottom electrode and this first top electrode.This second protective layer coats this first inductance.
By this, this first inductance, this first electric capacity and this perforating holes structure can be integrated in this semiconductor package in the lump, with the reduction product size.
Description of drawings
Fig. 1 shows the generalized section of known semiconductor encapsulating structure;
Fig. 2 to Figure 21 shows the schematic diagram of first embodiment of the manufacture method of semiconductor package of the present invention;
Figure 22 shows the generalized section of second embodiment of semiconductor package of the present invention;
Figure 23 shows the generalized section of the 3rd embodiment of semiconductor package of the present invention;
Figure 24 to Figure 31 shows the schematic diagram of second embodiment of the manufacture method of semiconductor package of the present invention; And
Figure 32 to Figure 34 shows the schematic diagram of the 3rd embodiment of the manufacture method of semiconductor package of the present invention.
Embodiment
Referring to figs. 2 to Figure 21, the schematic diagram of first embodiment of the manufacture method of demonstration semiconductor package of the present invention.With reference to figure 2, provide a base material 21.In the present embodiment, this base material 21 comprises a first surface 211, a lower surface 212, at least one groove 213 and at least one conductive hole structure 217.This groove 213 is opened on the first surface 211 of this base material 21.This conductive hole structure 217 is positioned at this groove 213, and is revealed in the first surface 211 of this base material 21.
In the present embodiment, the material of this base material 21 is a non-insulating material, for example silicon or silica.This conductive hole structure 217 comprises an external insulation layer 2141, a conductor 2142 and an inner insulating layer 2143.This external insulation layer 2141 is positioned at the sidewall of this groove 213, defines one second central channel 2144, and this conductor 2142 is positioned at the sidewall of this second central channel 2144, defines one first central channel 2145, and this inner insulating layer 2143 fills up this first central channel 2145.Because the material of this base material 21 is a non-insulating material, so this external insulation layer 2141 is avoided branching to this base material 21 by the electric current of this conductive hole structure 217, and reduced the electrical effect of this conductive hole structure 217 in order to isolated this base material 21 and this conductor 2142.
Yet, in other is used, as shown in Figure 3, this conductive hole structure 217 can only comprise an external insulation layer 2141 and a conductor 2142, and do not comprise this inner insulating layer 2143 (Fig. 2), this external insulation layer 2141 is positioned at the sidewall of this groove 213, defines one second central channel 2144, and this conductor 2142 fills up this second central channel 2144.Moreover the material of this base material 21 can be insulating material, glass for example, and then this conductive hole structure 217 can not comprise this external insulation layer 2141 (Fig. 2).Therefore, as shown in Figure 4, this conductive hole structure 217 can only comprise a conductor 2142 and an inner insulating layer 2143, and this conductor 2142 is positioned at the sidewall and the bottom of this groove 213, define one first central channel 2145, this inner insulating layer 2143 fills up this first central channel 2145.Perhaps, as shown in Figure 5, this conductive hole structure 217 only comprises a conductor 2142, and this conductor 2142 fills up this groove 213.With reference to figure 6, form one first insulating bottom layer 22 on this base material 21.In the present embodiment, this first insulating bottom layer 22 is positioned at the first surface 211 of this base material 21, and has one first perforation 221, and this first perforation 221 appears this conductive hole structure 217.Yet, in other is used, can not form this first insulating bottom layer 22.
Then, form one first electric capacity 23 (Figure 10) on this base material 21, this first electric capacity 23 comprises one first bottom electrode 231, one first dielectric layer 232 and one first top electrode 233, this first bottom electrode 231 is positioned on this base material 21, this first dielectric layer 232 is positioned on this first bottom electrode 231, and this first top electrode 233 is positioned on this first dielectric layer 232.In the present embodiment, this first electric capacity 23 is positioned on this first insulating bottom layer 22.In the present embodiment, it is as described below to form the step of this first electric capacity 23.With reference to figure 7, at first, form (for example sputter) one second metal level 234 on this base material 21.The material of this second metal level 234 is aluminum bronze (AlCu).Then, form (for example sputter) one the 3rd metal level on this second metal level 234, and the 3rd metal level is carried out anodic oxidation, to form one first oxide layer 235.The material of the 3rd metal level is that (Tantalum, Ta), the material of this first oxide layer 235 is tantalum pentoxide (Tantalum Pentoxide, Ta to tantalum 2O 5).Then, form (for example sputter) one the 4th metal level 236 on this first oxide layer 235.The material of the 4th metal level 236 is aluminum bronze (AlCu).At last, form one first photoresistance 237 on the 4th metal level 236.With reference to figure 8, remove this first oxide layer 235 (Fig. 7) of part and part the 4th metal level 236 (Fig. 7), forming this first dielectric layer 232 and this first top electrode 233 respectively, and remove this first photoresistance 237 (Fig. 7).With reference to figure 9, form one second photoresistance 238 on this second metal level 234, and coat this first dielectric layer 232 and this first top electrode 233.With reference to Figure 10, remove this second metal level 234 (Fig. 9) of part, forming this first bottom electrode 231, and remove this second photoresistance 238 (Fig. 9), form this first electric capacity 23 simultaneously.With reference to Figure 11, form one first protective layer 24, to coat this first electric capacity 23.This first protective layer 24 comprises several first openings 241, and these first openings 241 appear this conductive hole structure 217, this first bottom electrode 231 of part and this first top electrode 233 of part.
Then, form a first metal layer 25 (Figure 14) on this first protective layer 24.This first metal layer 25 comprises one first inductance 251, and preferably, this first metal layer 25 fills up these first openings 241,255, one second interior connection of metal connects metal 257 in metal 256 and one the 3rd to form to connect in one first.This first interior metal 255 that connects directly contacts this conductive hole structure 217, and this second interior connection metal 256 directly contacts these first bottom electrode, 231, the three interior connection metals 257 and directly contacts this first top electrode 233.In the present embodiment, it is as described below to form the step of this first metal layer 25.With reference to Figure 12, form one first crystal seed layer 252 on this first protective layer 24.With reference to Figure 13, form one the 3rd photoresistance 253 on this first crystal seed layer 252, with this first crystal seed layer 252 of cover part, and appear this first crystal seed layer 252 of part, and form one first electrodeposited coating 254 on quilt this first crystal seed layer 252 of part that appears.With reference to Figure 14, this first crystal seed layer 252 of part that removes the 3rd photoresistance 253 (Figure 13) and be capped, this first electrodeposited coating 254 and part this this first crystal seed layer 252 form this first metal layer 25.With reference to Figure 15, form one second protective layer 26, to coat this first inductance 251.This second protective layer 26 comprises at least one second opening 261, and this second opening 261 appears this first metal layer 25 of part.
Then, form at least one first projection 27 (Figure 18) in second opening 261 of this second protective layer 26.In the present embodiment, it is as described below to form the step of this first projection 27.With reference to Figure 16, form one second crystal seed layer 271 on this second protective layer 26.With reference to Figure 17, form one the 4th photoresistance 272 earlier on this second crystal seed layer 271, with this second crystal seed layer 271 of cover part, and appear this second crystal seed layer 271 of part, form one second electrodeposited coating 273 again on quilt this second crystal seed layer 271 of part that appears.With reference to Figure 18, this second crystal seed layer 271 of part that removes the 4th photoresistance 272 (Figure 17) and be capped is to form this first projection 27.
With reference to Figure 19, this base material 21 is set on a carrier 28, wherein the first surface 211 of this base material 21 is in the face of this carrier 28, and remove this base material 21 of part from the lower surface 212 (Figure 18) of this base material 21, to form a second surface 215, and the conductor 2142 that appears this conductive hole structure 217 (Figure 18) is in this second surface 215, to form a perforating holes structure 214.Yet, in other is used, can remove this base material 21 of more parts again, make the inner insulating layer 2143 of this conductive hole structure 217 (Figure 18) also be revealed in this second surface 215, be revealed in this second surface 215 to guarantee this conductor 2142.
With reference to Figure 20, form the second surface 215 of at least one electrical assembly in this base material 21.In the present embodiment, this electrical assembly is one second projection 31, and the manufacture method of this second projection 31 is with the manufacture method of this first projection 27, so repeat no more.With reference to Figure 21, remove this carrier 28 (Figure 20), form first embodiment of semiconductor package 2 of the present invention.Yet this electrical assembly can be one second inductance 32 and one second electric capacity 33, as shown in figure 22.The manufacture method of this second inductance 32 and this second electric capacity 33, manufacture method with this first inductance 251 and this first electric capacity 23, that is the technology that the technology of being carried out in the second surface 215 of this base material 21 can be carried out with the first surface 211 in this base material 21 is identical, so repeat no more.
By this, can simplify the technology of this first inductance 251 and this first electric capacity 23, and this first inductance 251, this first electric capacity 23 and this perforating holes structure 214 can be integrated in this semiconductor package 2 in the lump, with the reduction product size.
With reference to Figure 21, show the generalized section of first embodiment of semiconductor package of the present invention again.This semiconductor package 2 comprises a base material 21, one first insulating bottom layer 22, one second insulating bottom layer 34, one first electric capacity 23, one first protective layer 24, a first metal layer 25, one second protective layer 26, at least one first projection 27 and at least one electrical assembly.
This base material 21 has a first surface 211, a second surface 215, at least one groove 213 and at least one perforating holes structure 214.This groove 213 runs through this first surface 211 and this second surface 215, and this perforating holes structure 214 is positioned at this groove 213, and is revealed in this first surface 211 and this second surface 215.
In the present embodiment, the material of this base material 21 is a non-insulating material, for example silicon or silica.This perforating holes structure 214 comprises an external insulation layer 2141, a conductor 2142 and an inner insulating layer 2143, this external insulation layer 2141 is positioned at the sidewall of this groove 213, define one second central channel 2144, this conductor 2142 is positioned at the sidewall of this second central channel 2144, define one first central channel 2145, this inner insulating layer 2143 fills up this first central channel 2145.Because the material of this base material 21 is a non-insulating material, so this external insulation layer 2141 is avoided branching to this base material 21 by the electric current of this perforating holes structure 214, and reduced the electrical effect of this perforating holes structure 214 in order to isolated this base material 21 and this conductor 2142.
Yet, in other is used, this perforating holes structure 214 can only comprise an external insulation layer 2141 and a conductor 2142, and do not comprise this inner insulating layer 2143, this external insulation layer 2141 is positioned at the sidewall of this groove 213, define one second central channel 2144, this conductor 2142 fills up this second central channel 2144.Moreover, the material of this base material 21 can be insulating material, glass for example, and then this perforating holes structure 214 can not comprise this external insulation layer 2141, therefore, this perforating holes structure 214 can only comprise a conductor 2142 and an inner insulating layer 2143, and this conductor 2142 is positioned at the sidewall of this groove 213, defines one first central channel 2145, this inner insulating layer 2143 fills up this first central channel 2145, perhaps, this perforating holes structure 214 only comprises a conductor 2142, and this conductor 2142 fills up this groove 213.
This first insulating bottom layer 22 is positioned at the first surface 211 of this base material 21, and has one first perforation 221, and this first perforation 221 appears this perforating holes structure 214.This second insulating bottom layer 34 is positioned at the second surface 215 of this base material 21, and has one second perforation 341, and this second perforation 341 appears this perforating holes structure 214.This first electric capacity 23 is positioned on this first insulating bottom layer 22, and comprise one first bottom electrode 231, one first dielectric layer 232 and one first top electrode 233, this first bottom electrode 231 is positioned on this first insulating bottom layer, this first dielectric layer 232 is positioned on this first bottom electrode 231, and this first top electrode 233 is positioned on this first dielectric layer 232.In the present embodiment, the material of this first bottom electrode 231 and this first top electrode 233 is aluminum bronze (AlCu), and the material of this first dielectric layer 232 is tantalum pentoxide (Tantalum Pentoxide, Ta 2O 5).
This first protective layer 24 coats this first electric capacity 23.In the present embodiment, this first protective layer 24 comprises several first openings 241, and these first openings 241 appear this perforating holes structure 214, this first bottom electrode 231 of part and this first top electrode 233 of part.This first metal layer 25 is positioned on first protective layer 24; and comprise one first inductance 251; preferably, be positioned at this first metal layer 25 formation one first connection metal 255 of part, one second connection metal 256 and one the 3rd connection metal 257 of these first openings 241.This first interior metal 255 that connects directly contacts this perforating holes structure 214, and this second interior connection metal 256 directly contacts these first bottom electrode, 231, the three interior connection metals 257 and directly contacts this first top electrode 233.This second protective layer 26 coats this first inductance 251.In the present embodiment, this second protective layer 26 comprises at least one second opening 261, and this second opening 261 appears this first metal layer 25 of part.This first projection 27 is positioned at second opening 261 of this second protective layer 26.This electrical assembly is positioned at the second surface 215 of this base material 21.This electrical assembly is one second projection 31.
By this, this first inductance 251, this first electric capacity 23 and this perforating holes structure 214 can be integrated in this semiconductor package 2 in the lump, with the reduction product size.
With reference to Figure 22, show the generalized section of second embodiment of semiconductor package of the present invention.The semiconductor package 2 (Figure 21) of the semiconductor package 3 of present embodiment and first embodiment is roughly the same, and wherein identical assembly is given identical numbering.Present embodiment and first embodiment different be in, in the present embodiment, the second surface 215 of this semiconductor package 3 comprises several electrical assemblies (for example one second inductance 32, one second electric capacity 33 and one second projection 31).
With reference to Figure 23, show the generalized section of the 3rd embodiment of semiconductor package of the present invention.The semiconductor package 2 (Figure 21) of the semiconductor package 4 of present embodiment and first embodiment is roughly the same, and wherein identical assembly is given identical numbering.Present embodiment and first embodiment different be in, in the present embodiment, this semiconductor package 3 does not comprise this first insulating bottom layer 22 and this second insulating bottom layer 34, preferably, this first electric capacity 23 is positioned at the first surface 211 of this base material 21.
With reference to Figure 24 to Figure 31, the schematic diagram of second embodiment of the manufacture method of demonstration semiconductor package of the present invention.With reference to Figure 24, provide a base material 21.In the present embodiment, this base material 21 has a upper surface 216 and a second surface 215, and this groove 213 is opened on the second surface 215 of this base material 21, and this conductive hole structure 217 is revealed in the second surface 215 of this base material 21.With reference to Figure 25, form one second insulating bottom layer 34 on this base material 21.In the present embodiment, this second insulating bottom layer 34 is positioned at the second surface 215 of this base material 21, and has one second perforation 341, and this second perforation 341 appears this conductive hole structure 217.Then, form the second surface 215 of at least one electrical assembly in this base material 21, preferably, be positioned on this second insulating bottom layer 34, in the present embodiment, this electrical assembly is one second projection 31.With reference to Figure 26, this base material 21 is set on a carrier 28, wherein the second surface 215 of this base material 21 is in the face of this carrier 28, and remove this base material 21 of part from the upper surface 216 (Figure 25) of this base material 21, to form a first surface 211, and appear this conductive hole structure 217 (Figure 25) in this first surface 211, to form a perforating holes structure 217.
With reference to Figure 27, form one first electric capacity 23 on this base material 21, this first electric capacity 23 comprises one first bottom electrode 231, one first dielectric layer 232 and one first top electrode 233, this first bottom electrode 231 is positioned on this base material 21, this first dielectric layer 232 is positioned on this first bottom electrode 231, and this first top electrode 233 is positioned on this first dielectric layer 232.In the present embodiment, this first electric capacity 23 is positioned on this first insulating bottom layer 22.With reference to Figure 28, form one first protective layer 24, to coat this first electric capacity 23.This first protective layer 24 comprises several first openings 241, and these first openings 241 appear this first top electrode 233 of part.With reference to Figure 29, form a first metal layer 25 on this first protective layer 24.One first electrodeposited coating 254 and one first crystal seed layer 252 form this first metal layer 25.This first metal layer 25 comprises one first inductance 251, and preferably, this first metal layer 25 fills up these first openings 241,255, one second interior connection of metal connects metal 257 in metal 256 and one the 3rd to form to connect in one first.This first interior metal 255 that connects directly contacts this perforating holes structure 214, and this second interior connection metal 256 directly contacts these first bottom electrode, 231, the three interior connection metals 257 and directly contacts this first top electrode 233.With reference to Figure 30, form one second protective layer 26, to coat this first inductance 251.This second protective layer 26 comprises at least one second opening 261, and this second opening 261 appears this first metal layer 25 of part.With reference to Figure 31, form at least one first projection 27 in second opening 261 of this second protective layer 26, one second electrodeposited coating 273 and one second crystal seed layer 271 form this first projection 27.Then, remove this carrier 28, form first embodiment of semiconductor package 2 of the present invention.
With reference to Figure 32 to Figure 34, the schematic diagram of the 3rd embodiment of the manufacture method of demonstration semiconductor package of the present invention.The manufacture method (Fig. 2 to Figure 21) of the semiconductor package of the manufacture method of the semiconductor package of present embodiment and first embodiment is roughly the same, and wherein identical assembly is given identical numbering.Present embodiment is different with first embodiment be in, with reference to Figure 32, when a base material 21 is provided, this base material 21 has a first surface 211, a second surface 215, at least one groove 213 and at least one conductive hole structure, this groove 213 runs through this first surface 211 and this second surface 215, this conductive hole structure is positioned at this groove 213, and is revealed in this first surface 211 and this second surface 215, to form a perforating holes structure 214.Then, with reference to Figure 33, prior to first surface 211 formation one first inductance 251 and one first electric capacity 23 of this base material 21.With reference to Figure 34, the second surface 215 in this base material 21 forms at least one electrical assembly again, and forms first embodiment of semiconductor package of the present invention simultaneously.Yet, in other is used, also can form this electrical assembly prior to the second surface 215 of this base material 21, the first surface 211 in this base material 21 forms this first inductance 251 and this first electric capacity 23 again.
Only the foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, practise the foregoing description being made amendment and changing and still do not take off spirit of the present invention in the personage of this technology.Interest field of the present invention should be listed as claims.

Claims (22)

1.一种半导体封装结构的制造方法，包括：1. A method for manufacturing a semiconductor package structure, comprising: (a)提供一基材，该基材包括至少一沟槽及至少一导电孔结构，该导电孔结构位于该沟槽内；(a) providing a substrate, the substrate includes at least one groove and at least one conductive hole structure, and the conductive hole structure is located in the groove; (b)形成一第一电容于该基材上，该第一电容包括一第一下电极、一第一介电层及一第一上电极，该第一下电极位于该基材上，该第一介电层位于该第一下电极上，该第一上电极位于该第一介电层上；(b) forming a first capacitor on the substrate, the first capacitor includes a first lower electrode, a first dielectric layer and a first upper electrode, the first lower electrode is located on the substrate, the a first dielectric layer is located on the first lower electrode, and the first upper electrode is located on the first dielectric layer; (c)形成一第一保护层，以包覆该第一电容，该第一保护层包括数个第一开口，该等第一开口显露该导电孔结构、部分该第一下电极及部分该第一上电极；(c) forming a first protective layer to cover the first capacitor, the first protective layer includes a plurality of first openings, and the first openings reveal the conductive hole structure, part of the first lower electrode and part of the first upper electrode; (d)形成一第一金属层于该第一保护层上，该第一金属层包括一第一电感，且直接接触该导电孔结构、该第一下电极及该第一上电极；及(d) forming a first metal layer on the first protective layer, the first metal layer includes a first inductor, and directly contacts the conductive hole structure, the first lower electrode and the first upper electrode; and (e)形成一第二保护层，以包覆该第一电感。(e) forming a second protection layer to cover the first inductor. 2.如权利要求1的方法，其中该步骤(a)中，该基材具有一第一表面及一第二表面，该沟槽贯穿该基材的第一表面及第二表面，且该导电孔结构显露于该基材的第一表面及第二表面，以形成一穿导孔结构，该步骤(b)中，该第一电容位于该基材的第一表面。2. The method according to claim 1, wherein in the step (a), the substrate has a first surface and a second surface, the groove runs through the first surface and the second surface of the substrate, and the conductive The hole structure is exposed on the first surface and the second surface of the substrate to form a through hole structure. In the step (b), the first capacitor is located on the first surface of the substrate. 3.如权利要求1的方法，其中该步骤(a)中，该基材具有一第一表面及一下表面，该沟槽开口于该基材的第一表面，且该导电孔结构显露于该基材的第一表面，该步骤(b)中，该第一电容位于该基材的第一表面。3. The method according to claim 1, wherein in the step (a), the substrate has a first surface and a lower surface, the groove is opened on the first surface of the substrate, and the conductive hole structure is exposed on the substrate. The first surface of the substrate, in the step (b), the first capacitor is located on the first surface of the substrate. 4.如权利要求3的方法，其中该步骤(e)之后，更包括：4. The method of claim 3, wherein after the step (e), further comprising: (f)设置该基材于一载体上，其中该基材的第一表面面对该载体；(f) disposing the substrate on a carrier, wherein the first surface of the substrate faces the carrier; (g)从该基材的下表面移除部分该基材，以形成一第二表面，且显露该导电孔结构于该第二表面，以形成一穿导孔结构；(g) removing part of the substrate from the lower surface of the substrate to form a second surface, and exposing the conductive hole structure on the second surface to form a through hole structure; (h)形成至少一电性组件于该基材的第二表面；及(h) forming at least one electrical component on the second surface of the substrate; and (i)移除该载体。(i) Remove the carrier. 5.如权利要求1的方法，其中该步骤(a)中，该基材具有一上表面及一第二表面，该沟槽开口于该基材的第二表面，且该导电孔结构显露于该基材的第二表面。5. The method according to claim 1, wherein in the step (a), the substrate has an upper surface and a second surface, the groove is opened on the second surface of the substrate, and the conductive hole structure is exposed on the second surface of the substrate. 6.如权利要求5的方法，其中该步骤(a)之后，更包括：6. The method of claim 5, wherein after the step (a), further comprising: (a1)形成至少一电性组件于该基材的第二表面；(a1) forming at least one electrical component on the second surface of the substrate; (a2)设置该基材于一载体上，其中该基材的第二表面面对该载体；及(a2) disposing the substrate on a carrier, wherein the second surface of the substrate faces the carrier; and (a3)从该基材的上表面移除部分该基材，以形成一第一表面，且显露该导电孔结构于该第一表面，以形成一穿导孔结构。(a3) removing part of the substrate from the upper surface of the substrate to form a first surface, and exposing the conductive hole structure on the first surface to form a through hole structure. 7.如权利要求6的方法，其中该步骤(b)中，该第一电容位于该基材的第一表面。7. The method of claim 6, wherein in the step (b), the first capacitor is located on the first surface of the substrate. 8.如权利要求6的方法，其中该步骤(e)之后，更包括一移除该载体的步骤。8. The method of claim 6, further comprising a step of removing the carrier after the step (e). 9.如权利要求1的方法，其中该步骤(b)包括：9. The method of claim 1, wherein the step (b) comprises: (b1)形成一第二金属层于该基材上；(b1) forming a second metal layer on the substrate; (b2)形成一第三金属层于该第二金属层上，并对该第三金属层进行阳极氧化，以形成一第一氧化层；(b2) forming a third metal layer on the second metal layer, and anodizing the third metal layer to form a first oxide layer; (b3)形成一第四金属层于该第一氧化层上；(b3) forming a fourth metal layer on the first oxide layer; (b4)形成一第一光阻于该第四金属层上；(b4) forming a first photoresist on the fourth metal layer; (b5)移除部分该第一氧化层及部分该第四金属层，以分别形成该第一介电层及该第一上电极；(b5) removing part of the first oxide layer and part of the fourth metal layer to form the first dielectric layer and the first upper electrode respectively; (b6)移除该第一光阻；(b6) removing the first photoresist; (b7)形成一第二光阻于该第二金属层上，且包覆该第一介电层及该第一上电极；(b7) forming a second photoresist on the second metal layer and covering the first dielectric layer and the first upper electrode; (b8)移除部分该第二金属层，以形成该第一下电极；及(b8) removing part of the second metal layer to form the first bottom electrode; and (b9)移除该第二光阻。(b9) removing the second photoresist. 10.如权利要求1的方法，其中该步骤(d)包括：10. The method of claim 1, wherein the step (d) comprises: (d1)形成一第一晶种层于该第一保护层上；(d1) forming a first seed layer on the first protection layer; (d2)形成一第三光阻于该第一晶种层上，以覆盖部分该第一晶种层，且显露部分该第一晶种层；(d2) forming a third photoresist on the first seed layer to cover part of the first seed layer and expose part of the first seed layer; (d3)形成一第一电镀层于被显露的部分该第一晶种层上；及(d3) forming a first electroplating layer on the exposed portion of the first seed layer; and (d4)移除该第三光阻及被覆盖的部分该第一晶种层，该第一电镀层及部分该第一晶种层形成该第一金属层。(d4) removing the third photoresist and the covered part of the first seed layer, the first electroplating layer and part of the first seed layer forming the first metal layer. 11.一种半导体封装结构，包括：11. A semiconductor packaging structure, comprising: 一基材，具有一第一表面、一第二表面、至少一沟槽及至少一穿导孔结构，该沟槽贯穿该第一表面及该第二表面，该穿导孔结构位于该沟槽内，且显露于该基材的第一表面及第二表面；A substrate having a first surface, a second surface, at least one groove and at least one through-hole structure, the groove runs through the first surface and the second surface, and the through-hole structure is located in the groove within, and exposed on the first surface and the second surface of the substrate; 一第一电容，位于该基材的第一表面，且包括一第一下电极、一第一介电层及一第一上电极，该第一下电极位于该基材的第一表面，该第一介电层位于该第一下电极上，该第一上电极位于该第一介电层上；A first capacitor is located on the first surface of the base material, and includes a first lower electrode, a first dielectric layer and a first upper electrode, the first lower electrode is located on the first surface of the base material, the a first dielectric layer is located on the first lower electrode, and the first upper electrode is located on the first dielectric layer; 一第一保护层，包覆该第一电容，该第一保护层包括数个第一开口，该等第一开口显露该穿导孔结构、部分该第一下电极及部分该第一上电极；A first protective layer covering the first capacitor, the first protective layer includes a plurality of first openings, and the first openings expose the through hole structure, part of the first lower electrode and part of the first upper electrode ; 一第一金属层，位于该第一保护层上，且包括一第一电感，该第一金属层直接接触该穿导孔结构、该第一下电极及该第一上电极；及a first metal layer, located on the first protective layer, and including a first inductor, the first metal layer directly contacts the through-via structure, the first lower electrode, and the first upper electrode; and 一第二保护层，包覆该第一电感。A second protection layer covers the first inductor. 12.如权利要求11的封装结构，其中该基材的材质为玻璃、硅或氧化硅。12. The package structure according to claim 11, wherein the material of the substrate is glass, silicon or silicon oxide. 13.如权利要求11的封装结构，其中该穿导孔结构包括一导体，该导体填满该沟槽。13. The package structure of claim 11, wherein the through via structure comprises a conductor, and the conductor fills up the trench. 14.如权利要求11的封装结构，其中该穿导孔结构包括一导体及一内绝缘层，该导体位于该沟槽的侧壁，定义出一第一中心槽，该内绝缘层填满该第一中心槽。14. The packaging structure according to claim 11, wherein the through via structure comprises a conductor and an inner insulating layer, the conductor is located on the sidewall of the trench, defines a first central groove, and the inner insulating layer fills up the First center slot. 15.如权利要求11的封装结构，其中该穿导孔结构包括一外绝缘层及一导体，该外绝缘层位于该沟槽的侧壁，定义出一第二中心槽，该导体填满该第二中心槽。15. The packaging structure according to claim 11, wherein the TSV structure comprises an outer insulating layer and a conductor, the outer insulating layer is located on the sidewall of the trench, defines a second central slot, and the conductor fills the Second center slot. 16.如权利要求11的封装结构，其中该穿导孔结构包括一外绝缘层、一导体及一内绝缘层，该外绝缘层位于该沟槽的侧壁，定义出一第二中心槽，该导体位于该第二中心槽的侧壁，定义出一第一中心槽，该内绝缘层填满该第一中心槽。16. The package structure according to claim 11, wherein the through via structure comprises an outer insulating layer, a conductor and an inner insulating layer, the outer insulating layer is located on the sidewall of the trench to define a second central slot, The conductor is located on the sidewall of the second central groove, defines a first central groove, and the inner insulating layer fills up the first central groove. 17.如权利要求11的封装结构，其中该第一下电极直接接触该基材的第一表面。17. The package structure of claim 11, wherein the first bottom electrode directly contacts the first surface of the substrate. 18.如权利要求11的封装结构，更包括一第一绝缘底层，位于该基材的第一表面，且具有一第一穿孔，该第一穿孔显露该导电孔结构，该第一电容位于该第一绝缘底层上，该第一下电极位于该第一绝缘底层上。18. The packaging structure according to claim 11, further comprising a first insulating bottom layer located on the first surface of the substrate and having a first through hole, the first through hole reveals the conductive hole structure, the first capacitor is located on the first surface of the substrate On the first insulating bottom layer, the first lower electrode is located on the first insulating bottom layer. 19.如权利要求11的封装结构，其中该第一金属层更包括一第一内连接金属、一第二内连接金属及一第三内连接金属，该第一内连接金属直接接触该穿导孔结构，该第二内连接金属直接接触该第一下电极，该第三内连接金属直接接触该第一上电极。19. The package structure of claim 11, wherein the first metal layer further comprises a first interconnection metal, a second interconnection metal and a third interconnection metal, the first interconnection metal directly contacts the via hole structure, the second interconnection metal directly contacts the first lower electrode, and the third interconnection metal directly contacts the first upper electrode. 20.如权利要求11的封装结构，其中该第二保护层包括至少一第二开口，该第二开口显露部分该第一金属层。20. The package structure of claim 11, wherein the second passivation layer comprises at least one second opening exposing a portion of the first metal layer. 21.如权利要求20的封装结构，更包括至少一第一凸块，位于该第二保护层的第二开口内。21. The package structure of claim 20, further comprising at least one first bump located in the second opening of the second passivation layer. 22.如权利要求11的封装结构，更包括至少一电性组件，位于该基材的第二表面，其中该电性组件为一第二电感、一第二电容或一第二凸块。22. The package structure of claim 11, further comprising at least one electrical component located on the second surface of the substrate, wherein the electrical component is a second inductor, a second capacitor or a second bump.
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