CN102130005A - Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface - Google Patents
Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface Download PDFInfo
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- CN102130005A CN102130005A CN2010100273335A CN201010027333A CN102130005A CN 102130005 A CN102130005 A CN 102130005A CN 2010100273335 A CN2010100273335 A CN 2010100273335A CN 201010027333 A CN201010027333 A CN 201010027333A CN 102130005 A CN102130005 A CN 102130005A
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Abstract
The invention discloses a preparation method of a trench PMOS (positive-channel metal oxide semiconductor) enabling the side wall of a trench to be the (110) surface, which comprises the following steps: enabling the side wall surface of the trench after etching to be the (110) crystal surface when defining a trench pattern on a substrate through the photoetching process; injecting nitrogen ions into the inner wall of the trench after forming the trench by etching; and then growing a gate oxide on the inner wall of the trench. By adopting the method, the threshold voltage of the PMOS device can be effectively reduced to achieve the application requirement.
Description
Technical field
The present invention relates to the preparation method of a kind of groove PMOS, be specifically related to a kind of groove type MOS preparation of devices method of tool vertical trench.
Background technology
(see figure 1) in existing groove MOSFET device, many (100) faces that trenched side-wall is designed to of the preparation of groove-shaped PMOS.The interface state density that because of trenched side-wall is the device grid oxygen of groove PMOS of (110) face and sidewall makes threshold voltage higher more than the height of sidewall for (100) face, can't satisfy the needs of practical application.Therefore, industry is general is the preparation of the groove PMOS of (100) face with the design trenched side-wall only.But the mobility of edge, majority carrier hole (110) crystal face is far above its mobility along (110) crystal face among the PMOS.If therefore trenched side-wall can lower for the device threshold voltage of the groove PMOS of (110) face, its on state resistance can be little more a lot of than the PMOS that same size trenched side-wall is (100) under the identical situation of other device parameters, thereby can reduce size of devices greatly under the identical situation of device performance.
Summary of the invention
Technical problem to be solved by this invention provides the preparation method of a kind of trenched side-wall for the groove PMOS of (110) face, and it can effectively reduce the threshold voltage of groove-shaped PMOS.
For solving the problems of the technologies described above, trenched side-wall of the present invention is the preparation method of the groove PMOS of (110) face, and for when defining groove figure by photoetching process on substrate, making the channel side wall after the etching is (110) crystal face; And after etching forms groove, at the trench wall injecting nitrogen ion; Afterwards at trench wall growth grid oxygen.
The technique effect that the present invention can reach is: by at trenched side-wall in the PMOS device of (110) face, before the growth grid oxygen trench wall being carried out nitrogen injects, can reduce the interfacial state between grid oxygen and trenched side-wall greatly, thereby effectively reduce the threshold voltage of groove PMOS device, make that device size reduces greatly under the identical situation of performance, cost reduces greatly.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of traditional groove MOS device;
Fig. 2 is for implementing the structural representation of the prepared groove MOS device of method of the present invention;
Fig. 3 is the structural representation behind the etching groove in the method for the present invention;
Fig. 4 is the schematic diagram that nitrogen injects in the method for the present invention;
Fig. 5 is that grid form structural representation afterwards in the method for the present invention.
Embodiment
Trenched side-wall of the present invention is the preparation method of the groove PMOS of (110) face, the used substrate surface of this MOS device is (100) crystal face, and the side wall surface of groove is designed to (110) face, when defining groove figure by photoetching process on substrate, making the channel side wall after the etching is (110) crystal face; And after etching forms groove, at the trench wall injecting nitrogen ion; Afterwards at the trench wall of injecting nitrogen ion growth grid oxygen.The nitrogen ion that injects makes the suspension key of trenched side-wall and grid oxygen interface reduce greatly, thereby makes interfacial state reduce greatly, and therefore threshold voltage reduces and accurately controlled easily.PMOS majority carrier hole along the mobility of (110) crystal face more than along 110) height of the mobility of crystal face, make under the identical situation of other device performance of same size with (110) to be that the PMOS on state resistance of trenched side-wall is much smaller than being the PMOS on state resistance of trenched side-wall with (100).Therefore under the on state resistance situation identical with other device performance, the size of the groove PMOS of the present invention's preparation reduces greatly than conventional groove PMOS.
Concrete preparation flow is:
1) chooses the surface and be the substrate of (100) crystal face, make substrate breach (notch) direction be (110); During photoetching, make the groove bearing of trend along the notch direction, dotted line as shown in Figure 2 is a trenched side-wall, between two dotted lines be the etching of wanting form the position of groove, be arranged so that like this channel side wall after the etched substrate is (110) crystal face.Adopt the standard technology etching to form the groove (see figure 3);
2) then carry out the nitrogen ion and be injected into trenched side-wall and the channel bottom (see figure 4) of crystal plane direction for (110).In the nitrogen implantation step, the nitrogen ion implantation energy is: 1Kev～200Kev, the angular range of ion beam and substrate vertical axis is during injection: 1～85 °.Also can carry out annealing in process after injecting, the temperature of annealing in process is 300～1200 ℃, and the processing time is: 1 second-10 hours.
3) then carry out conventional gate oxide growth, polysilicon deposit and time quarter form the grid (see figure 5), and the tagma is injected, the source region is injected and follow-up metallization process, finally formation groove-shaped PMOS transistor arrangement as shown in Figure 1.
Method of the present invention, trenched side-wall are set to (110) face, add that between gate oxide growth trench wall being carried out nitrogen injects, and the interface state density of final PMOS device is reduced, and have also kept the advantage of (110) crystal face high hole mobility simultaneously.Through evidence, can effectively reduce the threshold voltage of PMOS device, be enough to satisfy practical application.
Claims (4)
1. preparation method that trenched side-wall is the groove PMOS of (110) face is characterized in that: when defining groove figure by photoetching process on substrate, making the channel side wall after the etching is (110) crystal face; And after etching forms groove, at described trench wall injecting nitrogen ion; Afterwards at described trench wall growth grid oxygen.
2. preparation method according to claim 1 is characterized in that: the breach direction of described substrate is (110).
3. preparation method according to claim 1 is characterized in that: in the described nitrogen implantation step, the nitrogen ion implantation energy is: 1Kev～200Kev, the angular range of ion beam and substrate vertical axis is during injection: 1～85 °.
4. preparation method according to claim 1 is characterized in that: also be included in the step of carrying out annealing in process after the injection, the temperature of described annealing in process is 300～1200 ℃, and the processing time is: 1 second-10 hours.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100273335A CN102130005A (en) | 2010-01-20 | 2010-01-20 | Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010100273335A CN102130005A (en) | 2010-01-20 | 2010-01-20 | Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface |
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| CN102130005A true CN102130005A (en) | 2011-07-20 |
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| CN2010100273335A Pending CN102130005A (en) | 2010-01-20 | 2010-01-20 | Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241340A (en) * | 2014-10-11 | 2014-12-24 | 王金 | Trench MOS (metal oxide semiconductor) unit and production method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235959A1 (en) * | 2002-06-25 | 2003-12-25 | Siliconix Incorporated | Self-aligned differential oxidation in trenches by ion implantation |
| CN101336483A (en) * | 2005-12-22 | 2008-12-31 | 维西埃-硅化物公司 | High mobility power metal-oxide semiconductor field-effect transistors |
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2010
- 2010-01-20 CN CN2010100273335A patent/CN102130005A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235959A1 (en) * | 2002-06-25 | 2003-12-25 | Siliconix Incorporated | Self-aligned differential oxidation in trenches by ion implantation |
| CN101336483A (en) * | 2005-12-22 | 2008-12-31 | 维西埃-硅化物公司 | High mobility power metal-oxide semiconductor field-effect transistors |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241340A (en) * | 2014-10-11 | 2014-12-24 | 王金 | Trench MOS (metal oxide semiconductor) unit and production method thereof |
| CN104241340B (en) * | 2014-10-11 | 2019-12-10 | 深圳市威兆半导体有限公司 | Groove MOS unit and preparation method thereof |
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Application publication date: 20110720 |