CN102129992B - Method for improving impurity concentration distribution of impurity injection type polysilicon emitter - Google Patents
Method for improving impurity concentration distribution of impurity injection type polysilicon emitter Download PDFInfo
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- CN102129992B CN102129992B CN 201010027290 CN201010027290A CN102129992B CN 102129992 B CN102129992 B CN 102129992B CN 201010027290 CN201010027290 CN 201010027290 CN 201010027290 A CN201010027290 A CN 201010027290A CN 102129992 B CN102129992 B CN 102129992B
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Abstract
The invention discloses a method for improving the impurity concentration distribution of an impurity injection type polysilicon emitter, comprising the following steps of: firstly, forming a base electrode and then depositing a polysilicon emitter-base electrode isolated dielectric layer, wherein the isolated dielectric layer is in a sandwich structure and amorphous silicon heavily-doped with an N type impurity is arranged on an intermediate layer; secondly, etching the isolated dielectric layer to form an emitter-base electrode contact window; thirdly, depositing non-doped polysilicon serving as an emitter of a bipolar transistor; fourthly, defining an polysilicon ion-injected photoetching layer of the emitter and carrying out polysilicon N type impurity injection on the emitter; and fifthly, carrying out quick annealing at a high temperature to allow impurities of the polysilicon to transversely diffuse and forming an impurity concentration increasing area above the polysilicon, which is close to the emitter-base electrode contact window. According to the method, the injection efficiency of the polysilicon emitter can be effectively improved, the current gain is increased and the resistance is reduced.
Description
Technical field
The present invention relates to integrated circuit and make the field, be specifically related to a kind of method of improving the polysilicon emitter impurities concentration distribution.
Background technology
Polysilicon emitter now has been widely used in the conventional bipolar transistor (BipolarTransistor).In most of the cases, during polycrystalline silicon growth, doped N-type impurity simultaneously in place forms the emitter of NPN bipolar transistor.But, some special bipolar-preparation of field-effect transistor (BiCMOS) in, need the technique of CMOS compatible and some passive devices, therefore, the polysilicon that needs the non-doping of growth in the flow process afterwards, injects N-type impurity with the mode of Implantation toward the polysilicon the inside again.
Because the polysilicon Implantation can only be injected into a specific degree of depth, and can not be excessively dark, enters base stage with the anti-penetration emitter, generally injects the degree of depth and will guarantee more than 1500A from the polysilicon of emitter/base and the interface of monocrystalline silicon.Therefore, impurity injection type polysilicon emitter is compared with doping type polysilicon emitter in place, the skewness of its impurity concentration in polysilicon, and lower at the relative concentration of the interface of polysilicon and monocrystalline silicon.
This structure as shown in Figure 1, mainly comprise substrate (101), symmetrical buried regions (102), isolation (103), collector region (108), intrinsic base region (107), low-resistance outer base area (104), polycrystal emitter (106), emitter-base isolation dielectric layer (105).
Summary of the invention
Technical problem to be solved by this invention provides a kind of method of improving the impurity injection type polysilicon emitter impurities concentration distribution, and the injection efficiency that it can the Effective Raise polysilicon emitter increases current gain, reduces resistance.
In order to solve above technical problem, the invention provides a kind of method of improving the impurity injection type polysilicon emitter impurities concentration distribution; May further comprise the steps: step 1, the base stage that forms, depositing polysilicon emitter-base isolation dielectric layer then, described spacer medium layer is sandwich structure, the attach most importance to unformed silicon of doped N-type impurity of middle one deck; Step 2, etching spacer medium layer form emitter-base stage contact window; The polysilicon of step 3, the non-doping of deposit is as the emitter of bipolar transistor; The lithography layer of step 4, definition emitter-polysilicon Implantation carries out emitter-polysilicon N-type Impurity injection; Step 5, carry out high temperature rapid thermal annealing, make the impurity horizontal proliferation of polysilicon, form impurity concentration at polysilicon near the zone above emitter-base stage contact window and increase the zone.
Beneficial effect of the present invention is: the injection efficiency of energy Effective Raise polysilicon emitter, increase current gain (Beta), and reduce resistance.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is conventional polysilicon emitter NPN transistor vertical structure schematic diagram;
Fig. 2 is the un-doped polysilicon emitter NPN transistor vertical structure schematic diagram that the described method of the embodiment of the invention forms;
Fig. 3 is the flow chart of the described method of the embodiment of the invention.
Embodiment
As shown in Figure 3, concrete steps of the present invention comprise:
1. formation base stage, then depositing polysilicon emitter/base spacer medium layer (205).This spacer medium layer is with the structure of sandwich, and middle one deck is with the unformed silicon of heavy doping N-type impurity, the two-layer oxide-film of using up and down, and nitrogen oxidation film all can.The layer dielectric thickness of spacer medium layer: 100A ~ 400A; The thickness of the unformed silicon of doping: 500A ~ 1500A in the middle of the spacer medium layer is heavy.Unformed silicon doping concentration wherein: arsenic or boron 1e20/cm3 ~ 1.4e21/cm3.
2. dry method+wet etching spacer medium layer (205) forms emitter-base stage contact window.
3. the polysilicon of the non-doping of deposit (206) is as the emitter of bipolar transistor.
4. the lithography layer of definition emitter-polysilicon Implantation carries out emitter-polysilicon (206) N-type Impurity injection.
5. in the high temperature rapid thermal annealing step, make the impurity horizontal proliferation of polysilicon, form impurity concentration addition zone (209) at polysilicon near the zone above emitter-base stage contact window.And it is more evenly distributed in polysilicon, the impurity concentration of the interface of the polysilicon of emitter/base contact window and intrinsic base region (207) is higher.
As shown in Figure 2, the structure that the method for the invention forms mainly comprises substrate (201), buried regions (202), isolation (203), collector region (208), intrinsic base region (207), low-resistance outer base area (204), polycrystal emitter (206), emitter-base stage sandwich structure spacer medium layer (205), impurity horizontal proliferation zone (209).
One deck was with the sandwich structure of the unformed silicon of heavy doping N-type impurity, as the spacer medium layer of polysilicon emitter/base stage in the middle of the method for the invention formed.The wherein horizontal proliferation of the heavy doping impurity in the unformed silicon makes it form the impurity concentration addition at polysilicon near the zone above the emitter/base contact window, and makes its impurities concentration distribution at polysilicon more even.
The present invention is not limited to execution mode discussed above.Above description to embodiment is intended in order to describe and illustrate the technical scheme that the present invention relates to.Based on the apparent conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches purpose of the present invention.
Claims (6)
1. method of improving the impurity injection type polysilicon emitter impurities concentration distribution; It is characterized in that, may further comprise the steps:
Step 1, the base stage that forms, depositing polysilicon emitter-base isolation dielectric layer then, described spacer medium layer is sandwich structure, the attach most importance to unformed silicon of doped N-type impurity of middle one deck;
Step 2, etching spacer medium layer form emitter-base stage contact window;
The polysilicon of step 3, the non-doping of deposit is as the emitter of bipolar transistor;
The lithography layer of step 4, definition emitter-polysilicon Implantation carries out emitter-polysilicon N-type Impurity injection;
Step 5, carry out high temperature rapid thermal annealing, make the impurity horizontal proliferation of polysilicon, form impurity concentration at polysilicon near the zone above emitter-base stage contact window and increase the zone.
2. the method for improving the impurity injection type polysilicon emitter impurities concentration distribution as claimed in claim 1; The two-layer up and down of the spacer medium layer of a kind of described sandwich structure of step is oxide-film or nitrogen oxidation film.
3. the method for improving the impurity injection type polysilicon emitter impurities concentration distribution as claimed in claim 2; It is characterized in that, it is characterized in that, the layer dielectric thickness of the layer of spacer medium described in the step 1 is 100 dusts ~ 400 dusts.
4. the method for improving the impurity injection type polysilicon emitter impurities concentration distribution as claimed in claim 1; It is characterized in that, the thickness of the unformed silicon that mixes in the middle of the layer of spacer medium described in the step 1 is 500 dusts ~ 1500 dusts.
5. the method for improving the impurity injection type polysilicon emitter impurities concentration distribution as claimed in claim 1; It is characterized in that, unformed silicon doping element is arsenic or boron described in the step 1.
6. the method for improving the impurity injection type polysilicon emitter impurities concentration distribution as claimed in claim 5; It is characterized in that, the arsenic of unformed silicon doping described in the step 1 or the concentration of boron are 1e20/cm
3～1.4e21/cm
3
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365479B1 (en) * | 2000-09-22 | 2002-04-02 | Conexant Systems, Inc. | Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure |
| US6482710B2 (en) * | 1999-10-14 | 2002-11-19 | Hitachi, Ltd. | Bipolar transistor and manufacting method thereof |
| CN101233604A (en) * | 2005-08-03 | 2008-07-30 | Nxp股份有限公司 | Semiconductor device and method of manufacturing such a device |
| CN101257042A (en) * | 2006-09-28 | 2008-09-03 | 三洋电机株式会社 | Semiconductor device |
| CN101599435A (en) * | 2009-07-24 | 2009-12-09 | 上海宏力半导体制造有限公司 | The doping method of single-layer polycrystalline silicon HBT extrinsic base region |
-
2010
- 2010-01-18 CN CN 201010027290 patent/CN102129992B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482710B2 (en) * | 1999-10-14 | 2002-11-19 | Hitachi, Ltd. | Bipolar transistor and manufacting method thereof |
| US6365479B1 (en) * | 2000-09-22 | 2002-04-02 | Conexant Systems, Inc. | Method for independent control of polycrystalline silicon-germanium in a silicon-germanium HBT and related structure |
| CN101233604A (en) * | 2005-08-03 | 2008-07-30 | Nxp股份有限公司 | Semiconductor device and method of manufacturing such a device |
| CN101257042A (en) * | 2006-09-28 | 2008-09-03 | 三洋电机株式会社 | Semiconductor device |
| CN101599435A (en) * | 2009-07-24 | 2009-12-09 | 上海宏力半导体制造有限公司 | The doping method of single-layer polycrystalline silicon HBT extrinsic base region |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |