CN102129880A - Three-dimensional chip selection sharing input package - Google Patents
Three-dimensional chip selection sharing input package Download PDFInfo
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- CN102129880A CN102129880A CN2010100040123A CN201010004012A CN102129880A CN 102129880 A CN102129880 A CN 102129880A CN 2010100040123 A CN2010100040123 A CN 2010100040123A CN 201010004012 A CN201010004012 A CN 201010004012A CN 102129880 A CN102129880 A CN 102129880A
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Abstract
The invention discloses a multi-chip package which is provided with a chip, wherein the chip is provided with a shared input and a unique access identification code. A first unique identification code is allocated and stored in a chip in a batch of chips. A group of chips are arranged on the multi-chip package. A series of scanning identification codes are applied to the shared input to allocate the available access identification code. In each chip, the scanning identification code of the shared input is compared with the first unique identification code stored in the chip; when the matching is detected, the chip is enabled by a circuit in the chip for a period of time so as to write the access identification code to a nonvolatile memory, wherein one of chips is enabled within a period of time. In addition, the shared input is used for writing the available identification code to the nonvolatile memory in the enabled chip in the group of chips. The first unique identification code can be stored when a wafer is subjected to a class test program.
Description
Technical field
The invention relates to and have many chip packagings and the encapsulation of sharing input, for example encapsulation of three dimensional integrated circuits chip, and the integrated circuit that so uses.
Background technology
Three-dimensional (3D) encapsulation technology is multiple integrated circuit to be integrated in a single encapsulation or other packaging housing be developed.For example, the multiplexed memory chip can repeatedly be put to improve the density of storer in the printed circuit board (PCB) unit area.Usually, the memory chip mode of also sharing identical control/address and/or data signal is repeatedly put.Therefore, a meeting of how repeatedly to put in the chip in time access has problems, and for example needs to read or write data when storing chip in the array rather than other.This problem can be solved by particular processing individual chip before encapsulation, but may be very expensive and complicated.For example, anyone can implement technology identification code with a uniqueness on each chip marking in the wafer when wafer is made, use unique photoengraving pattern on each chip, for example on the metal level therein, with configuration one demoder in the chip that each three-dimensional stacks on the specific level.Each chip must be followed the trail of according to this demoder configuration afterwards.This mode has increased the expense of photo-etching mark and the complicacy in the practical application.
No. the 7327592nd, United States Patent (USP), title is invented by Silverstri for " identification repeatedly stacks the chip semiconductor subassembly automatically ", draws at this to be reference.According to the invention of Silverstri, the individual chip during this chip stacks is to use the microballoon of chip chamber and utilizes by so-called " external control connection " and arrange identification.Special demoder is connected to these microballoons so that unique individual chip of choosing in stacking to this chip to be provided.So can allow any position in stacks in a given wafer, to use any chip.Yet the zone that it is need be on each chip big has relatively consumed join domain limited on the chip and complicated this packaging technology.
Therefore need provide a kind of integrated circuit (IC) design and technology in the wafer manufacture process, can distinguish each chip on the wafer, and can with any order be placed in one can not identification the encapsulation of multicore sheet in, and can allow to distinguish other chip in the operation after encapsulation simultaneously.
Summary of the invention
It for example is one to use the core assembly sheet in the multicore sheet encapsulation of three-dimensional integrated encapsulation that integrated circuit (IC) apparatus described in the invention is contained in, its with share incoming line and couple.This core assembly sheet has an operator scheme and relies on the chip of choosing in this group, for example chooses other chip in a three-dimensional storage device.Each chip in this group comprises a nonvolatile memory and is applicable to one first unique identification code (" scanning identification code ") that stores in a collection of chip, and one second unique identification code (" access identification code ") in this core assembly sheet of storage multicore sheet encapsulation.Logical circuit in this chip respond this one first order of sharing Input Online with an input scan identification code of this being shared Input Online be stored in one in this nonvolatile memory and be assigned with first identification code and compare, and respond a coupling, write one second identification code to this nonvolatile memory with activation.In addition, also comprise logical circuit in this chip and respond one second order that this shares Input Online, in this time, this is shared this second identification code that is assigned with that Input Online receives and write in this nonvolatile memory.Logical circuit in this chip according to this is assigned with in this nonvolatile memory second identification code to respond the order that this shares Input Online.
In addition, according to one embodiment of the invention also describe a technology wherein the chip in this core assembly sheet comprise case and place multicore sheet encapsulation from a collection of chip that comprises a wafer, and each this chip comprises that logical circuit can be before this wafer cuts certainly, for example, write this first identification code in this nonvolatile memory in the wafer sort stage of technology.
Also describe the method for a kind of manufacturing one multicore sheet encapsulation according to one embodiment of the invention, wherein this multicore sheet encapsulation comprises chip and has the access identification code of sharing the input and distinguishing chip described in this encapsulation.This method comprises the first unique identification code of storage in the chip of a collection of chip.Afterwards, settle a core assembly sheet certainly in this batch chip in multicore sheet encapsulation, this core assembly sheet has a plurality of inputs of sharing therein.Afterwards, choosing available access identity assignments in one group of access identification code finishes up to this group access identity assignments to chip described in this encapsulation.
This distributes the process of access identification code to comprise that applying a series of scanning identification code shares input in this.Each chip in this group, relatively this scanning identification code is with first identification code that is stored in this uniqueness in this chip and when detecting coupling, the circuit a period of time of sending in this chip of one scan identification code matched signal and activation writes in an access identification code this nonvolatile memory to this chip to use this to share input, and therefore one of described chip was enabled in the time.In addition, when sending one scan identification code matched signal, use this to share input writing in an available access identification code this nonvolatile memory to this chip that is enabled of this core assembly sheet, and continue afterwards to finish up to this group access identity assignments.
In addition, also describe one according to one embodiment of the invention and store this unique first identification code in the chip of this batch, wherein comprise and carry out a wafer class test procedure, it applies a testing tool, and first identification code that stores this uniqueness is in by in the chip of this testing tool.
In addition, also describe a kind of method of operating a multicore chip package according to one embodiment of the invention, comprise reception one order, it has a first and indicates an operator scheme and a second portion to indicate an access identification code; And this identification code that is assigned with in this access identification code and each chip compared, and use circuit in the certain chip with the order of a coupling of responding this certain chip.This order can be received in sharing Input Online by the chip in this multicore sheet encapsulation.This order can be shared Input Online in serial by the chip in this multicore sheet encapsulation and be received.
According to technology described herein, the chip that need be placed in the encapsulation of multicore sheet can utilize the mode that needn't distinguish individual chip in a wafer to make.Chip in a collection of can be distinguished in the wafer sort process by distributing unique scanning identification code.In addition, the chip with unique scanning identification code can utilize the mode that needn't distinguish individual chip in this encapsulation to be placed in the multicore sheet encapsulation.The access identification code of this multicore sheet encapsulation chips can use the technology that relies on unique scanning identification code to distribute.
Therefore, use technology described herein, chip is can be in a wafer factory manufactured and do not need to specify in advance employed core number in the single multicore sheet encapsulation, and does not need to specify in advance the order of chip placing in this encapsulation.In addition, chip can configuration need in the encapsulation of multicore sheet respectively that chip is how to be connected with input, and do not need putting in order of certain chip.
Description of drawings
Purpose of the present invention, feature, and embodiment can be described by the collocation accompanying drawing in the chapters and sections of following embodiment, wherein:
Fig. 1 shows that a tradition comprises the synoptic diagram to the multicore sheet encapsulation of a plurality of chips, and it has the input of sharing.
Fig. 2 shows the synoptic diagram according to the multicore sheet encapsulation of the embodiment of the invention, and wherein each chip that is placed in the encapsulation has the access identification code of a uniqueness, and responds and sharing the command set that input receives according to this access identification code.
Fig. 3 shows the concise and to the point block schematic diagram of an integrated circuit, comprises the chip that is applicable to multicore sheet encapsulation shown in Figure 2 therein.
Fig. 4 shows the process flow diagram of making a representative processes that comprises multicore sheet encapsulated integrated circuit device described herein.
Fig. 5 is for showing that a wafer sort board and has the simplified diagram of the wafer of a plurality of chips.
Fig. 6 shows a process flow diagram of the technology of being carried out by the wafer sort board.
Fig. 7 is for showing a packaging and testing board and one group of simplified diagram with multicore sheet encapsulation of scanning identification code chip.
Fig. 8 shows a process flow diagram of the technology of being carried out by the packaging and testing board.
Embodiment
The following Fig. 1 of embodiment of the invention collocation is described in detail to Fig. 8.
Fig. 1 shows the synoptic diagram of a tradition to the multicore sheet of a plurality of chip 13-18 encapsulation 10, and it has shares input 11 for example address, data to be provided and to control signal to chip 13-18 in the multicore sheet encapsulation 10.These chips are reached interconnection by stacking the shared input 11 that all chip 13-18 couple in 12 therewith by vertical connection 19,20 or other technology.In the case, must provide a technology to distinguish this individual chip in stacking.
Fig. 2 shows the synoptic diagram that access identification code command set is input into the multicore sheet encapsulation 60 of sharing input 50 that has according to the embodiment of the invention, and wherein each is placed in its access identification code with a uniqueness of chip 51-56 in the encapsulation 60 and is stored in the nonvolatile memory in the chip.Has circuit design to import the 50 individual chip 51-56 that react otherwise can't distinguish to sharing.This chip 51-56 use by between the circuit of chip chamber for example the three-dimensional integrated technology of line 58 and 59 representatives interconnect.Each chip has circuit, and it deciphers a command set according to the access identification code.Wherein other chip 51-56 comprises the integrated circuit storage device in an embodiment, and one in the command set orders it can comprise a reading order need specify in the data sequences that this shares input in advance.Described access identification code command set is in an example, for example be that a reading order comprises a series of byte, comprise first byte 01 (sexadecimal) indication read operation, second byte is loaded with access identification code " N ", the 3rd byte Addr1 is loaded with first byte of address, nybble Addr2 is loaded with second byte of address, and the 5th byte Addr3 is loaded with the 3rd byte of address.This command sequence apply so far share input and can be packed in all chips receive.Because each chip in the encapsulation has a unique access identification code that is stored in wherein, just can be by decoding correctly and to this order reaction.
Must be noted that the access identification code can be by with the order of chip in stacking identification code in addition, but needn't be like this.Therefore, in Fig. 2, the chip 51 of the top has access identification code=03, next chip has access identification code=01, next chip 53 has access identification code=04, next chip 54 has access identification code=02, and next chip 55 has access identification code=05 and next chip 56 has access identification code=06.It is the result who produces according to following described program that the sequence of this access identification code produces.
Fig. 3 is shown in the concise and to the point block schematic diagram of the integrated circuit on the chip 95, and it is applicable to settles chip described herein to encapsulate in a multicore sheet.When making and encapsulate, comparing with other chip that can be positioned in the same encapsulation on this integrated circuit, is undistinguishable.This integrated circuit comprises that a logical circuit is to distribute the access identification code of a uniqueness after encapsulation.In this example, the integrated circuit on the chip 95 comprises that a memory array 80 is on the semiconductor substrate.In an example, this memory array 80 comprises a flash memory, and it comprises an array of non-volatile storage element.One column decoder 81 stores the character line of arranging on array 80 column directions 82 along this and couples with many.Row decoder 83 stores the bit line of arranging on array 80 line directions 84 along this and couples with many, reads and the sequencing data in the storage element with array 80 since then.The address provides to row decoder 83 and column decoder 81 via bus 85.Induction amplifier in block 86 and data input structure couple via data bus 87 and row decoder 83 in this example.Data be by in the input/output end port of the integrated circuit on the chip 95 or other integrated circuit on chip 95 or outer data source be sent to the data input structure of square 86 by data input line 91.In this illustrative embodiment, other circuit 94 is also included within this integrated circuit, for example general purpose processor or special purpose circuit, or store composite module that array supports thus so that the system-on-a-chip function to be provided.Data is by the induction amplifier in the square 86, by data output line 92, is sent in the input/output end port of the integrated circuit on the chip 95 or the integrated circuit on other chip 95 or outer data destination.In this example, this chip 95 comprises that the voltage supply comes from the square 88, and its adjustment bias voltage that many kenels can be provided is chip so far, for example for flash memory as read, wipe, the voltage of sequencing, erase verification and sequencing checking.
A controller 89 is adjusted state machine with a bias voltage and should be used for operation set and become the different mode of circuit in this example.The application of this controller 89 can be used techniques well known, implements as the specific purposes logical circuit.In another embodiment, this controller comprises a general purpose processor, and it can be embodied on the identical integrated circuit, and it carries out a computer program to control the operation of this device.In another embodiment, the combination of a specific purposes logical circuit and a general purpose processor can be used to implement this controller.
This controller 89 comprises that its response of a command decoder applies order on online 93 with the command set of this integrated circuit of decoding.For example, its command set of a storage device is comprised read, write, buffer reads, buffer writes or the like kenel order.According to technology described herein, this command set also loads and uses the access identification code to choose the order of individual chip in the encapsulation of multicore sheet.This controller 89 also comprise scanning identification code/access identification code logical circuit its can support program described herein to distribute the access identification code of this brilliant example.Also comprise among the embodiment address generator in controller 89 to be used for resulting from the required address of different application in this device.
When settling multicore sheet encapsulation, this input comprise data input line 91, address wire 85 and order wire 93 thus the chip in the encapsulation of multicore sheet share, be called " sharing input " jointly.In certain embodiments, data, address and command signal are to apply with serial mode so far to share incoming line, and for example it can utilize known serial flash memory to use.
This chip 95 also comprises that nonvolatile memory 96 is applicable to storage one first unique identification code, is called the scanning identification code, reaches nonvolatile memory 97 and is applicable to storage one second unique identification code, is called the access identification code.This first unique identification code is unique in a collection of chip, and wherein a collection of perhaps is all chips in the single wafer, or all chips in group's wafer, and it can follow the trail of this chip in follow-up manufacturing and encapsulation process.This second unique identification code one group be placed in chip on the single packaging body in be unique, and corresponding to being used in a command set to choose the employed access identification code of certain chip in the packaging body since then.The storage element that this scanning identification code storer 96 and access identification code storer 97 can use in the array 80, and use in addition identification of a specific array address by controller 98.Alternatively, this scanning identification code storer 96 and access identification code storer 97 can use other the non-volatile storage element in the chip.For example, non-volatile Storage Register can couple with the usefulness as these purposes with controller 98.These identification codes can utilize identical with configuration registers or the similar mode of status register in installing therewith to implement on accessible non-volatile Storage Register.
Particularly, this scanning identification code storer 96 can configuration in the wafer sort program, to carry out access by wafer probe.So an entity test interface or other interface on integrated circuit, for example the testing cushion of specific function can be contacted by wafer probe, and can be write data by the wafer sort board in this scanning identification code storer 96 at the logical circuit on the integrated circuit.This entity test interface be according to the employed testing apparatus of production line specific mode be implemented on wafer and/or the chip.
Resource in this controller 98 or other chip comprises that scanning identification code/access identification code logical circuit is to respond this to share first order of 1 in the input first a scanning identification code of distributing compares in the identification code storer 96 so that an input scan identification code is scanned therewith.This logical circuit sends one scan identification code matched signal, or mismatch signal so far shares input, so distributes notified whether coupling of system of this access identification code.
Resource in this controller 98 or other chip comprises that the logical circuit that can respond scanning identification code coupling writes one second identification code to access identification code storer 97 a period of time length with activation and is enough to allow a system assignment access identification code to finish and uses to share input to write the program in the available access identification code access identification code so far storer 97.In addition, this controller 98, or resource in other chip, comprise that logical circuit responds this and share order in the input, it can send one by an external mechanical and respond the signal that the scanning identification code is mated, and in during this section of program activation an access identification code of distributing is write in the storer of access identification code so far.When this access identification code write-in program can't be enabled after one scan identification code coupling, this access identification code storer 97 can use storer pinning technology well known in the art to prevent to be changed.
Fig. 4 shows the process flow diagram of making a representative processes that comprises multicore sheet encapsulated integrated circuit device described herein.According to this example, one has the wafer manufactured (100) of the array of an access identification code activation chip, for example has as the chip among Fig. 3.This wafer is positioned in a wafer probe to carry out wafer sort program (101).Use this wafer probe, the identification code of a uniqueness in distributing the identification code scope so far criticize, and writes in the scanning identification code storer (102) by the wafer sort chip.Afterwards, this wafer shifts out and cuts into independent chip (103) in the wafer probe.During criticizing since then, one group of chip by test chooses to be packaged into multicore sheet encapsulation (104).Afterwards, one group of chip placing by test encapsulates (105) at a single multicore sheet.This chip can use the technology that can not distinguish certain chip that it is placed in the single multicore sheet encapsulation.
Afterwards, this multicore sheet of finishing encapsulation is positioned on the packaging and testing device and carries out for example final test.One program is performed the chip and scanning identification code coupling (106) encapsulating.In each chip, in order to respond this coupling, a period of time is carried out in one access write operation, it can be a special time of prior appointment, or the time that changes along with technology, till this chip successfully writes an access identification code or receives the signal that can't write the access identification code (107).Because each chip has the scanning identification code of a uniqueness in this batch, so only have a chip to be enabled in the time in this encapsulation.
When the detecting coupling, an available access identification code is used to share to import and is write in the encapsulation so far (108).Because have only a chip to be enabled to write this access identification code, only there is a chip can receive this available access identification code between at this moment.This program can determine that all access identification codes are assigned with (109) all in this encapsulation.If be not, then this program is got back to step 106, proceed the chip scanning that will encapsulate and with scanning identification code coupling.If in step 109, all access identification codes are assigned with all, then finish this program (110).Though in figure, do not show, if all access identification code and is not that all access identification codes are successfully distributed all in regular turn by this encapsulation in this batch, this procedure failure then.
Fig. 5 is for showing that a wafer sort board 200 and has the simplified diagram of the wafer 201 of a plurality of chips.This chip can not be differentiated after manufacturing, as described in Fig. 3.200 activations of wafer sort board write the scanning identification code so far on the individual chip in the wafer 201, so the chip in this batch are write a series of scanning identification code.As explained before, distributing access identification code to so-called a collection of can comprising in this technology is all chips in the single wafer, or all chips in group's wafer, or supports the group's chip in the multicore sheet packaging technology one specific production line.In this example, it has passed through the individual chip in this wafer 201 to be assigned with scanning identification code unique in this batch in regular turn after the wafer sort program, comprises scanning identification code 1, scanning identification code 2, scanning identification code 3 ... scanning identification code 160 etc.
Fig. 6 shows a process flow diagram of the technology of being carried out by wafer sort board 200.This technology involves surveys an ad-hoc location (x, chip y) (210) on the wafer.Test sample book is applied in this chip (211).(x, y) whether the chip on is by this test sample book (212) at this ad-hoc location in this algorithm decision.If this chip passes through, the one scan identification code can be written into the nonvolatile memory in this chip, and this chip can be labeled or to note down be one by chip (213).Afterwards, whether this program can determine chips all in this wafer whether all to be assigned with scanning identification code (214).If be not, then this probe moves on to the next chip (215) in the wafer, and this program loop is got back to step 210.If in step 212, this chip does not pass through,, or carry out other processing (217) after the wafer cutting so then this chip marking is that a chip failing can be dropped at chip.In addition, if, determined chips all in this wafer to finish test all, then stop this program (216) in step 214.
Fig. 7 is for showing a packaging and testing board 30 and one group of simplified diagram with multicore sheet encapsulation 301 of scanning identification code 12,9,14,16,10 and 18 chips.Chip in this multicore sheet encapsulation 301 has shares input 302.These chips can not be differentiated after manufacturing, as described in Fig. 3, choose the employed unique scanning identification code of certain chip but have in can criticizing since then.This mode makes the chip that is placed in this multicore sheet encapsulation 301 not need to be distinguished.After the described program, each chip in this batch receives the access identification code of a uniqueness before carrying out.As shown in Figure 7, for example, this chip has the coupling of first in this series scanning identification code, and it is 9 in this example, is assigned to the first access identification code in the available access identification code of this group, for example access identification code " 1 ".This chip has the coupling of second in this series scanning identification code, and it is 10 in this example, is assigned to the second access identification code in the available access identification code of this group, for example access identification code " 2 ".
Fig. 8 shows a process flow diagram of the technology of being carried out by packaging and testing board 300.This technology involves and at first extracts present encapsulation board (310) so far.Afterwards, scanning identification code (i) is applied in the input of sharing in the multicore sheet encapsulation so far, and wherein (i) is used for following the trail of the used index of scanning identification code that is assigned in this batch.This program can determine whether to detect a coupling (312), and for example detecting encapsulates the online signal of sharing that couples with the multicore sheet.If the coupling of detecting, the circuit that detects coupling on this chip can activation one access identification code write nonvolatile memory (313).At the chip that does not have to mate with current scanline identification code (i), this circuit that writes the access identification code will can not be enabled.Therefore, have only a chip to be enabled in this encapsulation and receive an access identification code to respond the coupling of a specific scanning identification code.Packaging and testing board 300 uses to share to import and writes an available access identification code in this chip that is enabled (314).Afterwards, this program can determine that all access identification codes are written into (315) all in whether this encapsulation.If be not, then last the scanning identification code in this batch is tested (316) for the decision of this program.If last scanning identification code is not tested as yet, then increase progressively this scanning identification code (317), and this program loop is got back to step 311 to continue to apply the scanning identification code.If be written into all in this multicore sheet encapsulation in all access identification codes of step 315, then finished this program (319).If in step 316, used all scanning identification codes of this batch but can't successfully distribute all access identification codes, then this procedure failure (318).
It can support to settle the program of a chip in a polycrystalline encapsulation integrated circuit described herein, and wherein these these chips can not be differentiated during manufacture, and can be positioned on the not ad-hoc location in the encapsulation, and has the I/O that can not differentiate.In the example herein, this chip is implemented as and can supports one to distribute the scanning identification code of each chip one uniqueness to be stored in the program in the nonvolatile memory in the chip in the wafer sort stage of technology in circuit.In the packaging and testing stage, this scanning identification code is used to support a program to be used for and scans the scanning identification code of mating in this encapsulation.Once the one scan identification code is mated, the chip of this coupling can be by the access identification code of sequencing one uniqueness.
When execute-in-place, an employed command set can utilize the advantage of this unique access identification code that other chip in the encapsulation is carried out access.Therefore, a kind of method of operation one multicore chip package, this multicore chip package comprises a plurality of chips, each chip is stored in the identification code that is assigned with unique in this multicore chip package, this method comprises the following step: receive an order in sharing Input Online, it has a first and indicates an operator scheme and a second portion to indicate an access identification code; And this identification code that is assigned with in this access identification code and each chip compared, and respond this order by the certain chip of coupling.
Though the present invention is described with reference to embodiment, right the present invention is not subject to its detailed description.Substitute mode and revise pattern and in previous description, advise, and other substitute mode and modification pattern will by art technology thought and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and revise pattern and be intended to drop among claim scope of the present invention and the category that equipollent defined thereof.
Claims (10)
1. integrated circuit (IC) apparatus comprises:
One core assembly sheet and incoming line couple, and the chip in this core assembly sheet comprises:
Nonvolatile memory is used for storing one first identification code and one second identification code in this chip; And
Control logic circuit to be comparing an input scan identification code of this Input Online and this first identification code that is stored in this nonvolatile memory, and responds a coupling and write this second identification code to this nonvolatile memory with activation.
2. integrated circuit (IC) apparatus as claimed in claim 1, wherein, the chip in this core assembly sheet was writing this first identification code in this nonvolatile memory before wafer cutting.
3. integrated circuit (IC) apparatus as claimed in claim 1, wherein, this second identification code that this control logic circuit basis is assigned with is to respond the signal of this Input Online.
4. integrated circuit (IC) apparatus as claimed in claim 1, wherein, this integrated circuit (IC) apparatus is responded an order, and this order has a first and indicates an operator scheme and a second portion to indicate this second identification code.
5. integrated circuit (IC) apparatus as claimed in claim 1, wherein, chip in this core assembly sheet comprises the integrated circuit storage device, and it comprises separately array in non-volatile storage element, and wherein this nonvolatile memory stores in this first identification code and the storage element of this second identification code in this array separately.
6. method of making a multicore sheet encapsulated integrated circuit, this multicore sheet encapsulation comprise chip and have input and first identification code in wherein, and comprise the access identification code and distinguish chip described in this encapsulation, and this method comprises:
In one group of access identification code, choose available access identity assignments and to chip described in this encapsulation, finish up to this group access identity assignments, by following steps:
(i) applying a series of scanning identification code imports in this; And
(ii) in this group in each chip, relatively this scanning identification code be stored in this first identification code in this chip, and the circuit in this chip of activation writes in the nonvolatile memory of an access identification code to this chip to use this input when detecting coupling.
7. the method for manufacturing one multicore sheet encapsulated integrated circuit as claimed in claim 6 comprises:
Store this first identification code respectively in a chip wherein of a collection of chip; And
Settle a core assembly sheet in this batch chip on this multicore sheet encapsulated integrated circuit, this core assembly sheet has a plurality of inputs of sharing.
8. the method for manufacturing one multicore sheet encapsulated integrated circuit as claimed in claim 7 wherein, comprises the packaging and testing program of execution, and it uses a testing tool, and stores this first identification code in passing through the chip of this testing tool.
9. the method for manufacturing one multicore sheet encapsulated integrated circuit as claimed in claim 6 wherein, is distributed available access identification code when being included in a packaging and testing program.
10. the method for operation one a multicore chip package, this multicore chip package comprises a plurality of chips, and each chip stores an identification code that is assigned with, and this method comprises the following step:
Reception one order has a first and indicates an operator scheme and a second portion to indicate an access identification code; And
This identification code that is assigned with in this access identification code and each chip is compared, and respond this order by the certain chip of coupling.
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| CN201010004012.3A CN102129880B (en) | 2010-01-14 | 2010-01-14 | The three-dimensional chip sharing input package is chosen |
| CN201510318899.6A CN104952487B (en) | 2010-01-14 | 2010-01-14 | A kind of method for operating multi-chip package device |
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| CN104237766A (en) * | 2013-06-24 | 2014-12-24 | 上海海尔集成电路有限公司 | Chip testing method and device |
| CN109599672A (en) * | 2013-07-02 | 2019-04-09 | 维斯普瑞公司 | Filter antenna equipment |
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| US7620763B2 (en) * | 2006-07-26 | 2009-11-17 | International Business Machines Corporation | Memory chip having an apportionable data bus |
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| CN104237766A (en) * | 2013-06-24 | 2014-12-24 | 上海海尔集成电路有限公司 | Chip testing method and device |
| CN109599672A (en) * | 2013-07-02 | 2019-04-09 | 维斯普瑞公司 | Filter antenna equipment |
Also Published As
| Publication number | Publication date |
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| CN104952487B (en) | 2018-03-27 |
| CN104952487A (en) | 2015-09-30 |
| CN102129880B (en) | 2015-09-30 |
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