CN102122949A - Flash memory circuit - Google Patents
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- CN102122949A CN102122949A CN2011100575683A CN201110057568A CN102122949A CN 102122949 A CN102122949 A CN 102122949A CN 2011100575683 A CN2011100575683 A CN 2011100575683A CN 201110057568 A CN201110057568 A CN 201110057568A CN 102122949 A CN102122949 A CN 102122949A
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Abstract
The invention relates to a flash memory circuit which at least comprises a peripheral circuit and a line decoding circuit, wherein the line decoding circuit comprises a level shifting circuit, a word line choosing circuit and a driving latch circuit; the level shifting circuit comprises a first pull-up MOS (metal oxide semiconductor), a second pull-up MOS, a first pull-down MOS, a second pull-down MOS, and a first inverter; by increasing the source electrode voltages of the first pull-down MOS and the second pull-down MOS, the source electrode voltages become higher than the grid electrode voltages of the first pull-down MOS and the second pull-down MOS; and meanwhile, by increasing the substrate voltages of the first pull-up MOS and the second pull-up MOS, the substrate voltages become higher than the source electrode voltages of the first pull-up MOS and the second pull-up MOS. In the invention, through improving the level shifting circuit of the traditional flash memory circuit, when the flash memory circuit is in a standby state, the leaked current flowing through the MOS is reduced and the MOS are prevented from being damaged by the high leaked current.
Description
Technical field
The present invention relates to the flash memory design circuit field, particularly a kind of flash memory circuit.
Background technology
As shown in Figure 1, in existing flash memory 1, mainly comprise peripheral circuit 11, column decode circuitry 12, array decoding circuit 13 and storage array 14.Wherein, described peripheral circuit 11 is connected with described array decoding circuit 13 with described column decode circuitry 12 respectively, and described column decode circuitry 12 is connected with storage array 14 with described array decoding circuit 13.Further, also comprise level shift circuit 121 in the described column decode circuitry 12, word line is selected circuit 122 and is driven latch cicuit 123, wherein said level shift circuit 121 selects circuit 122 to be connected with the word line of back one-level, and described word line selects circuit 122 to be connected with described driving latch cicuit 123.Particularly, described level shift circuit is similar to a voltage switch, high level signal and low level signal that output is complementary, word line selects circuit to select corresponding word line according to the high level signal or the low level signal that receive then, and drives corresponding word line in the described storage array 14 by driving latch cicuit 123.Particularly, can number be 201010161459.1 to disclose a kind of structure of voltage level shifter and the method for voltage level shifting with reference to Chinese patent application.
Show the schematic diagram of level shift circuit in the prior art with reference to figure 2.Particularly, the receiving terminal IN1 of described level shift circuit receives the input signal that comprises high level signal and low level signal, and has the output signal of voltage level complementation in output terminals A and output B output.
As shown in Figure 2, described level shift circuit comprises and draws metal-oxide- semiconductor 101 and 102, the drop-down metal-oxide- semiconductor 103 and 104 and first inverter 105, drawing metal-oxide- semiconductor 101 and 102 on wherein said is that P channel-type metal-oxide-semiconductor, described drop-down metal-oxide- semiconductor 103 and 104 are N channel-type metal-oxide-semiconductors.Further, draw the source electrode of metal-oxide- semiconductor 101 and 102 to be connected on the voltage ZVDD2 on described, draw metal-oxide- semiconductor 101 and 102 drain electrode and described drop-down metal-oxide-semiconductor 103 to link to each other on described and constitute output terminals A and output B, described drop-down metal-oxide- semiconductor 103 and 104 source ground with 104 drain electrode.Described input IN1 links to each other with the grid of described drop-down metal-oxide-semiconductor 103, links to each other with the grid of described drop-down metal-oxide-semiconductor 104 through first inverter, 105 backs.
The operation principle of described level shift circuit is as follows: when the input signal of described input IN1 was high level signal, described drop-down metal-oxide-semiconductor 103 conductings were pulled down to 0V (being ground connection) with the output signal of output B; Then make and draw metal-oxide-semiconductor 102 conductings, the output signal of output terminals A is pulled to ZVDD2; Then make and draw metal-oxide-semiconductor 101 to end, thereby the output signal of guaranteeing output B is 0V.
On the contrary, when the input signal of described input IN1 was low level signal, described drop-down metal-oxide-semiconductor 103 ended, and described drop-down metal-oxide-semiconductor 104 conductings are pulled down to 0V (being ground connection) with the output signal of output terminals A; Then make and draw metal-oxide-semiconductor 101 conductings on described, the output signal of output B is pulled to ZVDD2; Then make and draw metal-oxide-semiconductor 102 to end on described, the output signal of guaranteeing output terminals A is 0V.
But, in above-mentioned level shift circuit, when each metal-oxide-semiconductor during in cut-off state, usually more serious leaky can take place, thereby metal-oxide-semiconductor is produced infringement.At present, also there is not solution preferably at this problem in the existing technology.
Summary of the invention
The problem that the present invention solves provides a kind of flash memory circuit, reduces to flow through the leakage current of each metal-oxide-semiconductor of the level shift circuit in the described flash memory circuit.
For addressing the above problem, the invention provides a kind of flash memory circuit, at least comprise peripheral circuit and column decode circuitry, wherein said column decode circuitry comprises level shift circuit, word line is selected circuit and is driven latch cicuit, wherein said level shift circuit comprises: draw on first on metal-oxide-semiconductor and second and draw metal-oxide-semiconductor, the first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor and first inverter, the source electrode of the source electrode of the described first drop-down metal-oxide-semiconductor and the described second drop-down metal-oxide-semiconductor is connected to first voltage end and second voltage end, the voltage of wherein said first voltage end is greater than the grid voltage of the first drop-down metal-oxide-semiconductor, and the voltage of described second voltage end is greater than the grid voltage of the second drop-down metal-oxide-semiconductor; Drawing on described first on the substrate and described second of metal-oxide-semiconductor draws the substrate of metal-oxide-semiconductor to be connected to tertiary voltage end and the 4th voltage end, the voltage of wherein said tertiary voltage end is greater than the source voltage that draws metal-oxide-semiconductor on described first, and the voltage of described the 4th voltage end is greater than the source voltage that draws metal-oxide-semiconductor on described second.
Alternatively, draw the source electrode that draws metal-oxide-semiconductor on metal-oxide-semiconductor and second to be connected on the first operating voltage end on first described in the described level shift circuit, draw the grid of metal-oxide-semiconductor to be connected to the drain electrode of drawing metal-oxide-semiconductor on second on described first, draw the grid of metal-oxide-semiconductor to be connected to the drain electrode of drawing metal-oxide-semiconductor on first on described second; The grid of the described first drop-down metal-oxide-semiconductor is connected to the input of described level shift circuit, draw the drain electrode of drawing metal-oxide-semiconductor on metal-oxide-semiconductor and second to be connected to form two outputs with the drain electrode of the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively on described first, the input of described first inverter is connected in the grid of the described first drop-down metal-oxide-semiconductor, and output is connected in the grid of the described second drop-down metal-oxide-semiconductor.
Alternatively, first voltage end described in the described level shift circuit is the output of described first inverter.
Alternatively, second voltage end described in the described level shift circuit is the input of described first inverter.
Alternatively, described peripheral circuit comprises voltage regulator circuit at least, described voltage regulator circuit links to each other with the first operating voltage end, tertiary voltage end and the 4th voltage end, and described voltage regulator circuit produces the voltage of the voltage of the described first operating voltage end, described tertiary voltage end and the voltage of described the 4th voltage end.
Alternatively, the voltage of the voltage of described tertiary voltage end and described the 4th voltage end equates.
Alternatively, described voltage regulator circuit comprises multistage charge pump, single-stage charge pump, comparison controller and commutation circuit; Described single-stage charge pump is connected in described multistage electric charge delivery side of pump; Described comparison controller and single-stage electric charge delivery side of pump are connected in the input of described commutation circuit; The output of described commutation circuit is exported the voltage of the voltage of the described first operating voltage end, described tertiary voltage end and the voltage of described the 4th voltage end respectively.
Alternatively, also comprise power supply circuits in the described level shift circuit, the input of wherein said power supply circuits is connected with peripheral circuit, described power supply circuits respectively with described first on draw in the drain electrode, described second of metal-oxide-semiconductor draw the drain electrode of metal-oxide-semiconductor to be connected, the drain electrode of the described first drop-down metal-oxide-semiconductor, the drain electrode of the described second drop-down metal-oxide-semiconductor be connected, and exports second operating voltage to the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor.
Alternatively, described power supply circuits comprise first high-voltage tube and second high-voltage tube, the drain electrode that wherein said first high-voltage tube and the grid of second high-voltage tube are connected in the input of described power supply circuits, described first high-voltage tube and second high-voltage tube respectively with described first on draw and draw the drain electrode of metal-oxide-semiconductor to be connected on the metal-oxide-semiconductor and second, the source electrode of described first high-voltage tube and second high-voltage tube is connected with the drain electrode of the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively; The described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are low-voltage tubes.
Alternatively, described first high-voltage tube and described second high-voltage tube are N channel-type metal-oxide-semiconductors.
Alternatively, drawing on first described in the described level shift circuit and drawing metal-oxide-semiconductor on metal-oxide-semiconductor and second is P channel-type metal-oxide-semiconductor, and the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are N channel-type metal-oxide-semiconductors.
Compared with prior art, the embodiment of the invention has the following advantages: on the basis of the level shift circuit in existing flash memory circuit, by increasing the source voltage of the first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor, make described source voltage greater than grid voltage; Increase simultaneously and draw the underlayer voltage that draws metal-oxide-semiconductor on metal-oxide-semiconductor and second on first, make described underlayer voltage greater than source voltage.When above-mentioned any metal-oxide-semiconductor ends, can reduce to flow through the leakage current of metal-oxide-semiconductor like this, make metal-oxide-semiconductor can not be subjected to the infringement of high leakage current.
Description of drawings
Fig. 1 is the structural representation block diagram of existing flash memory circuit;
Fig. 2 is the schematic diagram of existing level shift circuit;
Fig. 3 is the schematic diagram of first embodiment of level shift circuit provided by the invention;
Fig. 4 is the schematic diagram of second embodiment of level shift circuit provided by the invention;
Fig. 5 is the schematic block diagram of the voltage regulator circuit in the peripheral circuit in the flash memory circuit of the present invention.
Embodiment
The inventor finds when each metal-oxide-semiconductor is in cut-off state, usually more serious leaky can take place in the level shift circuit of existing column decode circuitry, makes described metal-oxide-semiconductor be subjected to the infringement of high leakage current.For example, with reference to level shift circuit shown in Figure 2, when the input signal of input IN1 was low level signal, the Vgs of drop-down metal-oxide-semiconductor 103 was 0V, but flow through described drop-down metal-oxide-semiconductor 103 because the subthreshold value electric leakage still can produce leakage current.Again for example, when the input signal of input IN1 is high level signal, on draw metal-oxide-semiconductor 101 to end, but owing to draw the subthreshold value electric leakage of metal-oxide-semiconductor on described, still can produce leakage current and flow through and draw metal-oxide-semiconductor 101 on described.
Therefore, at the problems referred to above, the inventor makes change to the connected mode of metal-oxide-semiconductor in the existing level shift circuit, with drop-down metal-oxide-semiconductor source electrode be connected on the voltage end greater than its grid voltage, will on draw the substrate of metal-oxide-semiconductor to be connected on the voltage end greater than its source voltage, thereby reduce to flow through the leakage current of each metal-oxide-semiconductor, reduce the power consumption of each metal-oxide-semiconductor of whole flash memory system when standby.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
At first, the schematic block diagram of the voltage regulator circuit in the peripheral circuit in the reference flash memory circuit shown in Figure 5.Described voltage regulator circuit produces voltage, the voltage of tertiary voltage end and the voltage of the 4th voltage end of the first required operating voltage end of level shift circuit described in the embodiment of the invention.Alternatively, wherein, the voltage of the voltage of described tertiary voltage end and the 4th voltage end equates.Particularly, in an embodiment of the present invention, the voltage of the described first operating voltage end is ZVDD2, and the voltage of the voltage of described tertiary voltage end and the 4th voltage end is ZVDD2_PLUS, and described ZVDD2_PLUS is greater than described ZVDD2.Particularly, as shown in Figure 5, described voltage regulator circuit comprises multistage charge pump 111, single-stage charge pump 112, comparison controller 113 and commutation circuit 114.Wherein, described single-stage charge pump 112 output, described comparison controller 113 and the single-stage electric charge delivery side of pump that are connected in described multistage charge pump 111 is connected in the input of described commutation circuit 114.Then, the output of described commutation circuit 114 is exported described voltage ZVDD2_PLUS and described voltage ZVDD2 respectively.Need to prove that described voltage ZVDD2 produces by described multistage charge pump 111, described voltage ZVDD2_PLUS produces jointly by described multistage charge pump 111 and single-stage charge pump 112.
The first embodiment schematic diagram of reference level shift circuit as shown in Figure 3.Particularly, described level shift circuit comprises drawing on first on the metal-oxide-semiconductor 101, second and draws metal-oxide-semiconductor 102, first drop-down metal-oxide-semiconductor 103, the second drop-down metal-oxide-semiconductor 104 and first inverter 105.Alternatively, drawing on described first and drawing metal-oxide-semiconductor 102 on metal-oxide-semiconductor 101 and second is P channel-type metal-oxide-semiconductors, and the described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 are N channel-type metal-oxide-semiconductors.
Draw the source electrode that draws metal-oxide-semiconductor 102 on metal-oxide-semiconductor 101 and second to be connected on the first operating voltage end on described first, the voltage of the described first operating voltage end is ZVDD2.Draw the grid of metal-oxide-semiconductor 101 to be connected to the drain electrode of drawing metal-oxide-semiconductor 102 on second on described first, draw the grid of metal-oxide-semiconductor 102 to be connected to the drain electrode of drawing metal-oxide-semiconductor 101 on first on described second, the grid of the described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 is connected to input IN1, draw the drain electrode of drawing metal-oxide-semiconductor 102 on metal-oxide-semiconductor 101 and second to be connected to form two output terminals A and B with the drain electrode of the described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 respectively on described first, the input of described first inverter 105 is connected in the grid of the described first drop-down metal-oxide-semiconductor 103, and output is connected in the grid of the described second drop-down metal-oxide-semiconductor 104.
Different with existing level shift circuit is that the source electrode of the described first drop-down metal-oxide-semiconductor 103 is connected to first voltage end, is the output of described first inverter 105 in the present embodiment, is connected with the grid of the described second drop-down metal-oxide-semiconductor 104.The source electrode of the described second drop-down metal-oxide-semiconductor 104 is connected to second voltage end, is the input of described first inverter 105 in the present embodiment, is connected with the grid of the described first drop-down metal-oxide-semiconductor 103.Drawing the substrate that draws metal-oxide-semiconductor 102 on metal-oxide-semiconductor 101 and described second to be connected to tertiary voltage end and the 4th voltage end on described first, in the present embodiment, the voltage of the voltage of described tertiary voltage end and described the 4th voltage end equates, i.e. the ZVDD2_PLUS of the generation of voltage regulator circuit described in the peripheral circuit.Alternatively, the voltage ZVDD2 of the described first operating voltage end is 2.5V, and the voltage ZVDD2_PLUS of the voltage of described tertiary voltage end and described the 4th voltage end is 3.6V.
The operation principle of described level shift circuit is as follows: 1) when the input signal of described input IN1 is low level signal, the described first drop-down metal-oxide-semiconductor 103 ends, described input signal becomes high level signal after through first inverter 105, described second drop-down metal-oxide-semiconductor 104 conductings, this moment, the output signal of output terminals A was a low level.Then, because the output signal of described output terminals A is a low level, so draws metal-oxide-semiconductor 101 conductings on described first, this moment, the output signal of described output B was high level ZVDD2, draw metal-oxide-semiconductor 102 to end on described like this second, the output signal that keeps described output terminals A is a low level.
Compare with existing level shift circuit, because the source electrode of the described first drop-down metal-oxide-semiconductor 103 is connected the output of described first inverter 105, be connected with the grid of the described second drop-down metal-oxide-semiconductor 104, therefore when the input signal of described input IN1 is low level, the source electrode of the described first drop-down metal-oxide-semiconductor 103 is a high level voltage, the Vgs of the first drop-down metal-oxide-semiconductor 103 (gate source voltage) is a negative voltage so, can reduce to flow through the leakage current of the described first drop-down metal-oxide-semiconductor 103 like this.
On the other hand, owing to be connected to the 4th voltage end on the substrate that draws metal-oxide-semiconductor 102 on described second, the voltage ZVDD2_PLUS of described the 4th voltage end is greater than the voltage ZVDD2 of the described first operating voltage end.Therefore, when drawing metal-oxide-semiconductor 102 to end on described second, because the voltage ZVDD2_PLUS of described the 4th voltage end can reduce to flow through the leakage current that draws metal-oxide-semiconductor 102 on described second like this greater than the voltage ZVDD2 of described first working end.
2) when the input signal of described input IN1 is high level voltage, described first drop-down metal-oxide-semiconductor 103 conductings, described input signal IN1 becomes low level signal after through first inverter 105, and the described second drop-down metal-oxide-semiconductor 104 ends, and this moment, the output signal of described output B was a low level.Then, because the output signal of described output B is a low level, so draws metal-oxide-semiconductor 102 conductings on described second, this moment, the output signal of described output terminals A was high level ZVDD2, draw metal-oxide-semiconductor 101 to end on described like this first, the output signal that keeps described output B is a low level.
Compare with existing level shift circuit, because the source electrode of the described second drop-down metal-oxide-semiconductor 104 is connected the input of described first inverter 105, be connected with the grid of the described first drop-down metal-oxide-semiconductor 103, therefore when the grid voltage that is added in the described first drop-down metal-oxide-semiconductor 103 is high level signal, the source electrode of the described second drop-down metal-oxide-semiconductor 104 is a high level voltage, the Vgs of the so described second drop-down metal-oxide-semiconductor 104 (gate source voltage) is a negative voltage, can reduce to flow through the leakage current of the described second drop-down metal-oxide-semiconductor 104 like this.
On the other hand, owing to connect the tertiary voltage end on the substrate that draws metal-oxide-semiconductor 101 on described first, the voltage ZVDD2_PLUS of described tertiary voltage end is greater than the voltage ZVDD2 of the described first operating voltage end.Therefore, when drawing metal-oxide-semiconductor 101 to end on described first, because the voltage ZVDD2_PLUS of described tertiary voltage end can reduce to flow through the leakage current that draws metal-oxide-semiconductor 101 on described first like this greater than the voltage ZVDD2 of described first working end.
Need to prove, in embodiment one, because in described level shift circuit, therefore the described first operating voltage ZVDD2 is high voltage (2.5V), and drawing on described first and drawing metal-oxide-semiconductor 102, the described first drop-down metal-oxide-semiconductor 103 and the described second drop-down metal-oxide-semiconductor 104 on the metal-oxide-semiconductor 101, described second all is high-voltage tube.But be to use high-voltage tube to have certain defective, enter operating state because the shared circuit area of high-voltage tube is big and need higher operating voltage to drive high-voltage tube usually, therefore at the problems referred to above, the inventor also provides further improved technical scheme, and is specific as follows:
The second embodiment schematic diagram with reference to level shift circuit shown in Figure 4.Described level shift circuit has increased power supply circuits 106 on the basis of Fig. 3, described power supply circuits 106 are used for providing second operating voltage to the described first drop-down metal-oxide-semiconductor 103 and the described second drop-down metal-oxide-semiconductor 104.Particularly, the input IN2 of described power supply circuits 106 is connected with peripheral circuit 11, described power supply circuits 106 respectively with described first on draw in the drain electrode, described second of metal-oxide-semiconductor 101 draw the drain electrode of metal-oxide-semiconductor 102 to be connected, the drain electrode of the described first drop-down metal-oxide-semiconductor 103, the drain electrode of the described second drop-down metal-oxide-semiconductor 104 be connected, to the described first drop-down metal-oxide-semiconductor 103 and second drop-down metal-oxide-semiconductor 104 outputs second operating voltage.
In the present embodiment, alternatively, described power supply circuits 106 comprise first high-voltage tube 1061 and second high-voltage tube 1062, and alternatively, wherein said first high-voltage tube 1061 and described second high-voltage tube 1062 are N channel-type metal-oxide-semiconductors.Wherein, the grid of described first high-voltage tube 1061 be the input of described power supply circuits 106, described first high-voltage tube 1061 and the grid of described second high-voltage tube 1062 input, described first high-voltage tube 1061 and described second high-voltage tube 1062 that are connected in described power supply circuits 106 drain electrode respectively with described first on draw on the metal-oxide-semiconductor 101 and described second and draw the drain electrode of metal-oxide-semiconductor 102 to be connected, the source electrode of described first high-voltage tube 1061 and described second high-voltage tube 1062 is connected with the drain electrode of the described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 respectively.
Particularly, the input IN2 of described power supply circuits 106 receives from the voltage VB (not shown) on the peripheral circuit 11, and described voltage VB can be for described first high- voltage tube 1061 and 1062 work of second high-voltage tube.Wherein, greater than the threshold voltage vt of described first high-voltage tube 1061 and second high-voltage tube 1062, alternatively, in the present embodiment, described voltage VB is VDD+Vt to described voltage VB at least, and wherein said VDD is 1.8V.Then, provide second operating voltage to the described first drop-down metal-oxide-semiconductor 103 and the described second drop-down metal-oxide-semiconductor 104 respectively by described power supply circuits 106, in the present embodiment, described second operating voltage is VDD.Need to prove, because described voltage VB also is the required voltage of flash memory system when standby, so can not increase extra area.
Different with embodiment one is, because is low-voltage by described power supply circuits 106 for second operating voltage that the described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 provide, the described like this first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 can use low-voltage tube.Improved like this benefit is, because the area of the higher pressure pipe of area of low-voltage tube is littler, therefore reduces the size of described level shift circuit to a great extent.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (11)
1. flash memory circuit, at least comprise peripheral circuit and column decode circuitry, wherein said column decode circuitry comprises level shift circuit, word line is selected circuit and is driven latch cicuit, wherein said level shift circuit comprises: draw on first on metal-oxide-semiconductor and second and draw metal-oxide-semiconductor, the first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor and first inverter, it is characterized in that, the source electrode of the source electrode of the described first drop-down metal-oxide-semiconductor and the described second drop-down metal-oxide-semiconductor is connected to first voltage end and second voltage end, the voltage of wherein said first voltage end is greater than the grid voltage of the first drop-down metal-oxide-semiconductor, and the voltage of described second voltage end is greater than the grid voltage of the second drop-down metal-oxide-semiconductor; Drawing on described first on the substrate and described second of metal-oxide-semiconductor draws the substrate of metal-oxide-semiconductor to be connected to tertiary voltage end and the 4th voltage end, the voltage of wherein said tertiary voltage end is greater than the source voltage that draws metal-oxide-semiconductor on described first, and the voltage of described the 4th voltage end is greater than the source voltage that draws metal-oxide-semiconductor on described second.
2. flash memory circuit according to claim 1, it is characterized in that, draw the source electrode that draws metal-oxide-semiconductor on metal-oxide-semiconductor and second to be connected on the first operating voltage end on first described in the described level shift circuit, draw the grid of metal-oxide-semiconductor to be connected to the drain electrode of drawing metal-oxide-semiconductor on second on described first, draw the grid of metal-oxide-semiconductor to be connected to the drain electrode of drawing metal-oxide-semiconductor on first on described second; The grid of the described first drop-down metal-oxide-semiconductor is connected to the input of described level shift circuit, draw the drain electrode of drawing metal-oxide-semiconductor on metal-oxide-semiconductor and second to be connected to form two outputs with the drain electrode of the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively on described first, the input of described first inverter is connected in the grid of the described first drop-down metal-oxide-semiconductor, and output is connected in the grid of the described second drop-down metal-oxide-semiconductor.
3. flash memory circuit according to claim 1 is characterized in that, first voltage end described in the described level shift circuit is the output of described first inverter.
4. flash memory circuit according to claim 1 is characterized in that, second voltage end described in the described level shift circuit is the input of described first inverter.
5. flash memory circuit according to claim 1 and 2, it is characterized in that, described peripheral circuit comprises voltage regulator circuit at least, described voltage regulator circuit links to each other with the first operating voltage end, tertiary voltage end and the 4th voltage end, and described voltage regulator circuit produces the voltage of the voltage of the described first operating voltage end, described tertiary voltage end and the voltage of described the 4th voltage end.
6. flash memory circuit according to claim 5 is characterized in that, the voltage of the voltage of described tertiary voltage end and described the 4th voltage end equates.
7. flash memory circuit according to claim 5 is characterized in that, described voltage regulator circuit comprises multistage charge pump, single-stage charge pump, comparison controller and commutation circuit; Described single-stage charge pump is connected in described multistage electric charge delivery side of pump; Described comparison controller and single-stage electric charge delivery side of pump are connected in the input of described commutation circuit; The output of described commutation circuit is exported the voltage of the voltage of the described first operating voltage end, described tertiary voltage end and the voltage of described the 4th voltage end respectively.
8. flash memory circuit according to claim 2, it is characterized in that, also comprise power supply circuits in the described level shift circuit, the input of wherein said power supply circuits is connected with peripheral circuit, described power supply circuits respectively with described first on draw in the drain electrode, described second of metal-oxide-semiconductor draw the drain electrode of metal-oxide-semiconductor to be connected, the drain electrode of the described first drop-down metal-oxide-semiconductor, the drain electrode of the described second drop-down metal-oxide-semiconductor be connected, and exports second operating voltage to the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor.
9. flash memory circuit according to claim 8, it is characterized in that, described power supply circuits comprise first high-voltage tube and second high-voltage tube, the drain electrode that wherein said first high-voltage tube and the grid of second high-voltage tube are connected in the input of described power supply circuits, described first high-voltage tube and second high-voltage tube respectively with described first on draw and draw the drain electrode of metal-oxide-semiconductor to be connected on the metal-oxide-semiconductor and second, the source electrode of described first high-voltage tube and second high-voltage tube is connected with the drain electrode of the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively; The described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are low-voltage tubes.
10. flash memory circuit according to claim 9 is characterized in that, described first high-voltage tube and described second high-voltage tube are N channel-type metal-oxide-semiconductors.
11. flash memory circuit according to claim 1 is characterized in that, drawing on first described in the described level shift circuit and drawing metal-oxide-semiconductor on metal-oxide-semiconductor and second is P channel-type metal-oxide-semiconductor, and the described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are N channel-type metal-oxide-semiconductors.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN113258910A (en) * | 2021-06-25 | 2021-08-13 | 中科院微电子研究所南京智能技术研究院 | Computing device based on pulse width modulation |
| CN113258910B (en) * | 2021-06-25 | 2021-10-19 | 中科院微电子研究所南京智能技术研究院 | Computing device based on pulse width modulation |
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