CN102122767A - Expanding interconnecting component - Google Patents
Expanding interconnecting component Download PDFInfo
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- CN102122767A CN102122767A CN 201010042688 CN201010042688A CN102122767A CN 102122767 A CN102122767 A CN 102122767A CN 201010042688 CN201010042688 CN 201010042688 CN 201010042688 A CN201010042688 A CN 201010042688A CN 102122767 A CN102122767 A CN 102122767A
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Abstract
The invention is applicable to the field of the signal transmission and provides an expanding interconnecting component. The expanding interconnecting component comprises a first printed circuit board (PCB), a second PCB and a signal interconnector for connecting the first PCB and the second PCB. Signal returning paths of the first PCB, the second PCB and the signal interconnector are all arranged on the ground plane. The pins of the returning paths and the pins of signals are adjacently arranged on the signal interconnector. The signals comprise a high-speed signal and a clock signal. By the expanding interconnecting component, the signal returning path of the first PCB, the signal returning path of the second PCB and the signal returning path of the signal interconnector for connecting the first PCB and the second PCB are all arranged on the ground plane with equal electric potential and the same attribute, so reference planes before and after signal transfer are the same, the loop area of signal is the minimum, the electromagnetic interference is reduced, the loop impedance of signal is minimized and continuous, and seamless connection between signals and signal integrality are realized.
Description
Technical field
The invention belongs to field of signal transmissions, relate in particular to a kind of expansion interconnecting assembly.
Background technology
Along with the high speed development of electronics, the electric and communication technology, integrated level is more and more higher, more and more miniaturization of product, miniaturization, and therefore, the volume of a holonomic system will be more and more littler, function is more and more.This will be referred to the design and the application of a lot of key technologies, such as: the compatibility of each subsystem, signal how smoothly interconnection expand, collaborative work or the like between rational deployment, the system on the structure; One of them crucial technology is exactly the interconnection expansion between the signal.
Electronic apparatus of today, communication products function are from strength to strength, generally be difficult in a separate payment or a standalone module and realize the needed various difference in functionalitys of people, but need between each subsystem or the submodule combination, collaborative work mutually to finish, and these subsystems or submodule generally all are at printed circuit board (Printed Circuit Board, PCB) realize on, use expansion connectors miscellaneous (such as DIN connector, slot jack, golden finger etc.) to finish the expansion interconnection of signal simultaneously.Yet various signals can not only be factors such as simple electrical connection in logic, the seamless interconnection of necessary consideration signal, compatibility, integrality, otherwise the properties of product that design are defective, even function all can not normally realize.
Prior art especially can occur in the design of multilayer (four layers and more than) circuit board mainly in two kinds of situation; First kind of situation: high speed signal or clock signal are in the front and back of adopting the switching of signal interconnection device, and its plane of reference all is power plane (may be equipotential power plane, also may be non-equipotential power plane); Second kind of situation: high speed signal or clock signal are in the front and back of adopting the switching of signal interconnection device, and one of its plane of reference is a ground level, and another is a power plane.For the compatibility issue that both of these case produces, mainly by increasing tank capacitance, this electric capacity is connected between the different plane of references existing design solution, and need be according to the quantity of actual experiment verification the verifying results increase and decrease electric capacity.
Yet but there is the deficiency of the following aspects in prior art: (1) cost height: the increase of electric capacity quantity, the electric capacity via hole increase on the printed circuit board etc. all can bring the increase of cost; (2) effect of electromagnetic compatibility does not have absolute assurance: at first, different electric capacity, it presents capacitive low-impedance frequency range is limited, and the noise on integrated circuit board is countless, so non-constant width of the frequency bandwidth of noise, also there are multiple harmonic in useful high speed signal and clock signal, so by the loop cross structure existence very big hidden danger of electric capacity as a high speed signal or clock signal; Secondly, the increase of electric capacity causes the increase of via hole, so just further destroys the integrality of power plane or ground level; Once more, the impedance phase of power plane is for ground level and Yan Yaoda, and power plane also is easy to produce the shake of level, thereby the noise that power plane produces is also many than ground level; (3) in some cases, increased the burden on the board space structure and layout: such as, to some very little integrated circuit boards or the integrated circuit board of embedded functional is arranged, increase extra electric capacity, on structure and layout, can produce a bottleneck, or because the height of device, or because electric capacity cloth does not descend or the like; (4) destroy the electromagnetic environment that other is in poised state easily: such as, near original electromagnetic environment this tank capacitance has reached the requirement of balance of designer's expection, there is not to produce electromagnetic interference (the Electro-magnetic Interference that does not expect, EMI) problem, but, may destroy original electromagnetic balance environment, thereby bring some extra electromagnetic interference problems because of after having increased such capacitor loop.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of expansion interconnecting assembly, is intended to solve in the prior art before and after the signal converting on the signal interconnection device that the return flow path difference causes the signal circuit area big on pcb board, and impedance is discontinuous, problems such as poor compatibility.
The embodiment of the invention is achieved in that a kind of expansion interconnecting assembly, and it comprises first pcb board, second pcb board and the signal interconnection device that is used to connect described first pcb board and described second pcb board; The return flow path of the signal of described first pcb board, described second pcb board and described signal interconnection device is ground level, the adjacent setting on the signal interconnection device of the stitch of described return flow path and the stitch of described signal, described signal comprises high speed signal and clock signal.
Further, described first pcb board is a multi-layer PCB board, and described second pcb board is a multi-layer PCB board, and described multi-layer PCB board is the pcb board more than or equal to four layers, and described multi-layer PCB board comprises: signal lead layer, stratum and bus plane; The return flow path of the signal of the described signal lead layer of described multi-layer PCB board is described ground level.
Further, described stratum and the adjacent setting of described signal lead layer, described stratum is described ground level, the return flow path of the signal of the described signal lead layer of multi-layer PCB board is described stratum.
Further, described bus plane and the adjacent setting of described signal lead layer, described high speed signal and the mirror position of described clock signal on described bus plane are attached with the ground copper sheet, described ground copper sheet is described ground level, and the return flow path of the signal of the described signal lead layer of multi-layer PCB board is a described ground copper sheet.
Further, described signal lead layer is between described bus plane and described stratum, distance between described signal lead layer and the described stratum is less than the distance between described signal lead layer and the described bus plane, described stratum is described ground level, and the return flow path of the signal of the described signal lead layer of multi-layer PCB board is described stratum.
Further, described signal lead layer is between described bus plane and described stratum, distance between described signal lead layer and the described stratum is greater than the distance between described signal lead layer and the described bus plane, described high speed signal and the mirror position of described clock signal on described bus plane are attached with the ground copper sheet, described ground copper sheet is described ground level, and the return flow path of the signal of the described signal lead layer of multi-layer PCB board is a described ground copper sheet.
Further, described signal interconnection device comprises: the stitch unit, first ground that is connected with described ground level and one or more clock signal stitch that is used for transmit clock signal; Stitch unit, described first ground comprises one or more first ground stitch, have one first ground stitch and the adjacent setting of clock signal stitch at least, control the loop transfer impedance of described clock signal with the first ground stitch of the adjacent setting of described clock signal stitch, reduce the loop area of clock signal.
Further, described signal interconnection device also comprises: the stitch unit, second ground that is connected with described ground level and one or more high speed signal stitch that is used for transmit high-speed signals; Stitch unit, described second ground comprises a plurality of second ground stitch, two high speed signal stitch and one second adjacent setting of ground stitch at the most, control the loop transfer impedance of described high speed signal with the second ground stitch of the adjacent setting of described high speed signal stitch, reduce the loop area of high speed signal.
Further, described signal interconnection device also comprises: the stitch unit, the 3rd ground that is connected with described ground level and a plurality of low speed signal stitch that is used to transmit low speed signal; Stitch unit, described the 3rd ground comprises a plurality of the 3rd ground stitch, the adjacent setting of any one low speed signal stitch in one the 3rd ground stitch and N the low speed signal stitch, control the transfer impedance of described low speed signal stitch with the 3rd ground stitch of the adjacent setting of described low speed signal stitch, reduce the loop area of low speed signal, provide effective reference point to low speed signal; Described N is less than or equal to 20 natural number.
Further, the clock signal zone is by the first ground stitch or the second ground stitch and high speed signal zone isolation, the high speed signal zone is by the second ground stitch or the 3rd stitch and low speed signal zone isolation, and the low speed signal zone is by the 3rd ground stitch or the first ground stitch and described clock signal zone isolation; Described clock signal zone is for being provided with the zone of one or more clock signal stitch; Described high speed signal zone is for being provided with the zone of one or more high speed signal stitch; Described low speed signal zone is for being provided with the zone of a plurality of low speed signal stitch.
Expansion interconnecting assembly provided by the invention with the signal plane of reference of the signal plane of reference of first pcb board, second pcb board and the signal plane of reference that is used to connect the signal interconnection device of first pcb board and second pcb board all be set to equipotential ground level, make that the plane of reference before and after the signal converting is identical, thereby make the loop area minimum of signal, reduced electromagnetic interference, the impedance loop that has guaranteed signal minimizes and continuity, has realized the seamless link and the signal integrity of signal.
Description of drawings
Fig. 1 is a kind of modular structure schematic diagram of expanding interconnecting assembly that the embodiment of the invention provides;
Fig. 2 is the pin structure schematic diagram of signal interconnection device in the expansion interconnecting assembly that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Expansion interconnecting assembly provided by the invention with the signal plane of reference of the signal plane of reference of first pcb board, second pcb board and the signal plane of reference that is used to connect the signal interconnection device of first pcb board and second pcb board all be set to equipotential ground level, make that the plane of reference before and after the signal converting is identical.
Fig. 1 shows a kind of modular structure of expanding interconnecting assembly that the embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with the embodiment of the invention, and details are as follows.
A kind of interconnecting assembly of expanding comprises first pcb board 1, second pcb board 3 and the signal interconnection device 2 that is used to connect first pcb board 1 and second pcb board 3; The return flow path of the signal of first pcb board 1, second pcb board 3 and signal interconnection device 2 is ground level 4, the adjacent setting on signal interconnection device 2 of the stitch of return flow path and the stitch of signal, and signal comprises high speed signal and clock signal.
In embodiments of the present invention, first pcb board 1 is a multi-layer PCB board; Second pcb board 3 is a multi-layer PCB board; Multi-layer PCB board is the pcb board more than or equal to four layers, and multi-layer PCB board comprises: signal lead layer, stratum and bus plane; The return flow path of the signal of the above-mentioned signal lead layer of multi-layer PCB board is a ground level.
As one embodiment of the present of invention, when with the adjacent setting of signal lead layer have only the stratum time, the stratum is a ground level, the return flow path of the signal of the above-mentioned signal lead layer of multi-layer PCB board is the stratum.
As one embodiment of the present of invention, when with the adjacent setting of signal lead layer have only bus plane the time, high speed signal and the clock signal mirror position on bus plane is attached with the ground copper sheet, and the ground copper sheet is a ground level, and the return flow path of the signal of the above-mentioned signal lead layer of multi-layer PCB board is the ground copper sheet.Wherein, can make the ground copper sheet be attached to high speed signal and the mirror position of clock signal on bus plane by the means of laying.
As one embodiment of the present of invention, when the signal lead layer between bus plane and stratum, and the distance between signal lead layer and the stratum less than between signal lead layer and the bus plane apart from the time, the stratum is a ground level, and the return flow path of the signal of the above-mentioned signal lead layer of multi-layer PCB board is the stratum.
As one embodiment of the present of invention, when the signal lead layer between bus plane and stratum, and the distance between signal lead layer and the stratum is greater than the distance between signal lead layer and the bus plane, high speed signal and the clock signal mirror position on bus plane is attached with the ground copper sheet, the ground copper sheet is a ground level, and the return flow path of the signal of the above-mentioned signal lead layer of multi-layer PCB board is the ground copper sheet.
For a high speed signal or clock signal, if in the design of signal circuit, have defective, will produce very big electromagnetic compatibility problem so, particularly the radiated emission problem also can cause the problem on the function when serious.Here said defective be meant same high speed signal or clock signal by signal interconnection device 2 when first pcb board 1 is transferred on second pcb board 3, its loop area and impedance loop do not require design according to minimizing, particularly for the design of multilayer (four layers and more than) pcb board, more difficultly accomplish such requirement well.It is as follows now with the clock signal to be that example specifies: it is complete ground level that the plane of reference of clock signal on first pcb board 1 is set, and on signal interconnection device 2, to be defined as the earth signal of the plane of reference with the clock signal adjacent stitches, when the clock signal was transferred on second pcb board 3 by signal interconnection device 2, the plane of reference of second pcb board 3 was equipotential ground levels that same alike result is arranged with the plane of reference of first pcb board 1; The loop area minimum, the impedance loop that have so just guaranteed clock signal are minimum and continuous.
In the expansion interconnecting assembly that the embodiment of the invention provides, signal interconnection device 2 is to be applied to two expansion interconnection between the integrated circuit board, and seamless interconnection, signal compatibility and the signal integrity of signal comprehensively considered in the stitch definition of this signal interconnection device 2; Wherein, signal compatibility be meant in a complete circuit or pcb board on, do not produce mutually between all signals and disturb, or can not exert an influence to normal function because of the interference that produces; Signal integrity is meant the quality of signal on holding wire, mainly comprises the overshoot and the damped oscillation phenomenon of signal.
In embodiments of the present invention, signal interconnection device 2 comprises: stitch unit, first ground and one or more clock signal stitch that is used for transmit clock signal; Wherein stitch unit, first ground is connected with ground level 4, stitch unit, first ground comprises one or more first ground stitch, have one first ground stitch and the adjacent setting of clock signal stitch at least, the transfer impedance of control clock signal stitch, reduce the loop area of clock signal, make clock signal that the loop of low-impedance a, minimum area be arranged.
In embodiments of the present invention, signal interconnection device 2 also comprises: stitch unit, second ground and one or more high speed signal stitch that is used for transmit high-speed signals; Stitch unit, second ground is connected with ground level 4, stitch unit, second ground comprises a plurality of second ground stitch, two high speed signal stitch and one second adjacent setting of ground stitch at the most, transfer impedance with the second ground stitch control high speed signal stitch of the adjacent setting of high speed signal stitch, reduce the loop area of high speed signal, make high speed signal have one low-impedance, than the loop of small size.
In embodiments of the present invention, signal interconnection device 2 also comprises: a plurality of low speed signal stitch and stitch unit, the 3rd ground that are used to transmit low speed signal; Stitch unit, the 3rd ground is connected with ground level 4, stitch unit, the 3rd ground comprises a plurality of the 3rd ground stitch, the adjacent setting of any one low speed signal stitch in one the 3rd ground stitch and N the low speed signal stitch, control the transfer impedance of described low speed signal stitch with the 3rd ground stitch of the adjacent setting of low speed signal stitch, reduce the loop area of low speed signal; Provide an effective loop to low speed signal; Also provide more effectively reference point simultaneously to low speed signal; N is less than or equal to 20 natural number.
In embodiments of the present invention, for high speed signal and clock signal, the factor that influences its impedance is a lot, is minimum based on the impedance phase of ground level for the impedance on other plane, so choosing ground stitch is to reach low-impedance requirement.For high speed signal and clock signal, its loop is along the minimum path flow of impedance, and is close to the holding wire fasciculation, concentrates on holding wire below, and the physical distance of signal source and load reaches minimum, and the signal circuit area of this moment is just thought and reached minimum.As one embodiment of the present of invention, clock signal is meant the signal of telecommunication of fundamental frequency more than or equal to 5MHz; High speed signal is meant that the rise time is more than or equal to the signal of telecommunication of 5ns or the operating frequency signal of telecommunication more than or equal to 5MHz.
Because on integrated circuit board, ground level is for power plane, the impedance of ground level is wanted little and continuity also will be got well, so selectively the plane is as signal circuit, this just need reasonably define the ground stitch on the signal interconnection device.Simultaneously, if signal from the source end after load end, its return path is bigger, the radiated emission energy just must be stronger so, and be easy to be subjected to crosstalking, disturbing of other signals.And the principle of return path is: for low speed signal, its loop is the minimum path of resistance, and the surface current wider distribution, and for high speed signal, its loop is along the minimum path flow of impedance, and is close to the holding wire fasciculation, concentrate on the holding wire below, and have skin effect; Therefore if a signal is not set a low-impedance return path, it must select a low relatively path to return so, and such return path is unpredictable often and control, thereby must cause the increase of loop area.In embodiments of the present invention, by the adjacent position at clock signal stitch or high speed signal stitch be provided with ground stitch, appropriate design signal circuit, reduced the signal circuit area, guaranteed impedance loop and impedance continuity that signal is lower.
Compared with prior art, the expansion interconnecting assembly that the embodiment of the invention provides has following advantage: (1) does not increase extra cost: the plane of reference of signal before and after switching all is ground level, so do not need to increase the backflow that extra electric capacity guarantees signal; (2) effect of electromagnetic compatibility has obtained guaranteeing effectively: at first, loop characteristic according to high speed signal and clock signal, adopt the expansion interconnecting assembly that the embodiment of the invention provides can be, thereby reduced electromagnetic interference so that the area of signal circuit reaches to minimize; Secondly, guaranteed that the impedance loop of signal minimizes and continuity, for other plane of references, the impedance of ground level is minimum, and be most complete, reduced the integrity issues such as shake, reflection of signal, therefore can take into account signal integrity and electric capacity compatibility; (3) need not consider to increase bottleneck on the structure and layout that electric capacity brings; (4) can not destroy original electromagnetic balance environment on the integrated circuit board.
Fig. 2 shows the pin structure schematic diagram of signal interconnection device in the expansion interconnecting assembly that the embodiment of the invention provides, for convenience of explanation, only show the signal interconnection device pin structure schematic diagram of the product that adopts DIN connector, as we can see from the figure, 22 pairs of different power supply signals 21 of earth signal are isolated, particularly on the clock signal adjacent stitches in the isa bus signal, by selecting the signal return flow path of low-impedance ground stitch for use, in the middle of the ISA signal reasonably layout some earth signals, and near the high relatively signal area placement of speed, particularly for clock signal, earth signal of definition is adjacent separately, has reduced loop area greatly; And through experimental verification, the signal interconnection device that adopts the embodiment of the invention to provide all can reach radiation B level 4dB surplus (PEAK value), meets radiation standard, meets the demands.The signal interconnection device that the embodiment of the invention provides has solved that the signal circuit area is big, impedance loop causes greatly that signal is crosstalked mutually, the incomplete problem of signal.
In embodiments of the present invention, the clock signal zone is by the first ground stitch or the second ground stitch and high speed signal zone isolation, the high speed signal zone is by the second ground stitch or the 3rd stitch and low speed signal zone isolation, and the low speed signal zone is by the 3rd ground stitch or the first ground stitch and clock signal zone isolation; The clock signal zone is for being provided with the zone of one or more clock signal stitch; The high speed signal zone is for being provided with the zone of one or more high speed signal stitch; The low speed signal zone is for being provided with the zone of a plurality of low speed signal stitch.
Continuous development along with technology, speed, the frequency of digital signal are more and more higher, and analog signal also is easy to be subjected to the interference of digital signal, the space of pcb board is again more limited, if so not design as requested, it will be very big producing the probability of interference and the energy of interference, even have influence on the normal function of product sometimes.For example: a kind of peripheral element extension interface of compactness (Compact PeripheralComponent Interconnect, CPCI) product is not because reasonably distinguish signal of different nature, caused the function of this CPCI product to be subjected to tangible influence, its reason is: the senior connection of serial (SerialAdvanced Technology Attachment, SATA) signal pins and low-voltage differential (Low VoltageDifferential Signaling, LVDS) stitch of clock signal is adjacent, the result causes the SATA signal to be subjected to very large disturbance, and appearance can't enter the phenomenon of system; By improving, high speed signal SATA signal and low-voltage differential clock signal land used stitch are kept apart, solved above-mentioned problem of crosstalking.Therefore, in embodiments of the present invention, dissimilar signals is set, with high speed signal, low speed signal, clock signal, sensitive signal etc. separately, and adopts the ground stitch to isolate by subregion, solved between the unlike signal crosstalk mutually, problem such as coupling.
In embodiments of the present invention, the stitch of signal interconnection device 2 generally select for use short, thin, density is appropriate, firm contacting structure; And the connectors that metal shell is arranged will guarantee that the metal shell of the connectors of the connectors of male and female is electrically connected; Reduced the physical impedance of connectors like this, reduced the space radiation of connectors generation and the coupling between the signal, reduced the mutability of signal impedance, thereby guaranteed the reliability that the junction is electrically connected.For example, expansion embedded (Embedded Technology Extended, ETX) stitch of connector is just relatively shorter and thin, and resistance is 45m Ω under the direct current of 100mA, this is a reasonable connector, but it is exactly built on the sand that a shortcoming is arranged; CPCI connector for example again, its length just has the consideration signal integrity, and thickness also has concrete regulation, and has considered to shield with metal shell, and connectivity is also relatively firm, reliable; The employed connector stitch of some other product is very thick, long, and compares comparatively dense.In the present invention, can select the proper signal interconnection device of some stitch by artificial, thus solved since the stitch of connectors long, excessive, cross and thick or overstockedly cause the impedance sudden change and unmatched problem.
Expansion interconnecting assembly provided by the invention with the signal plane of reference of the signal plane of reference of first pcb board, second pcb board and the signal plane of reference that is used to connect the signal interconnection device of first pcb board and second pcb board all be set to equipotential ground level, make that the plane of reference before and after the signal converting is identical, thereby make the loop area minimum of signal, reduced electromagnetic interference, guaranteed that the impedance loop of signal minimizes and continuity; The seamless link and the signal integrity of signal have been realized.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. expand interconnecting assembly for one kind, it comprises first pcb board, second pcb board and the signal interconnection device that is used to connect described first pcb board and described second pcb board; It is characterized in that, the return flow path of the signal of described first pcb board, described second pcb board and described signal interconnection device is ground level, the adjacent setting on the signal interconnection device of the stitch of described return flow path and the stitch of described signal, described signal comprises high speed signal and clock signal.
2. expansion interconnecting assembly as claimed in claim 1, it is characterized in that described first pcb board is a multi-layer PCB board, described second pcb board is a multi-layer PCB board, described multi-layer PCB board is the pcb board more than or equal to four layers, and described multi-layer PCB board comprises: signal lead layer, stratum and bus plane; The return flow path of the signal of the described signal lead layer of described multi-layer PCB board is described ground level.
3. expansion interconnecting assembly as claimed in claim 2 is characterized in that, described stratum and the adjacent setting of described signal lead layer, and described stratum is described ground level, the return flow path of the signal of the described signal lead layer of multi-layer PCB board is described stratum.
4. expansion interconnecting assembly as claimed in claim 2, it is characterized in that, described bus plane and the adjacent setting of described signal lead layer, described high speed signal and the mirror position of described clock signal on described bus plane are attached with the ground copper sheet, described ground copper sheet is described ground level, and the return flow path of the signal of the described signal lead layer of multi-layer PCB board is a described ground copper sheet.
5. expansion interconnecting assembly as claimed in claim 2, it is characterized in that, described signal lead layer is between described bus plane and described stratum, distance between described signal lead layer and the described stratum is less than the distance between described signal lead layer and the described bus plane, described stratum is described ground level, and the return flow path of the signal of the described signal lead layer of multi-layer PCB board is described stratum.
6. expansion interconnecting assembly as claimed in claim 2, it is characterized in that, described signal lead layer is between described bus plane and described stratum, distance between described signal lead layer and the described stratum is greater than the distance between described signal lead layer and the described bus plane, described high speed signal and the mirror position of described clock signal on described bus plane are attached with the ground copper sheet, described ground copper sheet is described ground level, and the return flow path of the signal of the described signal lead layer of multi-layer PCB board is a described ground copper sheet.
7. expansion interconnecting assembly as claimed in claim 1 is characterized in that, described signal interconnection device comprises: the stitch unit, first ground that is connected with described ground level and one or more clock signal stitch that is used for transmit clock signal;
Stitch unit, described first ground comprises one or more first ground stitch, have one first ground stitch and the adjacent setting of clock signal stitch at least, control the loop transfer impedance of described clock signal with the first ground stitch of the adjacent setting of described clock signal stitch, reduce the loop area of clock signal.
8. expansion interconnecting assembly as claimed in claim 7 is characterized in that, described signal interconnection device also comprises: the stitch unit, second ground that is connected with described ground level and one or more high speed signal stitch that is used for transmit high-speed signals;
Stitch unit, described second ground comprises a plurality of second ground stitch, two high speed signal stitch and one second adjacent setting of ground stitch at the most, control the loop transfer impedance of described high speed signal with the second ground stitch of the adjacent setting of described high speed signal stitch, reduce the loop area of high speed signal.
9. expansion interconnecting assembly as claimed in claim 8 is characterized in that, described signal interconnection device also comprises: the stitch unit, the 3rd ground that is connected with described ground level and a plurality of low speed signal stitch that is used to transmit low speed signal;
Stitch unit, described the 3rd ground comprises a plurality of the 3rd ground stitch, the adjacent setting of any one low speed signal stitch in one the 3rd ground stitch and N the low speed signal stitch, control the transfer impedance of described low speed signal stitch with the 3rd ground stitch of the adjacent setting of described low speed signal stitch, reduce the loop area of low speed signal, provide effective reference point to low speed signal; Described N is less than or equal to 20 natural number.
10. expansion interconnecting assembly as claimed in claim 9, it is characterized in that, the clock signal zone is by the first ground stitch or the second ground stitch and high speed signal zone isolation, the high speed signal zone is by the second ground stitch or the 3rd stitch and low speed signal zone isolation, and the low speed signal zone is by the 3rd ground stitch or the first ground stitch and described clock signal zone isolation;
Described clock signal zone is for being provided with the zone of one or more clock signal stitch; Described high speed signal zone is for being provided with the zone of one or more high speed signal stitch; Described low speed signal zone is for being provided with the zone of a plurality of low speed signal stitch.
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| CN 201010042688 CN102122767B (en) | 2010-01-08 | 2010-01-08 | Expanding interconnecting component |
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| CN 201010042688 CN102122767B (en) | 2010-01-08 | 2010-01-08 | Expanding interconnecting component |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521934A (en) * | 2011-12-14 | 2012-06-27 | 福建三元达软件有限公司 | Method for solving problem of electromagnetic interference of handheld point-of-sale (POS) terminal |
| CN110113864A (en) * | 2019-05-11 | 2019-08-09 | 武汉精立电子技术有限公司 | A kind of PCB pin layout method and structure of module board, module board |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6692272B2 (en) * | 2001-11-14 | 2004-02-17 | Fci Americas Technology, Inc. | High speed electrical connector |
| US7471520B2 (en) * | 2005-03-10 | 2008-12-30 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Impedance matching external component connections with uncompensated leads |
| CN1949953A (en) * | 2006-11-01 | 2007-04-18 | 华为技术有限公司 | Wiring method for printed circuitboard and printed circuitboard |
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2010
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521934A (en) * | 2011-12-14 | 2012-06-27 | 福建三元达软件有限公司 | Method for solving problem of electromagnetic interference of handheld point-of-sale (POS) terminal |
| CN110113864A (en) * | 2019-05-11 | 2019-08-09 | 武汉精立电子技术有限公司 | A kind of PCB pin layout method and structure of module board, module board |
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| CN102122767B (en) | 2013-05-01 |
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