CN101938068A - Signal interconnector - Google Patents
Signal interconnector Download PDFInfo
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- CN101938068A CN101938068A CN2009101890550A CN200910189055A CN101938068A CN 101938068 A CN101938068 A CN 101938068A CN 2009101890550 A CN2009101890550 A CN 2009101890550A CN 200910189055 A CN200910189055 A CN 200910189055A CN 101938068 A CN101938068 A CN 101938068A
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- signal
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- speed signal
- clock signal
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Abstract
The invention provides a signal interconnector which is applicable to the field of signal transmission. The signal interconnector comprises a first ground pin unit and one or a plurality of clock signal pins for transmitting clock signals, wherein the first ground pin unit comprises one or a plurality of first ground pins, and at least one first ground pin is arranged adjacent to one clock signal pin. The first ground pin arranged adjacent to the clock signal pin is used for controlling the transmission impedance of the clock signal pin and reducing the area of a return circuit of the clock signals. The signal interconnector controls the effective transmission of the clock signals by arranging the ground pin in the adjacent position of the clock signal pin, so that the clock signals have a low-impedance return circuit. The area of the return circuit is reduced, the mutual crosstalk of the signals is avoided, and the seamless connection as well as the integrity and the compatibility of the signals are realized.
Description
Technical field
The invention belongs to field of signal transmissions, relate in particular to a kind of signal interconnection device.
Background technology
Along with the high speed development of electronics, the electric and communication technology, integrated level is more and more higher, more and more miniaturization of product, miniaturization, and therefore, the volume of a holonomic system will be more and more littler, function is more and more.This will be referred to the design and the application of a lot of key technologies, such as: the compatibility of each subsystem, signal how smoothly interconnection expand, collaborative work or the like between rational deployment, the system on the structure; One of them crucial technology is exactly the interconnection expansion between the signal.
Electronic apparatus of today, communication products function are from strength to strength, generally be difficult in a separate payment or a standalone module and realize the needed various difference in functionalitys of people, but need between each subsystem or the submodule combination, collaborative work mutually to finish, and these subsystems or submodule generally all are at printed circuit board (Printed Circuit Board, PCB) realize on, use expansion connectors miscellaneous (such as DIN connector, slot jack, golden finger etc.) to finish the expansion interconnection of signal simultaneously.Yet various signals can not only be factors such as simple electrical connection in logic, the seamless interconnection of necessary consideration signal, compatibility, integrality, otherwise the properties of product that design are defective, even function all can not normally realize.
Fig. 1 shows the connector pin leg structure schematic diagram of the product of the employing DIN connector that prior art provides.The signal definition mode of this stitch is: power supply and earth signal 11 are set together, and isa bus signal 12 (that is: " signal " zone among the figure) is set together.But as everybody knows, include clock signal in the isa bus signal 12, and the stitch signal definition mode of Fig. 1 is not considered the loop problem of this clock signal, thereby cause loop area very big, cause radiated emission not up to standard then.
Because clock signal must have the loop, if can not give the loop of Low ESR of the artificial design of signal, minimum area, signal will oneself go to select a low-impedance loop so, and this loop also can be in the nearer place from this signal scarcely, even might be to return from the cabinet metal shell, so just caused loop area big especially; And also having portion of energy scatters on other paths, particularly when a plurality of signals have such loop, their energy will superpose, crosstalk mutually, can cause sizable radiated emission, (Signal Integrity SI), thereby influences normal function can to cause some signal integrity under the serious situation.
In addition, only digital signal and analog signal have been carried out the subregion setting in the prior art, yet do not carry out rational subregion between heterogeneity, the dissimilar signal, be not have the subregion setting between high speed signal, low speed signal, clock signal, the sensitive signal, intersection between them is mixed can increase coupling, causes crosstalking or interference problem between the unlike signal.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of signal interconnection device, is intended to solve that signal circuit area in the prior art is big, impedance loop big, signal expanding the problem that stitch definition on the connectors and layout unreasonablely cause signal to be crosstalked mutually, signal is imperfect, incompatible.
The embodiment of the invention is achieved in that a kind of signal interconnection device, and described signal interconnection device comprises: stitch unit, first ground and one or more clock signal stitch that is used for transmit clock signal; Stitch unit, described first ground comprises one or more first ground stitch, have one first ground stitch and the adjacent setting of clock signal stitch at least, control the transfer impedance of described clock signal stitch with the first ground stitch of the adjacent setting of described clock signal stitch, reduce the loop area of clock signal.
Further, described signal interconnection device also comprises: a plurality of high speed signal stitch and stitch unit, second ground that are used for transmit high-speed signals; Stitch unit, described second ground comprises a plurality of second ground stitch, two high speed signal stitch and one second adjacent setting of ground stitch at the most, control the transfer impedance of described high speed signal stitch with the second ground stitch of the adjacent setting of described high speed signal stitch, reduce the loop area of high speed signal.
Further, be provided with one second ground stitch between different two high speed signal stitch.
Further, described signal interconnection device also comprises: a plurality of low speed signal stitch and stitch unit, the 3rd ground that are used to transmit low speed signal; Stitch unit, described the 3rd ground comprises a plurality of the 3rd ground stitch, the adjacent setting of any one low speed signal stitch in one the 3rd ground stitch and N the low speed signal stitch, control the transfer impedance of described low speed signal stitch with the 3rd ground stitch of the adjacent setting of described low speed signal stitch, reduce the loop area of low speed signal; Described N is less than or equal to 20 natural number.
Further, the clock signal zone is by the first ground stitch or the second ground stitch and high speed signal zone isolation, the high speed signal zone is by the second ground stitch or the 3rd ground stitch and low speed signal zone isolation, and the low speed signal zone is by the 3rd ground stitch or the first ground stitch and described clock signal zone isolation; Described clock signal zone is for being provided with the zone of one or more clock signal stitch; Described high speed signal zone is for being provided with the zone of a plurality of high speed signal stitch; Described low speed signal zone is for being provided with the zone of a plurality of low speed signal stitch.
Further, described clock signal is the signal of telecommunication that fundamental frequency is not less than 5MHz.
Further, described high speed signal is to be not less than the signal of telecommunication of 5ns or the signal of telecommunication that operating frequency is not less than 5MHz the rise time.
Signal interconnection device provided by the invention is provided with the ground stitch by the adjacent position at the clock signal stitch, thereby effective transmission of control clock signal, make clock signal that a low-impedance loop be arranged, and reduced loop area, avoid signal to crosstalk mutually, realized the seamless link of signal and signal integrity, compatibility.
Description of drawings
Fig. 1 is the connector pin leg structure schematic diagram of the product of the employing DIN connector that provides of prior art,
Fig. 2 is the connector pin leg structure schematic diagram of the product of the employing DIN connector that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The signal interconnection device that the embodiment of the invention provides is provided with the ground stitch by the adjacent position at the clock signal stitch, thereby the transfer impedance of control clock signal stitch, make clock signal that a low-impedance loop be arranged, reduced loop area, avoid signal to crosstalk mutually, realized the seamless link and the signal integrity of signal.
The signal interconnection device that the embodiment of the invention provides is applied to the expansion interconnection between the integrated circuit board, and seamless interconnection, signal compatibility and the signal integrity of signal comprehensively considered in the stitch definition of this signal interconnection device; Wherein, signal compatibility be meant in a complete circuit or PCB on, do not produce mutually between all signals and disturb, or can not exert an influence to normal function because of the interference that produces; Signal integrity is meant the quality of signal on holding wire, mainly comprises the overshoot and the damped oscillation phenomenon of signal.
In embodiments of the present invention, the signal interconnection device comprises: stitch unit, first ground and one or more clock signal stitch that is used for transmit clock signal; Wherein stitch unit, first ground comprises one or more first ground stitch, has one first ground stitch and the adjacent setting of clock signal stitch at least, and the transfer impedance of control clock signal stitch reduces the loop area of clock signal; Make clock signal that the loop of low-impedance a, minimum area be arranged.
In embodiments of the present invention, the signal interconnection device also comprises: a plurality of high speed signal stitch and stitch unit, second ground that are used for transmit high-speed signals; Stitch unit, second ground comprises a plurality of second ground stitch, two high speed signal stitch and one second adjacent setting of ground stitch at the most, with the transfer impedance of the second ground stitch control high speed signal stitch of the adjacent setting of high speed signal stitch, reduce the loop area of high speed signal; Make high speed signal have one low-impedance, than the loop of small size.
In embodiments of the present invention, the signal interconnection device also comprises: a plurality of low speed signal stitch and stitch unit, the 3rd ground that are used to transmit low speed signal; Stitch unit, the 3rd ground comprises a plurality of the 3rd ground stitch, the adjacent setting of any one low speed signal stitch in one the 3rd ground stitch and N the low speed signal stitch, control the transfer impedance of described low speed signal stitch with the 3rd ground stitch of the adjacent setting of low speed signal stitch, reduce the loop area of low speed signal; Provide an effective loop to low speed signal; Also provide more effectively reference point simultaneously to low speed signal; N is less than or equal to 20 natural number.
As one embodiment of the present of invention, two power supply signals of different potentials can be isolated by the ground stitch, with the problem of avoiding power supply signal to crosstalk mutually.
In embodiments of the present invention, for high-frequency signal, high speed signal, the factor that influences its impedance is a lot, is minimum based on the impedance phase of ground level for the impedance on other plane, so choosing ground stitch is to reach low-impedance requirement.For high-frequency signal, high speed signal, its loop is along the minimum path flow of impedance, and is close to the holding wire fasciculation, concentrates on holding wire below, and the physical distance of signal source and load reaches minimum, and the signal circuit area of this moment is just thought and reached minimum.As one embodiment of the present of invention, clock signal is meant that fundamental frequency is not less than the signal of telecommunication of 5MHz; High speed signal is meant that the rise time is not less than the signal of telecommunication of 5ns or the signal of telecommunication that operating frequency is not less than 5MHz.
Because on integrated circuit board, ground level is for power plane, the impedance of ground level is wanted little and continuity also will be got well, so selectively the plane is as signal circuit, this just need reasonably define the ground stitch on the signal interconnection device.Simultaneously, if signal from the source end after load end, its return path is bigger, the radiated emission energy just must be stronger so, and be easy to be subjected to crosstalking, disturbing of other signals.And the principle of return path is: for low speed signal, its loop is the minimum path of resistance, and the surface current wider distribution, and for high speed signal, its loop is along the minimum path flow of impedance, and is close to the holding wire fasciculation, concentrate on the holding wire below, and have skin effect; Therefore if a signal is not set a low-impedance return path, it must select a low relatively path to return so, and such return path is unpredictable often and control, thereby must cause the increase of loop area.In embodiments of the present invention, by the adjacent position at clock signal stitch or high speed signal stitch be provided with ground stitch, appropriate design signal circuit, reduced the signal circuit area, guaranteed impedance loop and impedance continuity that signal is lower.
Fig. 2 shows the connector pin leg structure schematic diagram of the product of the employing DIN connector that the embodiment of the invention provides, as we can see from the figure, 22 pairs of different power supply signals 21 of earth signal are isolated, particularly on the clock signal adjacent stitches in the isa bus signal, by selecting the signal return flow path of low-impedance ground stitch for use, in the middle of the ISA signal reasonably layout some earth signals, and near the high relatively signal area placement of speed, particularly for clock signal, earth signal of definition is adjacent separately, has reduced loop area greatly; And through experimental verification, the signal interconnection device that adopts the embodiment of the invention to provide all can reach radiation B level 4dB surplus (PEAK value), meets radiation standard, meets the demands.Compare with prior art shown in Figure 1, the signal interconnection device that the embodiment of the invention provides has solved that the signal circuit area is big, impedance loop causes greatly that signal is crosstalked mutually, the incomplete problem of signal.
In embodiments of the present invention, the clock signal zone is by the first ground stitch or the second ground stitch and high speed signal zone isolation, the high speed signal zone is by the second ground stitch or the 3rd ground stitch and low speed signal zone isolation, and the low speed signal zone is by the 3rd ground stitch or the first ground stitch and described clock signal zone isolation; The clock signal zone is for being provided with the zone of one or more clock signal stitch; The high speed signal zone is for being provided with the zone of a plurality of high speed signal stitch; The low speed signal zone is for being provided with the zone of a plurality of low speed signal stitch.
Continuous development along with technology, speed, the frequency of digital signal are more and more higher, and analog signal also is easy to be subjected to the interference of digital signal, the space of PCB is again more limited, if so not design as requested, it will be very big producing the probability of interference and the energy of interference, even have influence on the normal function of product sometimes.For example: a kind of peripheral element extension interface of compactness (Compact PeripheralComponent Interconnect, CPCI) product is not because reasonably distinguish signal of different nature, caused the function of this CPCI product to be subjected to tangible influence, its reason is: the senior connection of serial (SerialAdvanced Technology Attachment, SATA) signal pins and low-voltage differential (Low VoltageDifferential Signaling, LVDS) stitch of clock signal is adjacent, the result causes the SATA signal to be subjected to very large disturbance, and appearance can't enter the phenomenon of system; By improving, high speed signal SATA signal and low-voltage differential clock signal land used stitch are kept apart, solved above-mentioned problem of crosstalking.Therefore, in embodiments of the present invention, dissimilar signals is set, with high speed signal, low speed signal, clock signal, sensitive signal etc. separately, and adopts the ground stitch to isolate by subregion, solved between the unlike signal crosstalk mutually, problem such as coupling.
In embodiments of the present invention, the stitch of signal interconnection device generally select for use short, thin, density is appropriate, firm contacting structure; And the connectors that metal shell is arranged will guarantee that the metal shell of the connectors of the connectors of male and female is electrically connected; Reduced the physical impedance of connectors like this, reduced the space radiation of connectors generation and the coupling between the signal, reduced the mutability of signal impedance, thereby guaranteed the reliability that the junction is electrically connected.For example, expansion embedded (Embedded Technology Extended, ETX) stitch of connector is just relatively shorter and thin, and resistance is 45m Ω under the direct current of 100mA, this is a reasonable connector, but it is exactly built on the sand that a shortcoming is arranged; CPCI connector for example again, its length just has the consideration signal integrity, and thickness also has concrete regulation, and has considered to shield with metal shell, and connectivity is also relatively firm, reliable; The employed connector stitch of some other product is very thick, long, and compare comparatively dense, and in the present invention, can select the proper signal interconnection device of some stitch by artificial, thus solved since the stitch of connectors long, excessive, cross and thick or overstockedly cause the impedance sudden change and unmatched problem.
The signal interconnection device that the embodiment of the invention provides is provided with the ground stitch by the adjacent position at the clock signal stitch, thereby effective transmission of control clock signal, make clock signal that a low-impedance loop be arranged, and reduced loop area, avoid signal to crosstalk mutually, realized the seamless link and the signal integrity of signal; Simultaneously dissimilar, of different nature signals are carried out rational subregion setting, thereby avoided to produce problems such as interference, signal compatibility difference between the unlike signal.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a signal interconnection device is characterized in that, described signal interconnection device comprises:
Stitch unit, first ground and one or more clock signal stitch that is used for transmit clock signal;
Stitch unit, described first ground comprises one or more first ground stitch, have one first ground stitch and the adjacent setting of clock signal stitch at least, control the transfer impedance of described clock signal stitch with the first ground stitch of the adjacent setting of described clock signal stitch, reduce the loop area of clock signal.
2. signal interconnection device as claimed in claim 1 is characterized in that, described signal interconnection device also comprises:
A plurality of high speed signal stitch and stitch unit, second ground that are used for transmit high-speed signals;
Stitch unit, described second ground comprises a plurality of second ground stitch, two high speed signal stitch and one second adjacent setting of ground stitch at the most, control the transfer impedance of described high speed signal stitch with the second ground stitch of the adjacent setting of described high speed signal stitch, reduce the loop area of high speed signal.
3. signal interconnection device as claimed in claim 2 is characterized in that, is provided with one second ground stitch between two different high speed signal stitch.
4. signal interconnection device as claimed in claim 2 is characterized in that, described signal interconnection device also comprises: a plurality of low speed signal stitch and stitch unit, the 3rd ground that are used to transmit low speed signal;
Stitch unit, described the 3rd ground comprises a plurality of the 3rd ground stitch, the adjacent setting of any one low speed signal stitch in one the 3rd ground stitch and N the low speed signal stitch, control the transfer impedance of described low speed signal stitch with the 3rd ground stitch of the adjacent setting of described low speed signal stitch, reduce the loop area of low speed signal; Described N is less than or equal to 20 natural number.
5. signal interconnection device as claimed in claim 4, it is characterized in that, the clock signal zone is by the first ground stitch or the second ground stitch and high speed signal zone isolation, the high speed signal zone is by the second ground stitch or the 3rd ground stitch and low speed signal zone isolation, and the low speed signal zone is by the 3rd ground stitch or the first ground stitch and described clock signal zone isolation;
Described clock signal zone is for being provided with the zone of one or more clock signal stitch; Described high speed signal zone is for being provided with the zone of a plurality of high speed signal stitch; Described low speed signal zone is for being provided with the zone of a plurality of low speed signal stitch.
6. signal interconnection device as claimed in claim 1 is characterized in that, described clock signal is the signal of telecommunication that fundamental frequency is not less than 5MHz.
7. signal interconnection device as claimed in claim 2 is characterized in that, described high speed signal is to be not less than the signal of telecommunication of 5ns or the signal of telecommunication that operating frequency is not less than 5MHz the rise time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101890550A CN101938068A (en) | 2009-12-17 | 2009-12-17 | Signal interconnector |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101890550A CN101938068A (en) | 2009-12-17 | 2009-12-17 | Signal interconnector |
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|---|---|
| CN101938068A true CN101938068A (en) | 2011-01-05 |
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| CN2009101890550A Pending CN101938068A (en) | 2009-12-17 | 2009-12-17 | Signal interconnector |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103717258A (en) * | 2011-08-05 | 2014-04-09 | 领先仿生公司 | Sound processor interconnects,headpiece assemblies, and methods of making the same |
-
2009
- 2009-12-17 CN CN2009101890550A patent/CN101938068A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103717258A (en) * | 2011-08-05 | 2014-04-09 | 领先仿生公司 | Sound processor interconnects,headpiece assemblies, and methods of making the same |
| CN103717258B (en) * | 2011-08-05 | 2016-07-06 | 领先仿生公司 | Sound Processor Unit connectors, headphone assembly and the method manufacturing them |
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Application publication date: 20110105 |