CN102110616B - Method for realizing thin film multilayer wiring on low temperature cofired ceramic (LTCC) substrate - Google Patents
Method for realizing thin film multilayer wiring on low temperature cofired ceramic (LTCC) substrate Download PDFInfo
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- CN102110616B CN102110616B CN 200910251523 CN200910251523A CN102110616B CN 102110616 B CN102110616 B CN 102110616B CN 200910251523 CN200910251523 CN 200910251523 CN 200910251523 A CN200910251523 A CN 200910251523A CN 102110616 B CN102110616 B CN 102110616B
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- 239000000758 substrate Substances 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 239000000919 ceramic Substances 0.000 title abstract 2
- 239000010410 layer Substances 0.000 claims abstract description 42
- 238000009713 electroplating Methods 0.000 claims abstract description 20
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 239000010949 copper Substances 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 229920001721 polyimide Polymers 0.000 claims description 11
- 239000004642 Polyimide Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000010344 co-firing Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 230000003746 surface roughness Effects 0.000 claims description 3
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 12
- 230000002349 favourable effect Effects 0.000 abstract description 2
- 239000012790 adhesive layer Substances 0.000 abstract 2
- 238000004140 cleaning Methods 0.000 abstract 1
- 238000005336 cracking Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 239000003292 glue Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000007788 liquid Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 4
- 239000008367 deionised water Substances 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical group [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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Abstract
The invention belongs to the field of integrated circuits, and in particular relates to a process method for realizing thin film multilayer wiring on a low temperature cofired ceramic (LTCC) substrate. The method comprises the following steps of: (1) processing a substrate interface; (2) cleaning the substrate; (3) sputtering an adhesive layer on the substrate; (4) photoetching a conduction band pattern; (5) electroplating a conduction band; (6) photoetching through hole column patterns; (7) electroplating through hole columns; (8) removing an electroplating mould; (9) photoetching a conduction band reverse pattern; (10) corroding the adhesive layer; (11) processing a dielectric film; and (12) repeating the steps of between (3) and (11) to obtain the LTCC substrate of which the through hole columns are interconnected and which is subjected to thin film multilayer wiring. The method has the advantages that: reliable interconnection of interfaces of the thin film multilayer wiring of the LTCC substrate and reliable interconnection of through holes between a plurality of layers of wirings are realized; the quality problem of cracking of a dielectric layer is solved; and the through hole columns can also be used for dissipating heat and is extremely favorable for a high-density wiring process, so that six-layer thin film wiring can be realized, the minimum line width spacing is 20mu m, and the minimum through hole is phi 20mu m.
Description
Technical field
The invention belongs to integrated circuit fields, particularly a kind of process that on ltcc substrate, realizes thin film multilayer wiring.
Background technology
At LTCC (low temperature multilayer co-firing pottery) substrate upper film multilayer wiring following advantage is arranged: (1) wiring density is high; (2) high frequency characteristics is good; (3) be embedded with the embedding type thin film multilayer wiring substrate of thin film passive components such as film resistor, electric capacity, inductance and IC chip in can making.Because thin film multilayer wiring has above-mentioned advantage, is widely used in technical fields such as aviation, communication, computers.
At present, domestic film wiring can realize the wiring of 4 layer films, minimum feature spacing 30 μ m, minimum vias φ 50 μ m.Conventional technology is etching through hole figure on polyimide film, evaporates conductor layer then, when forming the wiring conductor layer, has also accomplished via metalization.This simple for process, but following problem can appear: 1, big, the easy breaking phenomena that produces of through hole conduction band of through hole contact resistance.2, because of the ltcc substrate surface irregularity, and have blockage effect, cause the wiring of LTCC through hole and film can't realize effective interconnection, promptly ltcc substrate film Wiring technique compatibility is relatively poor.3, deielectric-coating is prone to be full of cracks, and it not only influences the adhesiveness of dielectric layer and substrate, metal level, and has a strong impact on the insulation resistance of dielectric layer, makes the metal conduction band short circuit of many wired circuits middle level and layer, loses the dielectric effect.
Summary of the invention
The objective of the invention is in order to solve the unreliable problem of interconnection at ltcc substrate thin film multilayer wiring interface in the prior art a kind of method that on ltcc substrate, realizes thin film multilayer wiring that provides.
The objective of the invention is to realize through following technical step:
(1), the processing of substrate interface: substrate is chosen as ltcc substrate, adopts mechanical polishing to improve its evenness, and the surface roughness of substrate is reached below the 0.1 μ m;
(2), substrate cleans: ltcc substrate adopts ultrasonic cleaning, the method that argon plasma is cleaned;
(3), sputter adhesion layer TiW/Au: for improving the tack of conductor layer on ltcc substrate, the compound adhesion layer TiW/Au of magnetron sputtering one deck on ltcc substrate;
(4), photoetching conduction band version: utilize photoresist and well-known photolithographic techniques, make the conduction band version that contains the conduction band figure, i.e. the electroplating mold of conduction band;
(5), electroplate conduction band: adopt known microplating technology, on the conduction band version, make the copper conduction band that links to each other with the TiW/Au adhesion layer;
(6), photoetching through hole post version: utilize photoresist and known photoetching technique, on conduction band version and conduction band, make the through hole post version that contains through hole post figure, i.e. the electroplating mold of through hole post;
(7), electroplating ventilating hole post: adopt the microplating technology, on through hole post electroplating mold, make the copper vias post that links to each other with conduction band.
(8), remove electroplating mold: adopt stripper to remove the electroplating mold of conduction band and through hole post, stay conduction band and through hole post.
(9), the anti-version of photoetching conduction band: utilize photoetching technique, on the ltcc substrate of removing electroplating mold, produce the anti-version of conduction band, the protective layer of formation conduction band and through hole post with positive glue;
(10), corrosion adhesion layer TiW/Au: on the ltcc substrate of making the anti-version of conduction band, adopt the technology of wet etching to remove unnecessary adhesion layer TiW/Au on the ltcc substrate;
(11), deielectric-coating processing:
A, on the ltcc substrate of removing adhesion layer TiW/Au coating polyimide;
B, heating cure, the LTCC substrate that is coated with polyimides adopts hot plate to solidify, and solidifies to be divided into two steps ladder solidification method:
The first step is preparatory imidization: (80 ℃ of temperature, 3 minutes time), (110 ℃ of temperature, 3 minutes time);
Second step was imidization: (140 ℃ of temperature, 5 minutes time), (170 ℃ of temperature, 5 minutes time), (200 ℃ of temperature, 5 minutes time);
Metal interconnected through hole post is exposed in c, mechanical polishing;
(12), repeat the step of (3)～(11), can make the ltcc substrate of the thin film multilayer wiring of metal throuth hole pole interconnection.
Advantage of the present invention is following: reliability of technology of the present invention is high, has realized the reliable interconnect at ltcc substrate thin film multilayer wiring interface and the through hole reliable interconnect between the multilayer wiring; Adopt the ladder solidification method to solve the quality problems of dielectric layer be full of cracks.The metal throuth hole post of producing in addition also can be used for heat dissipation channel, is very favorable for high-density wiring technology, can realize the wiring of 6 layer films, minimum feature spacing 20 μ m, minimum vias φ 20 μ m.
Description of drawings:
Fig. 1 is provided by the invention at LTCC upper film multilayer wiring process chart;
Fig. 2-a-Fig. 2-g is the schematic cross-section of each each step of film wiring on ltcc substrate.
Embodiment
Below in conjunction with accompanying drawing most preferred embodiment of the present invention is further described, Fig. 1 has provided the technological process of making at ltcc substrate upper film multilayer wiring.
Concrete technology is following:
(1) preparation of substrate interface
Substrate is chosen as 3 inches LTCC side's sheets of the multilayer co-firing that has polished.The thin-film technique first being processed must be carried out mechanical lapping, polishing to the surface of the LTCC multilager base plate behind the sintering, and the surface roughness of substrate is reached below the 0.1 μ m, to solve the irregular problem of LICC substrate.
(2) substrate cleans
The LTCC substrate was through alcohol ultrasonic cleaning 10 minutes, and the impurity on removal surface etc. adopt argon plasma to clean then and made the surface of purification and thin layer that affinity is preferably arranged in 30 minutes the influential pollutant of device performance, and the film adhesive strength reaches 20MPa.
(3) sputter adhesion layer TiW/Au
Be to improve the tack of conductor layer on ltcc substrate, on ltcc substrate with the compound adhesion layer TiW/Au of magnetron sputtering method sputter one deck.The TiW of the sputter one deck 0.05 μ m of elder generation, selecting power for use is 400W, the time is 20 seconds.Then, the Au of sputter 0.15 μ m again, power is 400W, the time is 60 seconds.
(4) make conduction band version (being the conduction band electroplating mold) with photoetching technique
Even glue: even glue on the LTCC substrate, select negative photoresist for use, the thick 5.0 μ m of glue;
Preceding baking: the LTCC substrate that will apply photoresist is placed on the hot plate, and temperature is set to 90 ℃, and the time is 5 minutes;
Exposure:, be placed on and carry out the exposure of figure alignment on the mask aligner with the LTCC substrate of preceding baking;
Develop: the LTCC substrate that made public, adopt supporting developing liquid developing, normal temperature developed 4 minutes, used supporting rinsing liquid rinsing 2 minutes again, and deionized water rinsing is clean and dry;
The back baking: the LTCC substrate after will developing is placed on the hot plate, and temperature is set to 140 ℃, and the time is 6 minutes;
Play glue: after the LTCC substrate that dried by the fire, played glue 3 minutes with plasma, guarantee that district to be plated does not have cull and counterdie.
The conduction band version that the process above-mentioned steps is produced is shown in Fig. 2-a, and wherein lower floor is the LTCC substrate, and sputter adheres to one deck TiW/Au above the LTCC substrate, the conduction band version of making for photoresist above the TiW/Au-and be the conduction band electroplating mold.
(5) electroplate conduction band
Adopt known microplating technology, on the conduction band version, make the high copper conduction band of 5 μ m that links to each other with the TiW/Au adhesion layer.In technology, adopt 1.5～2mA/cm
2Current density, the time is 60 minutes.Its state wherein exposes the TiW/Au place in the conduction band version shown in Fig. 2-b, be coated with the Cu wiring among the figure of copper conduction band-promptly.
(6) make through hole post version (being through hole post electroplating mold) with photoetching technique
On the basis of Fig. 2-b, carry out following steps.
Even glue: on the basis with Fig. 2-b, select negative photoresist for use, the even thick 5.0 μ m of glue.Comprise copper wiring (conduction band) sunk part is filled and led up.
Preceding baking: the LTCC substrate that will apply photoresist is put into hot plate, and temperature is set to 90 ℃, and the time is 5 minutes.
Exposure: the LTCC substrate of preceding baking is placed on and carries out the exposure of figure alignment on the mask aligner.
Develop: the LTCC substrate that made public, adopt supporting developing liquid developing, normal temperature developed 4 minutes, used supporting rinsing liquid rinsing 2 minutes again, and deionized water rinsing is clean and dry.
The back baking: the LTCC substrate after will developing is put on the hot plate and is dried, and temperature is set to 140 ℃, and the time is 6 minutes.
Play glue: plasma was played glue 3 minutes, guaranteed that district to be plated does not have cull and counterdie.
Form through hole post mold state shown in Fig. 2-c, above the copper wiring cylinder hole is arranged, but also do not electroplate Cu post (being the through hole post) this moment.
(7) electroplating ventilating hole post
Employing microplating technology can solve the reliable interconnect between thin film multilayer wiring effectively.
Shown in Fig. 2-c, adopt the microplating technology, in technology, adopt 1.5～2mA/cm
2Current density, the time is 10 minutes.Obtain the copper vias post of 5 μ m height, i.e. Cu through hole post post among Fig. 2-c, this moment, Cu through hole post post linked to each other with copper conduction band (Cu wiring).
(8) remove electroplating mold
Adopt stripper to remove the two-layer photoresist (being conduction band version and through hole post version) as electroplating mold, temperature is 80 ℃, and the time is 10 minutes.State behind the removal electroplating mold does not have anti-version mask layer this moment shown in Fig. 2-d.
(9) the anti-version mask layer of photoetching conduction band
Remove the LTCC substrate behind the electroplating mold, make the anti-version mask layer of conduction band, form mask, protect copper conduction band and copper vias post subsequent corrosion technology with positive glue.
Even glue: select positive photoresist for use.For guaranteeing the adhesiveness of photoresist and silicon chip, the LTCC substrate surface at Fig. 2-d state carries out tackified finish with HMDS earlier, rotates gluing then, the thick 1.5 μ m of glue.
Preceding baking: the LTCC substrate that will apply photoresist is put into hot plate, and temperature is set to 90 ℃, and the time is 3 minutes.
Exposure: the LTCC substrate of preceding baking is placed on and carries out the exposure of figure alignment on the mask aligner.
Develop: the LTCC substrate that made public adopts supporting developing liquid developing, and normal temperature developed 2 minutes, and deionized water rinsing is clean and dry.
The back baking: the LTCC substrate after will developing is placed on the hot plate, and temperature is set to 140 ℃, and the time is 3 minutes.
Form the anti-version mask layer of conduction band through above-mentioned steps, promptly exposed unnecessary adhesion layer TiW/Au and conduction band and guide pillar are protected by an anti-version mask layer.
(10) the unnecessary adhesion layer TiW/Au of corrosion
Erode the adhesion layer TiW/Au that exposes in the step (9), need to play glue 3 minutes before the corrosion adhesion layer TiW/Au, to remove cull.
The corrosive liquid of Au is iodine and 3: 1 mixed solution of KI, 58 ℃ of temperature, and the time is 20 seconds.The corrosive liquid of TiW is a hydrogen peroxide solution, 2 minutes time.
The state behind the adhesion layer TiW/Au of eroding is shown in Fig. 2-e.
(11) the coating polyimide deielectric-coating, be heating and curing and polish
Adopt spin-coating method, with liquid macroimolecule polymer poly acid imide, be coated on the LTCC substrate surface that erodes adhesion layer TiW/Au, the spin coating thickness of polyimides is 10 μ m, and the state of LTCC substrate that is coated with polyimides is shown in Fig. 2-f.
The LTCC substrate that is coated with polyimides adopts hot plate to solidify, and solidifies to be divided into two steps ladder heating:
The first step is preparatory imidization: (80 ℃ of temperature, 3 minutes time), (110 ℃ of temperature, 3 minutes time);
Second step was imidization: (140 ℃ of temperature, 5 minutes time), (170 ℃ of temperature, 5 minutes time), (200 ℃ of temperature, 5 minutes time); This species stage temperature-curable method can solve polyimides dielectric layer " be full of cracks " phenomenon effectively.
Polyimides deielectric-coating ladder need carry out mechanical polishing after solidifying, to expose metal interconnected post, shown in Fig. 2-g.
(12), repeat the described step in (3)～(11), can make the thin film multilayer wiring structure of metal column interconnection.
Claims (2)
1. method that on ltcc substrate, realizes thin film multilayer wiring is characterized in that may further comprise the steps:
(1), substrate interface is handled: substrate adopts low temperature multilayer co-firing pottery ltcc substrate, improves its evenness with mechanical polishing, and the surface roughness of substrate is reached below the 0.1 μ m;
(2), substrate cleans: ltcc substrate adopts ultrasonic cleaning, and argon plasma is cleaned;
(3), the compound adhesion layer TiW/Au of sputter on the ltcc substrate that cleaned;
(4), photoetching conduction band version: utilize photoetching technique, on the TiW/Au of ltcc substrate adhesion layer, make the thick conduction band version of 5 μ m;
(5), electroplate conduction band: adopt the microplating technology, on the conduction band version, make the high copper conduction band of 5 μ m that links to each other with the TiW/Au adhesion layer;
(6), photoetching through hole post version: utilize photoetching technique, on conduction band version and conduction band, make the thick through hole post version of 5 μ m;
(7), electroplating ventilating hole post: adopt the microplating technology, on through hole post version, make the high copper vias post of 5 μ m that links to each other with conduction band;
(8), remove conduction band version and through hole post version: adopt stripper to remove the conduction band version and the through hole post version of conduction band and through hole post, stay conduction band and through hole post;
(9), the anti-version of photoetching conduction band: utilize photoetching technique, on the ltcc substrate of removing electroplating mold, produce the anti-version of conduction band, form the protective layer of conduction band and through hole post;
(10), corrosion adhesion layer TiW/Au: on the ltcc substrate of making the anti-version of conduction band, adopt the technology of wet etching to remove adhesion layer TiW/Au on the ltcc substrate;
(11), deielectric-coating processing: a, on the ltcc substrate of removing adhesion layer TiW/Au coating polyimide, b, be heating and curing, metal interconnected through hole post is exposed in c, mechanical polishing;
(12) ltcc substrate of the thin film multilayer wiring of metal throuth hole pole interconnection can be made in repeating step (3)～(11).
2. a kind of method that on ltcc substrate, realizes thin film multilayer wiring according to claim 1 is characterized in that: the LTCC substrate that step (11) is coated with polyimides adopts hot plate to solidify, and solidifies to be divided into two steps ladder solidification method:
The first step is preparatory imidization: 80 ℃ of temperature, 3 minutes time, 110 ℃ of temperature, 3 minutes time;
Second step was imidization: 140 ℃ of temperature, 5 minutes time, 170 ℃ of temperature, 5 minutes time, 200 ℃ of temperature, 5 minutes time.
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| CN102856213B (en) * | 2012-08-24 | 2014-12-10 | 中国兵器工业集团第二一四研究所苏州研发中心 | LTCC substrate based thin film multilayer wiring manufacturing method |
| CN103874334A (en) * | 2014-03-25 | 2014-06-18 | 广东达进电子科技有限公司 | Manufacturing method of teflon high-frequency circuit board |
| CN104701251B (en) * | 2015-04-03 | 2017-08-04 | 中国电子科技集团公司第二十四研究所 | The preparation method of active silicon substrate |
| CN109661102B (en) * | 2015-11-03 | 2021-10-26 | 畅博电子(上海）有限公司 | Ceramic substrate circuit board and method for manufacturing the same |
| US10426043B2 (en) | 2016-08-19 | 2019-09-24 | Honeywell Federal Manufacturing & Technologies, Llc | Method of thin film adhesion pretreatment |
| CN107871704B (en) * | 2017-10-26 | 2020-05-05 | 苏州华博电子科技有限公司 | Method for manufacturing thin film circuit on warping co-fired ceramic substrate |
| CN109152221B (en) * | 2018-09-06 | 2020-08-11 | 中国电子科技集团公司第三十八研究所 | Forming method of shallow-layer loop-shaped cavity on low-temperature co-fired ceramic substrate |
| CN110459668B (en) * | 2019-08-16 | 2020-12-25 | 国网河南省电力公司邓州市供电公司 | Preparation method of high-power LED heat dissipation substrate |
| CN110891376A (en) * | 2019-11-21 | 2020-03-17 | 上海安费诺永亿通讯电子有限公司 | High-frequency electronic circuit and preparation method thereof |
| CN115611652A (en) * | 2022-11-10 | 2023-01-17 | 华东光电集成器件研究所 | Process method for improving welding performance of LTCC conductor |
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| US6537902B1 (en) * | 2000-01-24 | 2003-03-25 | Oki Electric Industry Co, Ltd. | Method of forming a via hole in a semiconductor device |
| EP1461816B1 (en) * | 2001-11-09 | 2007-01-24 | WiSpry, Inc. | Mems device having contact and standoff bumps and related methods |
| CN101252162A (en) * | 2008-03-27 | 2008-08-27 | 潮州三环（集团）股份有限公司 | High power LED ceramic packaging base |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6537902B1 (en) * | 2000-01-24 | 2003-03-25 | Oki Electric Industry Co, Ltd. | Method of forming a via hole in a semiconductor device |
| EP1461816B1 (en) * | 2001-11-09 | 2007-01-24 | WiSpry, Inc. | Mems device having contact and standoff bumps and related methods |
| CN101252162A (en) * | 2008-03-27 | 2008-08-27 | 潮州三环（集团）股份有限公司 | High power LED ceramic packaging base |
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