CN102110595A - Method for performing low-temperature metal bonding on InGaAs and GaAs - Google Patents
Method for performing low-temperature metal bonding on InGaAs and GaAs Download PDFInfo
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- CN102110595A CN102110595A CN2010105957073A CN201010595707A CN102110595A CN 102110595 A CN102110595 A CN 102110595A CN 2010105957073 A CN2010105957073 A CN 2010105957073A CN 201010595707 A CN201010595707 A CN 201010595707A CN 102110595 A CN102110595 A CN 102110595A
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Abstract
The invention discloses a method for performing low-temperature metal bonding on InGaAs and GaAs. The method comprises the following steps of: cleaning a single-side polished InGaAs epitaxial wafer to remove organic substances on the surface of the wafer; performing evaporation on the cleaned InGaAs epitaxial wafer to form a metal layer; performing photoresist etching on the InGaAs epitaxial wafer to obtain the InGaAs epitaxial wafer with a narrow metal strip; removing a photoresist on the surface of the InGaAs epitaxial wafer by plasma etching; cleaning a GaAs epitaxial wafer to remove organic substances on the surface of the wafer; attaching the cleaned GaAs epitaxial wafer to the InGaAs epitaxial wafer which is subjected to the plasma etching so as to obtain an attached wafer; oppositely arranging the attached wafer in a vacuum bonding machine for bonding and performing thermal treatment to remove vapor of a bonding interface; and thinning the bound wafer and corroding off the GaAs substrate of the bound wafer. By the method, the low-temperature metal bonding of the InGaAs and the GaAs is realized.
Description
Technical field
The present invention relates to semiconductor hetero-junction material growing technology field, be meant especially and a kind of InGaAs and GaAs carried out the method for low-temperature metal bonding, utilize that the vacuum bonding machine is realized between the low temperature III-V family material, the low-temperature metal bonding between III-V family material and the Si materials such as (Ge, GaN).
Background technology
Opto-electronic device more and more to integrated, miniaturization development, utilize bonding techniques that the heterojunction semiconductor material is bonded together, thereby the technology for preparing semiconductor device such as various lasers, detector more and more is subjected to extensive concern.This technology is that the wafer with two surfacing cleanings mutually combines by the chemical bond on surface under certain conditions, and is not subjected to the lattice of two kinds of wafer materials, the restriction in crystal orientation.Utilize bonding techniques combination new construction material that the great degree of freedom is arranged, can make full use of the superior light characteristic and the superior electrical characteristics of Si material of III-V family semi-conducting material, thereby obtain desirable semiconductor device material; In addition can also be integrated with the Si electronic circuit, thus extensive, multiple functional integrated opto-electronics device formed.
The many knots of utilization, multipotency band or multiple level structure are one of the most real methods of the solar cell of realization Ultra-High Efficiency.Yet the lattice constant of the monolayer material of the multijunction solar cell that is complementary with solar spectrum differs bigger, and epitaxial growth at present generally adopts means such as lattice gradual change to realize the growth of non-lattice matched materials, but has introduced complex defect to a certain degree; Perhaps adopt mechanical laminated way to realize that the monolithic between the different lattice constants material is integrated, but this method electricity connect very complexity.Bonding techniques has great superiority with respect to the above two: experimental technique is simple; Only local is in the interface for dislocation, and bonding can be broken through restrictions such as crystal orientation, lattice match, with the solar spectrum coupling, realizes high efficiency to greatest extent.In order to overcome the destruction of lattice mismatch extension to solar cell active layer crystal mass, people begin to explore the application of bonding techniques in the monolithic multijunction solar cell is integrated.California, USA Polytechnics takes the lead in the bonding semiconductor technology is applied in the efficient compound solar cell research of many knots in the world, and the center of research is GaInP at present
2The Direct Bonding of/GaAs and InGaAsP/InGaAs system.German Fraunhofer of while research institute is applied in Direct Bonding integrated technology and epitaxial loayer transfer techniques on GaAs and the Si buffering substrate, afterwards the epitaxial growth efficient multi-node solar battery.California, USA Anoex company and California Institute of Technology etc. are produced on the InGaAs solar cell on the InP/Si substrate, make that growth becomes possibility above 4 solar cells that save on the Si substrate.At present the best index of binode battery of bonding is GaAs/InGaAs binode battery (the K Tanabe of Direct Bonding of people such as the Tanabe report of California, USA Polytechnics, Anna Fontcuberta i Morral, Harry A.Atwater ane etc, Direct-bonded GaAs/InGaAs tandem solar cell, APPLIED PHYSICSLETTERS, 89,102106,2006.), its index is as follows: battery efficiency (1suns, AM1.5,25 ℃) be 9.3%, cell area is 0.337cm
2, fill factor, curve factor is 0.62.The domestic report that does not still have relevant bonding battery efficiency, the external report that does not still have metal bonding to realize multijunction solar cell at present.
For the Direct Bonding between the semi-conducting material, the semi-conducting material doping content at its bonded interface place and surface roughness all have extremely strict requirement, otherwise bonding quality is not high, cause battery efficiency to reduce even false bonding.And metal bonding is relatively simple, only need original battery material bonding face respectively the metal of evaporation suitable thickness just can be easy on the bonding, interface quality is fine and bonding area is big, success rate is high.Metal itself has good ductility, can effectively suppress the release of thermal stress.Simultaneously, thermal conductivity that metal is good and conductivity can well reduce the thermal resistance and the resistance of bond devices, help the optimization of device performance.Adopt the metal bonding that certain graphic structure is arranged of appropriate design, the potential barrier and the electricity that can influence bonded interface both sides semi-conducting material are led, reduce the absorption of metal pair light, avoided the complexity of growth tunnel junction, its superiority is greater than the connection of only adopting tunnel junction to each sub-series battery.Though the growth of the integral body of tunnel junctions has not been a difficult problem, the light absorption meeting of tunnel junctions has influence on the short-circuit current density of GaAs intermediate cell; And along with the rising of band gap width, the decline that fails to be convened for lack of a quorum of the tunnelling probability of tunnel junctions and peak electricity.The applied metal bonding directly couples together the adjacent sub-solar cell of different band gap, can not cause the tangible loss of voltage and too big current loss.
Be easy to realize low-temperature bonding for metal bonding, semiconductor technology such as high-temperature boiling, burn into attenuate etc. that the wafer behind the bonding can anti-residence has.At present the successful example of low-temperature bonding is a lot of in the world, utilize the plasma treatment wafer surface as people such as Tong Qinyi after, obtain the bonded energy that interface bond can be higher than body InP material at 200 degree; People such as the Mages of University of California carry out the high temperature bonding again through after the Low Temperature Heat Treatment earlier; The domestic low-temperature bonding technology that people such as Zhao Hong spring were once arranged.But the above two are all very high to laboratory apparatus and conditional request, though and the third party is not high to the laboratory apparatus conditional request, bonding is chronic, the requirement to operating personnel in the bonding process is very high.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of InGaAs and GaAs is carried out the method for low-temperature metal bonding, to realize the low-temperature metal bonding of InGaAs and GaAs.
(2) technical scheme
For achieving the above object, the invention provides and a kind of InGaAs and GaAs are carried out the method for low-temperature metal bonding, this method comprises:
Clean the InGaAs epitaxial wafer of single-sided polishing, remove the organic substance on surface;
Evaporated metal layer on the InGaAs epitaxial wafer that cleans up;
This InGaAs epitaxial wafer is carried out photoetching corrosion, obtain InGaAs epitaxial wafer with narrow bonding jumper;
The using plasma etching is removed the photoresist on InGaAs epitaxial wafer surface;
Clean the GaAs epitaxial wafer, remove the organic substance on surface;
The GaAs epitaxial wafer that cleans up is fitted the wafer after obtaining fitting with the InGaAs epitaxial wafer through plasma etching;
Wafer after this applying is opposite to carries out bonding in the vacuum bonding machine, and heat-treat, to drive away the aqueous vapor of bonded interface; And
Wafer behind the para-linkage carries out attenuate, and erodes the GaAs substrate of the wafer of bonding.
In the such scheme, the InGaAs epitaxial wafer of described cleaning single-sided polishing is removed the organic step on surface, comprising: the InGaAs epitaxial wafer of single-sided polishing is cleaned with organic solvent, remove the organic substance on surface, again with plasma water flushing at least 5 minutes.
In the such scheme, described cleaning GaAs epitaxial wafer is removed the organic step on surface, comprising: the GaAs epitaxial wafer is cleaned with organic solvent, remove the organic substance on surface, again with plasma water flushing at least 5 minutes.
In the such scheme, described InGaAs epitaxial wafer comprises:
One n type InP substrate 11;
One p type layer GaInP 12, this p type layer 12 are produced on the n type InP substrate 11;
One p type InGaAs layer 13, this p type InGaAs layer 13 is produced on the p type layer 12;
One n type InGaAs layer 14, this n type InGaAs layer 14 is produced on the p type InGaAs layer 13; And
One n type GaInP layer 15, this n type GaInP layer 15 is produced on the n type InGaAs layer 14.
In the such scheme, described GaAs epitaxial wafer comprises:
One n type GaAs substrate 21;
One n type GaAs resilient coating 22, this n type GaAs resilient coating 22 is produced on the n type GaAs substrate 21;
One p type GaInP corrosion barrier layer 23, this GaInP layer 23 is produced on the GaAs resilient coating 22;
One p
+Type GaAs layer 24, this p
+Type GaAs layer 24 is produced on the GaInP layer 23;
One p
+Type Al
0.9Ga
0.1As layer 25, this p
+Type Al
0.9Ga
0.1As layer 25 is produced on the p type GaAs layer 24;
One n type GaAs layer 26, this n type GaAs layer 26 is produced on p
+Type Al
0.9Ga
0.1On the As layer 25;
One p type GaAs layer 27, this p type GaAs layer 27 is produced on the n type GaAs layer 26; And
One p type Al
0.2Ga
0.8As layer 28, this p type Al
0.2Ga
0.8As layer 28 is produced on the p type GaAs layer 27.
In the such scheme, the wafer after described will the applying is opposite in the step of carrying out bonding in the vacuum bonding machine, and the vacuum degree of vacuum bonding adopts 10
-4To 10
-5Pa.
In the such scheme, described on the InGaAs epitaxial wafer that cleans up in the step of evaporated metal layer, the metal material that metal level adopts is Ti/Au, AuGeNi/Au, Al or Ni/Au, and the thickness of metal material is 10nm to 50nm.
In the such scheme, in the described step of heat treatment, be applied to that the pressure on the wafer is 1MPa to 5MPa behind the bonding.
In the such scheme, described step of heat treatment comprises following four temperature stages:
Pre-bonding is 1 hour in ℃ temperature range of stage 1:30～90;
Pre-bonding is 1 hour in ℃ temperature range of stage 2:120～200;
Stage 3:300～350 ℃ pre-bonding 0.5 hour;
Stage 4: slowly cooling, to room temperature, take out wafer.
In the such scheme, described heat treatment is more than 250 ℃ the time in temperature, heats up to require slowly average 0.2～0.5 ℃/minute; Temperature-fall period also requires slowly same, average 0.2～0.5 ℃/minute; And when temperature is lower than 250 ℃, take the nature temperature reduction way to lower the temperature.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, method of InGaAs and GaAs being carried out the low-temperature metal bonding provided by the invention, realized the low-temperature metal bonding of InGaAs and GaAs, and realized GaAs/InGaAs (or the Si of lattice constant mismatch by metal bonding, Ge) Double Junction Tandem Solar Cells, utilize the metal substitute tunnel junctions of bonded interface that the sub-battery of two-stage is coupled together, for realizing that efficient solar battery provides a kind of new method, make solar cell can break through materials limitations, by the multiple different materials of selecting to be complementary with solar spectrum, realize high-efficiency battery thereby connect together, for realizing that by bonding efficient multi-node solar battery lays the first stone.
2, provided by the invention InGaAs and GaAs are carried out the method for low-temperature metal bonding, repeatable the bonding time shortens greatly than higher, only need carry out in real earnest according to the operating process of setting, just the bonding wafer that can obtain to be of high quality.General substrate wafer thickness is about 350 μ m, and (as 400 μ m-460 μ m) also can use the present invention to obtain high-quality bonding wafer for thicker epitaxial wafer.
Description of drawings
Fig. 1 is the method flow diagram that InGaAs and GaAs is carried out the low-temperature metal bonding provided by the invention;
Fig. 2 a to Fig. 2 c is the process chart that InGaAs and GaAs is carried out the low-temperature metal bonding provided by the invention; (Si is after Ge) epitaxial wafer 20 cleans through preceding method, with p for GaAs epitaxial wafer 10 and InGaAs
+The surface bond of the surface of GaAs layer 24 and metal level 16 is heat-treated together, and attenuate GaAs substrate 21 removes GaAs substrate 21 with corrosive liquid then, and the GaAs film transfer has been arrived on the InP substrate 11;
Fig. 3 is the infrared perspective figure according to embodiment of the invention bonding wafer interface;
Fig. 4 a and Fig. 4 b are the SEM figure according to embodiment of the invention bonding wafer interface;
Fig. 5 a is the structural representation of InGaAs epitaxial wafer;
Fig. 5 b is the structural representation of GaAs epitaxial wafer.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention utilizes the vacuum bonding machine that InGaAs and GaAs are carried out the method for low-temperature metal bonding, and as shown in Figure 1, this method may further comprise the steps:
Step 1: clean the InGaAs epitaxial wafer of single-sided polishing, remove the organic substance on surface;
Step 2: evaporated metal layer on the InGaAs epitaxial wafer that cleans up;
Step 3: this InGaAs epitaxial wafer is carried out photoetching corrosion, obtain InGaAs epitaxial wafer with narrow bonding jumper;
Step 4: the using plasma etching is removed the photoresist on InGaAs epitaxial wafer surface;
Step 5: clean the GaAs epitaxial wafer, remove the organic substance on surface;
Step 6: the GaAs epitaxial wafer and the InGaAs epitaxial wafer through plasma etching that clean up are fitted the wafer after obtaining fitting;
Step 7: the wafer after will fitting is opposite to and carries out bonding in the vacuum bonding machine, and heat-treats, to drive away the aqueous vapor of bonded interface; And
Step 8: the wafer behind the para-linkage carries out attenuate, and erodes the GaAs substrate of the wafer of bonding.
Based on shown in Figure 1 InGaAs and GaAs are carried out the method flow diagram of low-temperature metal bonding, Fig. 2 a to Fig. 2 c shows the process chart that InGaAs and GaAs are carried out the low-temperature metal bonding provided by the invention, comprises the steps:
Step 1: the InGaAs epitaxial wafer 10 usefulness organic solvents of single-sided polishing are cleaned, remove the organic substance on surface, wash more than 5 minutes with plasma water again;
Shown in Fig. 5 b, described InGaAs epitaxial wafer 10 comprises:
One n type InP substrate 11;
One p type layer GaInP 12, this p type layer 12 are produced on the n type InP substrate 11;
One p type InGaAs layer 13, this p type InGaAs layer 13 is produced on the p type layer 12;
One n type InGaAs layer 14, this n type InGaAs layer 14 is produced on the p type InGaAs layer 13; And
One n type GaInP layer 15, this n type GaInP layer 15 is produced on the n type InGaAs layer 14.
Step 2: evaporated metal layer 16 on InGaAs epitaxial wafer 10; This metal level 16 is produced on the n type GaInP layer 15, and wherein the metal material that adopts of metal level 16 can be Ti/Au, AuGeNi/Au, Al, Ni/Au etc., about the thickness 10～50nm of metal material (the bonding jumper thickness of Fig. 4 adopt be 20nm).
Step 3: InGaAs epitaxial wafer 10 is carried out photoetching corrosion (or adopting lift-off technology to obtain bonding jumper), design the width of bonding jumper (as design according to requirement on devices for solar cell, require bonding jumper to occupy surface area and can not surpass 6%), obtain InGaAs epitaxial wafer with narrow bonding jumper;
Step 4: remove the photoresist on the InGaAs epitaxial wafer 10, can adopt the RIE technology that the surface is handled because metal is thin, the InGaAs epitaxial wafer 10 of process plasma surface treatment more helps the bonding success;
Step 5: GaAs epitaxial wafer 20 usefulness organic solvents are cleaned, remove the organic substance on surface, wash more than 5 minutes with plasma water again.
Shown in Fig. 5 a, described GaAs epitaxial wafer 20 comprises:
One n type GaAs substrate 21;
One n type GaAs buffering (buffer) layer 22, this n type GaAs resilient coating 22 is produced on the n type GaAs substrate 21;
One p type GaInP corrosion barrier layer 23, this GaInP layer 23 is produced on the GaAs resilient coating 22;
One p
+Type GaAs layer 24, this p
+Type GaAs layer 24 is produced on the GaInP layer 23;
One p
+Type Al
0.9Ga
0.1As layer 25, this p
+Type Al
0.9Ga
0.1As layer 25 is produced on the p type GaAs layer 24;
One n type GaAs layer 26, this n type GaAs layer 26 is produced on p
+Type Al
0.9Ga
0.1On the As layer 25;
One p type GaAs layer 27, this p type GaAs layer 27 is produced on the n type GaAs layer 26;
One p type Al
0.2Ga
0.8As layer 28, this p type Al
0.2Ga
0.8As layer 28 is produced on the p type GaAs layer 27.
The cleaning process of GaAs epitaxial wafer:
1. use the surface of acetone cotton balls wiping GaAs epitaxial wafer 20, examine under a microscope no tangible dirty particle, such epitaxial wafer just can be used for bonding;
2. with ethanol, acetone, trichloroethylene in order back and forth high temperature ultrasonic boil and wash GaAs epitaxial wafer 20 each 3 times, after having cleaned with ethanol at last, washed repeatedly 5 minutes with deionized water, purpose is to remove the surface organic matter pollution;
Step 6: GaAs epitaxial wafer 20 that cleans up and the InGaAs epitaxial wafer 10 that passes through plasma treatment are fitted, and the wafer after the applying is opposite to bonding in the vacuum bonding machine, heat-treats, to drive away the aqueous vapor of bonded interface.
Heat treatment described here comprises:
(1) anchor clamps that will be placed with two epitaxial wafers that post place in the vacuum bonding machine, apply certain pressure by force application apparatus to wafer after the sealing, generally between 1 to 5MPa.Begin then to vacuumize, arrive certain vacuum degree (3 * 10
-3Pa is following) after can begin to set low temperature 30 to 90 degree, pre-bonding is about 1 hour in 30 to 90 ℃ of temperature ranges.Vacuum degree remains on 10 in insulating process
-4To 10
-5Pa.
(2) wafer behind the pre-bonding carries out 120 to 200 degrees centigrade low-temperature bonding more than 1 hour, and pressure is the same.This process can be removed the steam between the interface, and this process bonding time, long more bonded energy was big more.
(3) wafer behind the pre-bonding carries out 300 to 350 degrees centigrade low-temperature bonding about 0.5 hour again.Further remove interface steam, increase the interface bond energy.The one-tenth key mode of bonded interface is followed the rising of temperature and the effusion of gas, and the Van der Waals during from pre-bonding is in conjunction with being transformed into the atomic bond combination.
(4) begin slow cooling then, after room temperature, can take out wafer, carry out next step processing.Notice that 250 ℃ of processes that heat up later on and lower the temperature will compare slowly, average about 0.2-0.5 ℃/minute, prevent that thermal stress from can not get in time discharging and causing the bonding failure.
Step 7: the wafer behind the para-linkage carries out attenuate.After the wafer taking-up with above-mentioned bonding, mechanical reduction GaAs substrate is thinned to about 100 μ m.
Step 8: erode the GaAs substrate 21 of bonding wafer, finish the making of low-temperature metal bonding.
The corrosion step of GaAs substrate 21 is as follows:
(1) with photoresist or wax protection wafer side, prevent the corrosive liquid lateral erosion.
(2) to place volume ratio be H for wafer that bonding is good
3PO
4: H
2O
2: H
2O=1: carry out the corrosion of GaAs substrate 21 in 1: 3 the solution; Be HCL: H with volume ratio then
2O=2: 1 solution corrosion removes GaInP barrier layer 23, and the acquisition superficial layer is P
+The contact electrode layer 24 of GaAs, surperficial so several microns GaAs film has approximately just been transferred on the InP substrate, has obtained the GaAs/InGaAs Double Junction Tandem Solar Cells wafer of bonding.
(3) utilize organic solvent to remove glue or wax, if the poor quality of bonding here, bonding can appear separating in wafer in the process of heat treatment paraffin removal.The wafer bonding that the method for our this low-temperature bonding obtains can be than higher, and wafer is complete in wax removing process, the bonding phenomenon do not occur separating.
From result of experiment, the effect of this low-temperature metal bonding is fine.The infrared perspective figure of bonding wafer shown in Figure 3 is very bright, does not have Newton's ring, shows that the part that do not have between the interface on the bonding seldom.The InGaAs/GaAs wafer of making has been carried out the SEM figure test of bonded interface, and the interface is very smooth, and there is layer of metal striped (white portion among Fig. 4 b) centre; In the place that does not have metal the space is arranged, the space has not had again in the place away from bonding jumper, illustrates that the quality of bonding is fine.
Utilize corrosive liquid such as phosphoric acid with bonding wafer GaAs substrate etching intact after, the GaAs film has been transferred on the InP substrate, the I-V characteristic of test bonding wafer illustrates that the InGaAs/GaAs wafer interface of bonding has realized ohmic contact, and the electrical characteristics of bonded interface are good.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. method that InGaAs and GaAs are carried out the low-temperature metal bonding is characterized in that this method comprises:
Clean the InGaAs epitaxial wafer of single-sided polishing, remove the organic substance on surface;
Evaporated metal layer on the InGaAs epitaxial wafer that cleans up;
This InGaAs epitaxial wafer is carried out photoetching corrosion, obtain InGaAs epitaxial wafer with narrow bonding jumper;
The using plasma etching is removed the photoresist on InGaAs epitaxial wafer surface;
Clean the GaAs epitaxial wafer, remove the organic substance on surface;
The GaAs epitaxial wafer that cleans up is fitted the wafer after obtaining fitting with the InGaAs epitaxial wafer through plasma etching;
Wafer after this applying is opposite to carries out bonding in the vacuum bonding machine, and heat-treat, to drive away the aqueous vapor of bonded interface; And
Wafer behind the para-linkage carries out attenuate, and erodes the GaAs substrate of the wafer of bonding.
2. the method that InGaAs and GaAs are carried out the low-temperature metal bonding according to claim 1 is characterized in that the InGaAs epitaxial wafer of described cleaning single-sided polishing is removed the organic step on surface, comprising:
The InGaAs epitaxial wafer of single-sided polishing is cleaned with organic solvent, remove the organic substance on surface, again with plasma water flushing at least 5 minutes.
3. the method that InGaAs and GaAs are carried out the low-temperature metal bonding according to claim 1 is characterized in that described cleaning GaAs epitaxial wafer is removed the organic step on surface, comprising:
The GaAs epitaxial wafer is cleaned with organic solvent, remove the organic substance on surface, again with plasma water flushing at least 5 minutes.
4. the method that InGaAs and GaAs are carried out the low-temperature metal bonding according to claim 1 is characterized in that described InGaAs epitaxial wafer comprises:
One n type InP substrate (11);
One p type layer GaInP (12), this p type layer (12) is produced on the n type InP substrate (11);
One p type InGaAs layer (13), this p type InGaAs layer (13) are produced on the p type layer (12);
One n type InGaAs layer (14), this n type InGaAs layer (14) are produced on the p type InGaAs layer (13); And
One n type GaInP layer (15), this n type GaInP layer (15) is produced on the n type InGaAs layer (14).
5. the method that InGaAs and GaAs are carried out the low-temperature metal bonding according to claim 1 is characterized in that described GaAs epitaxial wafer comprises:
One n type GaAs substrate (21);
One n type GaAs resilient coating (22), this n type GaAs resilient coating (22) are produced on the n type GaAs substrate (21);
One p type GaInP corrosion barrier layer (23), this GaInP layer (23) is produced on the GaAs resilient coating (22);
One p
+Type GaAs layer (24), this p
+Type GaAs layer (24) is produced on the GaInP layer (23);
One p
+Type Al
0.9Ga
0.1As layer (25), this p
+Type Al
0.9Ga
0.1As layer (25) is produced on the p type GaAs layer (24);
One n type GaAs layer (26), this n type GaAs layer (26) is produced on p
+Type Al
0.9Ga
0.1On the As layer (25);
One p type GaAs layer (27), this p type GaAs layer (27) are produced on the n type GaAs layer (26); And
One p type Al
0.2Ga
0.8As layer (28), this p type Al
0.2Ga
0.8As layer (28) is produced on the p type GaAs layer (27).
6. according to claim 1 InGaAs and GaAs are carried out the method for low-temperature metal bonding, it is characterized in that the wafer after described will the applying is opposite in the step of carrying out bonding in the vacuum bonding machine, the vacuum degree of vacuum bonding adopts 10
-4To 10
-5Pa.
7. method of InGaAs and GaAs being carried out the low-temperature metal bonding according to claim 1, it is characterized in that, described on the InGaAs epitaxial wafer that cleans up in the step of evaporated metal layer, the metal material that metal level adopts is Ti/Au, AuGeNi/Au, Al or Ni/Au, and the thickness of metal material is 10nm to 50nm.
8. according to claim 1 InGaAs and GaAs are carried out the method for low-temperature metal bonding, it is characterized in that, in the described step of heat treatment, be applied to that the pressure on the wafer is 1MPa to 5MPa behind the bonding.
9. the method that InGaAs and GaAs are carried out the low-temperature metal bonding according to claim 1 is characterized in that described step of heat treatment comprises following four temperature stages:
Pre-bonding is 1 hour in ℃ temperature range of stage 1:30～90;
Pre-bonding is 1 hour in ℃ temperature range of stage 2:120～200;
Stage 3:300～350 ℃ pre-bonding 0.5 hour;
Stage 4: slowly cooling, to room temperature, take out wafer.
10. according to claim 1 InGaAs and GaAs are carried out the method for low-temperature metal bonding, it is characterized in that, described heat treatment is more than 250 ℃ the time in temperature, and heating up requires slowly average 0.2～0.5 ℃/minute; Temperature-fall period also requires slowly same, average 0.2～0.5 ℃/minute; And when temperature is lower than 250 ℃, take the nature temperature reduction way to lower the temperature.
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| CN107359135A (en) * | 2016-05-09 | 2017-11-17 | 中国科学院半导体研究所 | Transfer bonding structure of integrated device and preparation method thereof in Terahertz antenna sheet |
| US10418501B2 (en) | 2015-10-02 | 2019-09-17 | X-Celeprint Limited | Wafer-integrated, ultra-low profile concentrated photovoltaics (CPV) for space applications |
| US10416425B2 (en) | 2009-02-09 | 2019-09-17 | X-Celeprint Limited | Concentrator-type photovoltaic (CPV) modules, receiver and sub-receivers and methods of forming same |
| CN111073649A (en) * | 2019-12-30 | 2020-04-28 | 中国科学院半导体研究所 | Etching solution for secondary epitaxial pretreatment, preparation method thereof and pretreatment method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US10416425B2 (en) | 2009-02-09 | 2019-09-17 | X-Celeprint Limited | Concentrator-type photovoltaic (CPV) modules, receiver and sub-receivers and methods of forming same |
| CN102184980A (en) * | 2011-04-02 | 2011-09-14 | 中国科学院苏州纳米技术与纳米仿生研究所 | Wafer-bonding-based triple-junction solar cell and preparation method thereof |
| CN102270693A (en) * | 2011-07-15 | 2011-12-07 | 中国科学院苏州纳米技术与纳米仿生研究所 | Multijunction laminated solar cell and manufacturing method thereof |
| CN105229795A (en) * | 2013-03-14 | 2016-01-06 | 森普留斯公司 | For the high-efficiency solar receiver comprising stacking solar cell of condensation photovoltaic |
| CN104916715A (en) * | 2015-05-25 | 2015-09-16 | 中国电子科技集团公司第十八研究所 | Preparation method of quantum-dot five-junction solar cell |
| US10418501B2 (en) | 2015-10-02 | 2019-09-17 | X-Celeprint Limited | Wafer-integrated, ultra-low profile concentrated photovoltaics (CPV) for space applications |
| CN107359135A (en) * | 2016-05-09 | 2017-11-17 | 中国科学院半导体研究所 | Transfer bonding structure of integrated device and preparation method thereof in Terahertz antenna sheet |
| CN111073649A (en) * | 2019-12-30 | 2020-04-28 | 中国科学院半导体研究所 | Etching solution for secondary epitaxial pretreatment, preparation method thereof and pretreatment method |
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