CN102104038B - Semiconductor device provided with high-voltage and low-voltage components on identical substrate - Google Patents
Semiconductor device provided with high-voltage and low-voltage components on identical substrate Download PDFInfo
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- CN102104038B CN102104038B CN201010602387XA CN201010602387A CN102104038B CN 102104038 B CN102104038 B CN 102104038B CN 201010602387X A CN201010602387X A CN 201010602387XA CN 201010602387 A CN201010602387 A CN 201010602387A CN 102104038 B CN102104038 B CN 102104038B
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Abstract
The invention discloses a semiconductor device provided with high-voltage and low-voltage components on an identical substrate, which comprises the substrate, a low-voltage component area and a high-voltage component area which are formed on the substrate. The high-voltage component area comprises an n+ drain region formed on the surface of the substrate, an n-type epitaxial layer encircling the n+ drain region and an n-type epitaxial expansion and diffusion layer formed below the n-type epitaxial layer.
Description
Technical field
The present invention relates to semiconductor device, more specifically, the application relates to a kind of semiconductor device that has high voltage device and low voltage component on same substrate.
Background technology
High-voltage semi-conductor generally uses high voltage device and low voltage component on same substrate.At some, only have in the application of or a few high-pressure installation, high-pressure installation be typically used as and be called as " opener or open Lou " configuration.This high pressure node that is meaning in circuit only connects the collector electrode of bipolar transistor or the drain electrode of MOS transistor.Low-pressure section in circuit can be by the outer low pressure Power supply or by high-pressure installation power supply on a sheet.
Said structure allow to utilize simple and therefore relatively not expensive technique manufacture above-mentioned semiconductor circuit.
Any high pressure and low voltage component be manufactured in to the semiconductor technology on same substrate, be successful manufacturing installation, the designer faces three key factors that need balance.They are: (1) process complexity, the circuit function that (2) are best, and the area of (3) semiconductor chip.
Referring to Fig. 1.Traditionally, between low voltage component 10 or between low voltage component 10 and high voltage device 20 the little epitaxy layer thickness that must or be conducive to insulate, and allow the operation with high pressure of some devices between on same substrate, carrying out, the part hybrid circuit utilizes the RESURF principle to find the balance of the two.
Fig. 1 left side shows by p-type insulate and disperses the low-voltage npn electric crystal of isolation.Because the ISO diffusion is not very dark, so epi must be very thin, the area that this also means the boundary diffusion that (mean) is large and is lost at large insulation layer.
This method also has some serious defects, because the substrate under drain electrode need to have high resistance, as shown in Figure 1.Low voltage component 10 and high voltage device 20 are isolated by insulation layer.Low voltage component 10 can be npn type bipolar transistor, and high voltage device 20 can be the dmos pipe.Low voltage component 10 has collector electrode 11, base stage 12 and the emitter 13 that is formed at N-shaped epitaxial loayer top, and N-shaped epitaxial loayer below has N-shaped buried layer nBL.High voltage device 20 has drain electrode 21, grid 22 and the source electrode 23 that is formed at N-shaped epitaxial loayer top, and source electrode 23 is formed in p-type body 24.In this example, drain electrode 21 is n+ traps of doping, and it stops the electric field that is produced by this substrate.Like this, the whole electric field under drain electrode 21 is contained in semiconductor.Away from the drain electrode 21(drift region) zone, electric field can exhaust N-shaped epitaxial loayer 30 fully, so electric field can be present in semi-conductive top.The N-shaped epitaxial loayer 30(cut-off region (pinched off) that this is completely depleted) transverse electric field that limits, drain electrode 21 that can supportive device and grid 22 with drain 21 and source electrode 23 between high pressure.The drift region that this N-shaped epitaxial loayer 30 exhausts depends on following substrate, before the grid that the exhausting fully of N-shaped epitaxial loayer 30 must occur in device or near the transverse electric field source electrode arrive boundary value, to avoid voltage breakdown.Equally, the resistivity of substrate also is restricted to definite value to promote exhausting of N-shaped epitaxial loayer.
Under drain electrode, the situation difference, substrate herein need to have high resistivity to allow the wide loss district that realizes in order to reduce electric field.Because the zone under drain electrode has the feature of one-sided step junction, therefore the problem of thin epitaxial loayer can be more outstanding.It is well known in the art that the electric field at identical peak value, with respect to bilateral step junction, the bilateral step junction that for example can utilize thick N-shaped epitaxial loayer to form, one-sided step junction only can support the voltage of half.According to above-mentioned, can know clearly, under drain electrode, needing under the resistance substrate that has rate and drift region needs the resistance substrate that has rate to conflict mutually.The method of this resistance substrate rate conflict of traditional solution is to utilize thick N-shaped epitaxial loayer to provide for the depletion region under the n+ drain electrode exceptional space that needs.
Summary of the invention
The objective of the invention is, for above-mentioned the deficiencies in the prior art, provides a kind of method, with the resistance substrate rate under the solution drain electrode and the conflicting problem of resistance substrate rate under drift region.For the suitable loss of the N-shaped epitaxial loayer under drift region, the resistance substrate rate can be optimised, and this optimization allows to utilize suitable thin N-shaped epitaxial loayer so that the simple insulation between low voltage component (simple isolation) to be provided.
For meeting above requirement, the invention provides technical scheme is: the semiconductor device that has high voltage device and low voltage component on a kind of same substrate, comprise substrate and be formed at the low voltage component zone and high voltage device zone on substrate, described high voltage device district inclusion is formed at the n+ drain region of substrate surface, surround the N-shaped epitaxial loayer of this n+ drain region, and the dark N-shaped diffusion layer that is formed at this N-shaped epitaxial loayer below, N-shaped extension by name expands prolongs diffusion layer (epi extension diffusion).
Described N-shaped extension expands and prolongs the volume of diffusion layer greater than described n+ drain region.
The thickness of described N-shaped epitaxial loayer is less than 5 um.
The expansion concentration of described n+ drain region is greater than the doping content of N-shaped epitaxial loayer, and the doping content of N-shaped epitaxial loayer is greater than the doping content of N-shaped extension expansion diffusion layer, and the doping content of N-shaped extension expansion diffusion layer is greater than the doping content of p-type substrate.
The doping content of described N-shaped epitaxial loayer is 2E15 atoms/cm
3, and the doping content of p-type substrate layer is 2E14 atoms/cm
3.
The electric field strength in described high voltage device zone is extended from N-shaped epitaxial loayer top and is increased gradually to N-shaped extension expansion diffusion layer bottom with the degree of depth, then from p-type substrate layer top, to p-type substrate layer bottom, reduces gradually.
The present invention provides a kind of technical scheme in addition: the semiconductor device that has high voltage device and low voltage component on a kind of same substrate, comprise substrate and be formed at the low voltage component zone and high voltage device zone on substrate, described high voltage device district inclusion is formed at the n+ drain region of substrate surface, surround the N-shaped epitaxial loayer of this n+ drain region, and the N-shaped extension expansion diffusion layer that is formed at this N-shaped epitaxial loayer below; Described low voltage component district inclusion is formed at the dark pBL zone of below, base region.
The thickness of described N-shaped epitaxial loayer is less than 5 um.
The present invention also provides a kind of technical scheme: the semiconductor device that has high voltage device and low voltage component on a kind of same substrate, comprise substrate and be formed at the low voltage component zone and high voltage device zone on substrate, described high voltage device district inclusion is formed at the n+ drain region of substrate surface, surround the N-shaped epitaxial loayer of this n+ drain region, and the N-shaped extension expansion diffusion layer that is formed at this N-shaped epitaxial loayer below; And between described n+ drain region and N-shaped epitaxial loayer, also have the N-shaped doped region around the n+ drain region, the doping content of this N-shaped doped region is higher than the doping content of described N-shaped epitaxial loayer.
The doping content of described N-shaped doped region is at 1E16 atoms/cm
3～1E18 atoms/cm
3Between, the doping content of described N-shaped epitaxial loayer is at 1.5E15 atoms/cm
3～5E15 atoms/cm
3Between.
The thickness of described N-shaped epitaxial loayer is less than 5 um.
The present invention provides again a kind of technical scheme: the semiconductor device that has high voltage device and low voltage component on a kind of same substrate, comprise substrate and be formed at the low voltage component zone and high voltage device zone on substrate, described high voltage device district inclusion is formed at the n+ drain region of substrate surface, surround the N-shaped epitaxial loayer of this n+ drain region, and the N-shaped extension expansion diffusion layer that is formed at this N-shaped epitaxial loayer below; Described low voltage component district inclusion is formed at the high-dopant concentration layer of below, base region.
The doping content of described high-dopant concentration layer is at 5E17 atoms/cm
3～5E18 atoms/cm
3Between.
The thickness of described N-shaped epitaxial loayer is less than 5 um.
Compared to prior art, the present invention is by arranging extension expansion diffusion layer, can make substrate to the forming for both sides have enough the graded junction be used to the space that exhausts of n+ drain electrode, and those spaces are for holding the high-tension wide depletion region of needs support.This epitaxial loayer expansion diffusion can be converted to the high voltage processing procedure by multiple low-voltage processing procedure, and does not need to carry out completely the processing procedure that starts anew to research and develop.
The accompanying drawing explanation
Fig. 1 shows the traditional solution when high-pressure installation and low-voltage device are formed on same substrate.
Fig. 2 shows how one embodiment of the present of invention and epi diffusion can increase the N-shaped thickness with more multiplex space in diffusion layer.
Fig. 3 is the sectional drawing of A direction, shows doping profile and its enhancing N-shaped district.
Fig. 4 is the chart of the electric field vertical with crystal column surface under n+ drain electrode.
Fig. 5 is the schematic diagram of the drain region of high-tension electricity crystal, has shown depletion layer.
Fig. 6 display application the second embodiment of the present invention of dark pBL.
How Fig. 7 demonstration is by utilizing suitable N-shaped layer around the n+ drain electrode, to extend the SOA of high-tension electricity crystal.
Fig. 8 shows the another embodiment that SOA is further improved.
Embodiment
For making purpose of the present invention, it is clearer that technical scheme and advantage are expressed, and the present invention will be further described in detail below in conjunction with drawings and the specific embodiments.
Fig. 2 to Fig. 5 shows according to the first embodiment of the present invention.Fig. 6 shows according to the second embodiment of the present invention.Fig. 7 shows according to the third embodiment of the present invention.Fig. 8 shows according to the fourth embodiment of the present invention.
With reference to Fig. 2.The transistor of Fig. 2 is to be applied to build the transistorized embodiment of high pressure dmos with " opening Lou " by the extension expansion concept.As shown in the figure, low voltage component 10 and high pressure unit 20 isolate by insulation layer.Low voltage component 10 can be npn type bipolar transistor.Low voltage component 10 has collector electrode 11, base stage 12 and the emitter 13 that is formed at N-shaped epitaxial loayer top, and N-shaped epitaxial loayer below has N-shaped buried layer nBL.High voltage device 20 has drain electrode 21, grid 22 and the source electrode 23 that is formed at N-shaped epitaxial loayer top, and source electrode 23 is formed in p-type body 24.With reference to Fig. 3 to Fig. 5.Fig. 3 is the sectional drawing along A-A direction in Fig. 2, and it shows doping profile and its enhancing N-shaped district.As shown in the figure, the doping content of n+ drain region is the highest, be secondly the N-shaped epitaxial loayer, be N-shaped extension expansion diffusion layer again, the doping content minimum be the p-type substrate.Wherein, the doping content of N-shaped epitaxial loayer is 2E15 atoms/cm
3, and the doping content of p-type substrate is 2E14 atoms/cm
3.Fig. 4 is the chart of the electric field vertical with crystal column surface under n+ drain electrode, and in figure, the intensity of electric field E1 is Δ
log
eq
, and the intensity of electric field E2 is-Δ
log
eq
.Fig. 5 is the schematic diagram of the drain region of high-tension electricity crystal, and it has further shown depletion layer, and depletion layer 50 extends between 51He border, border 52.
Continuation is with reference to Fig. 2 to Fig. 5.In this embodiment, drain electrode 21 is n+ traps of doping, and it stops the electric field that is produced by substrate.The n+ drain region 21 at device middle part must be wide to being large enough to hold weld pad.Extension expansion diffusion layer 25 horizontal expansions under drain region 21 exceed 21De border, n+ drain region.This extension expansion diffusion layer 25 of horizontal expansion can reduce the electric field at 21 edges, n+ drain region, and also can provide more N-shaped cross section be used to conducting drain current, to reduce transistorized conducting resistance (on-state resistance).The semiconductor that reduces to allow to have with less device manufacture certain conducting resistance of conducting resistance.
The N-shaped layer of additional thickness be set under drain region and its horizontal expansion is also had to the another one advantage, keeping the non-depletion region (un-depleted region) adjacent with the n+ drain region, this non-depletion region has improved the safety operation area of device.This kind situation as shown in Figure 6.Charge carrier is getted over the electric field that ends at drain region that drift region produces them.When cross section is extended and the n+ drain region have by the resilient coating of slightly slight doping around the time, with conventional apparatus, compare, the appearance ionization by collision relevant to high-intensity magnetic field and high current density usually in conventional apparatus, can only occur under higher voltage.This produces more superior safety operation area.
With reference to Fig. 6, this figure shows according to the second embodiment of the present invention.This embodiment is further forming dark pBL district 63 below the p-type body 24 at the high voltage device edge on the basis of the first embodiment shown in Figure 2.The dark pBL district 63 of device edge is by providing large P type surface (p-type surface) to help to reduce the electric field of device edge at edge.Electric field by the charge generation in epitaxial loayer is not only stopped by the p-type adulterate body now, and has the pBL doped layer to stop.Depletion region 60 becomes between 61He border, border 62 and extends.Therefore, from the electric field of epitaxial loayer emission, by described two doped layers, shared, with all electric fields, by the situation that the p-type adulterate body stops, compare its peak reduction.This technical scheme allows drift region to shorten, thereby has reduced the resistivity of drift region.For the semiconductor of certain conducting resistance, with the drift region of low-resistivity, make the semi-conductive volume of manufacturing less.
With reference to Fig. 7, it shows another preferred embodiment of the present invention, and this embodiment also shows how on the basis of the first embodiment shown in Figure 2, further to improve the SOA of high voltage transistor.As shown in the figure, this embodiment also has the N-shaped doped region 71 around n+ drain region 21 between n+ drain region 21 and N-shaped epitaxial loayer, and the doping content of this N-shaped doped region 71 is higher than the doping content of N-shaped epitaxial loayer.For example, the doping content of N-shaped doped region 71 is at 1E16 atoms/cm
3～1E18 atoms/cm
3Between, the doping content of N-shaped epitaxial loayer is at 1.5E15 atoms/cm
3～5E15 atoms/cm
3Between.Should add the electric field that N-shaped doped region dwell section is produced by the charge carrier in drift region, the quantity that reduces to greatly reduce the charge carrier that is produced by ionization by collision of drain region electric field, thereby the voltage of expansion SOA, even higher current density.
Recognize that reliability and durability when SOA uses for a long time to high tension apparatus are extremely important, Fig. 8 is presented on the basis of embodiment shown in Figure 2, to another further improvement of SOA.As shown in the figure, embodiment shown in Figure 8 is at the new p-type degree of depth doped layer of additional one deck of p-type body 24.Although the charge carrier of have its source in ionization by collision and its generation of problem, if but could create suitable approach for the charge carrier of enough forward bias source electrodes/matrix knot (source/body junction), the parasitic npn that is produced by drain electrode, p-type body and source electrode could become passive.The shown in Figure 8 upper suitable p-type layer that appends to initial p-type body (p-body) can reduce the resistance of p-type body as shunting (shunt), thereby hole current (carry the hole current) can be guided into towards the edge of drain electrode, and voltage can be promoted to, not be enough to open source electrode/matrix knot (source/body junction).Additional p-type layer can implant or utilize existing boron diffusion to produce by (suitable) boron of appropriateness.This embodiment utilizes isolation diffusion to reduce the series impedance of body, body (body) is connected with substrate, and without other mask plate.
Utilize technique scheme of the present invention, epitaxial loayer can be done thinlyyer.With regard to the manufacture of high-voltage semi-conductor, the thickness of the needed epitaxial loayer of employing technical solution of the present invention can be less than utilizing 70% of conventional art.For example, the thickness of said n type epitaxial loayer can be less than 5 um, this be about the conventional art requirement half or below.
Principle of the present invention and design philosophy are:
For the resistance substrate rate under the solution drain electrode and the conflicting problem of resistance substrate rate under drift region, the present invention utilizes suitable thin N-shaped epitaxial loayer so that the simple insulation between low voltage component (simple isolation) to be provided, this thin N-shaped epitaxial loayer is in order to hold the space of the lower electric field of drain electrode, to obtain by substrate being carried out to N-shaped diffusion (n-type diffusion into the substrate) from this thin N-shaped epitaxial loayer, with the thick N-shaped epitaxial loayer of emulation.By carrying out the N-shaped diffusion of the degree of depth, be referred to as extension extension layer diffusion (extension diffusion) (at US 6,236,100 also mention), n+ that this substrate is tied drain electrode becomes both sides and has enough be used to exhausting the graded junction in space, and this space is for holding the high-tension wide depletion region of needs support.This extension expansion diffusion layer can be converted to the high voltage processing procedure by multiple low-voltage processing procedure, and does not need to carry out completely the processing procedure that starts anew to research and develop.In this processing procedure, low voltage component remains unchanged, and comprises their Butut, model and other CAD feature.
In addition, dark p-type diffusion also can be assisted epitaxial loayer expansion diffusion, if necessary, resistance substrate rate for circuit voltage part is mated accurately, equally also can be by diffusion that should be additional for the border at high-pressure installation or other key components (edge or other critical parts) to form electric field.
This epitaxial loayer diffuses to form a kind of method of uniqueness, and the method is utilized thin epitaxial loayer and thick N-shaped district, with low-voltage high density processing procedure, builds high voltage device.The concept of epitaxial loayer expansion is not limited to utilize diffusion to produce, and identical effect also can obtain by the selective epitaxial layer growth.
The foregoing is only preferred embodiments of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, do any modification, be equal to replacement, improve etc., within all should being included in protection scope of the present invention.
Claims (3)
1. on a same substrate, has the semiconductor device of high voltage device and low voltage component, comprise substrate and be formed at the low voltage component zone and high voltage device zone on substrate, it is characterized in that, described high voltage device district inclusion is formed at the n+ drain region of substrate surface, surround the N-shaped epitaxial loayer of this n+ drain region, and the N-shaped extension expansion diffusion layer that is formed at this N-shaped epitaxial loayer below; And between described n+ drain region and N-shaped epitaxial loayer, also have the N-shaped doped region around the n+ drain region, the doping content of this N-shaped doped region is higher than the doping content of described N-shaped epitaxial loayer.
2. on same substrate according to claim 1, have the semiconductor device of high voltage device and low voltage component, it is characterized in that, the doping content of described N-shaped doped region is at 1E16atoms/cm
3～1E18atoms/cm
3Between, the doping content of described N-shaped epitaxial loayer is at 1.5E15atoms/cm
3～5E15atoms/cm
3Between.
3. on same substrate according to claim 1 and 2, have the semiconductor device of high voltage device and low voltage component, it is characterized in that, the thickness of described N-shaped epitaxial loayer is less than 5um.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000312002A (en) * | 1999-04-27 | 2000-11-07 | Sanyo Electric Co Ltd | Semiconductor device and manufacture thereof |
| CN101471301A (en) * | 2007-12-24 | 2009-07-01 | 上海贝岭股份有限公司 | Method for manufacturing bipolar transistor compatible with high voltage and low voltage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000312002A (en) * | 1999-04-27 | 2000-11-07 | Sanyo Electric Co Ltd | Semiconductor device and manufacture thereof |
| CN101471301A (en) * | 2007-12-24 | 2009-07-01 | 上海贝岭股份有限公司 | Method for manufacturing bipolar transistor compatible with high voltage and low voltage |
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