CN102103560A - Anti-deadlock method and device for system buses - Google Patents
Anti-deadlock method and device for system buses Download PDFInfo
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- CN102103560A CN102103560A CN2009102254707A CN200910225470A CN102103560A CN 102103560 A CN102103560 A CN 102103560A CN 2009102254707 A CN2009102254707 A CN 2009102254707A CN 200910225470 A CN200910225470 A CN 200910225470A CN 102103560 A CN102103560 A CN 102103560A
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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Abstract
The invention discloses an anti-deadlock method and device for system buses, wherein the method comprises: a bus interconnecting module receives operating commands sent from masters; and the bus interconnecting module judges whether conditions which can cause system deadlock exist between the parameters of the operating commands which are issued but not completed and the parameters of the received operating commands, if so, the bus interconnecting module blocks the received operating commands. By utilizing the method and device disclosed by the invention, the occurrence of system-bus deadlock can be effectively prevented, and the performance of a system bus can be guaranteed better.
Description
Technical field
The present invention relates to communication field, relate in particular to a kind of deadlock prevention method and device that is used for system bus.
Background technology
At present, comparatively the interconnection protocol of Cheng Shu SoC (System on Chip, SOC (system on a chip)) internal bus has AXI (Advanced extensible Interface, advanced extensive interface), OCP (open nuclear agreement) etc.In the SoC framework based on the AXI bus protocol, the Bus Matrix (bus matrix) by Interconnect (bus interconnection module) realizes the data stream exchange of many Master (main equipment) to many Slave (slave unit).Data tracking is carried out in ID number by data carry of AXI agreement, the Interconnect of AXI judges the purpose outlet according to address control signal, but data are to come sequential delivery according to its sequence number of carrying, that is: must transmit in order for same ID number the data of same Master.Simultaneously, the AXI agreement is supported the transmission mode of Outstanding (hang-up), Out-of-Order (out of order).
So,,,, generally all be modified to the numbering of Master and former ID number combination with ID number in order to distinguish different Master if they adopt ID number identical transmission data for different Master.Like this, for Interconnect, identical ID number the data that different Master send, owing to be modified for ID number, can out of order transmission.And, receive identical ID number the data of different Master for Slave, also can be according to out of order transmission.
But, because Slave makes in AXI bus utilization process for the transmission process mode from identical ID number the data of different Master, deadlock may appear,
Fig. 1 is an AXI bus schematic diagram in the prior art, and in Fig. 1, mi_x_sj is the read command of expression Masteri to Slave j, and x represents ID number.As shown in the figure, Master1 has sent two and has been 0 order ID number, first sends to Slave1, second sends to Slave2, because ID is identical, so will transmit in order, the sequential delivery here is by guaranteeing with the direct-connected Slave interface 1 of Master1, the data transmission that Slave interface 1 needs earlier Slave1 to be returned is given Master1, and the data transmission that Slave2 is returned is given Master1 again, and all send to the Slave1 data transmission earlier, transmission sends to the data of Slave2 again, that is to say the m1_0_s1 order in the first transmission diagram, m1_0-s2 order in the transmission diagram again.In like manner, Master2 has also sent two and has been 0 order ID number among the figure, need the m2_0_s2 order in the first transmission diagram, m2_0_s1 in transmission diagram order again, Slave interface 1 and Slave interface 2 among the figure all need to revise data ID, to distinguish the order of different Master, promptly produce m1_00_s1, m1_00_s2, m2_10_s2, m2_10_s1 with identical ID transmission.So in Interconnect inside, and Slave all can handle the order that is received in different I D number mode, just can out of orderly transmit.At this moment, if the out of order priority processing of Slave1 second the order m2_10_s1, and Slave2 also out of order priority processing second the order m1_00_s2, the data that so just caused Slave1 and Slave2 to return are waited for mutually, and the data bus of Slave1 and Slave2 all can not get discharging, and causes system deadlock.
At present, mainly contain following two kinds of methods and solve the system bus deadlock that above-mentioned reason causes:
1, the Master that connects Interconnect does not carry out the Outstanding transmission mechanism, that is to say, before second accessing operation of Master initiation itself, must wait until that previous accessing operation finishes.
2, single Slave transmission mechanism, that is to say, on the Slave interface that Interconnect connects, increase decision logic, if different Slave of Master visit, Interconnect hangs up second operational access of this Master in inside so, just do not receive this visit, finish just receiving second visit up to previous visit.Because same Master can not visit different Slave simultaneously in the same moment, the deadlock problem occurs so can prevent the AXI system.
But, above-mentioned two kinds of performance loss problem that all have system, and dirigibility is not high yet.For example, for first kind of deadlock prevention method,, influenced the transmission performance of AXI agreement itself like this because a Master itself does not support the Outstanding transmission mechanism; And for second method, Figure 2 shows that a Master visits the situation of different Slave, the operational access Slave2 of an id0 of Master2 front, id1 operation then will be visited Slave1, Interconnect operates the id1 of back to having stoped, at this moment the id1 of Master2 back, id2 operation is all sent out to be come out, if and id0 operation this moment is corresponding very dark at the operation queue of Slave2, and priority is very low, the operation of Master2 back will be blocked for a long time like this, and its Outstanding characteristic is brought into play to be come out yet.
In sum, there has been the problem of the technique influence system bus performance of anti-locking system generation deadlock in prior art always since the midium or long term as can be known, therefore is necessary to propose improved technological means, solves the problems referred to above.
Summary of the invention
Because there is the problem of the technique influence system bus performance of anti-locking system generation deadlock in the prior art, fundamental purpose of the present invention is to provide a kind of deadlock prevention method and device that is used for system bus.
The deadlock prevention method that is used for system bus according to the embodiment of the invention comprises: the bus interconnect module receives the operational order of autonomous device; The bus interconnect module judges and to have issued but whether have the condition that causes system deadlock between the parameter of the parameter of uncompleted operational order and the operational order of reception, if the result of judgement is for being, and the operational order of barrage reception then.
Preferably, receive at the bus interconnect module before the operational order of autonomous device, this method further comprises: the storage of bus interconnect module has issued but the parameter of uncompleted operational order.
Preferably, the parameter of operational order comprises at least: the slave unit of transmission sequence number and visit.
Preferably, cause the condition of system deadlock further to comprise: to issue but the transmission sequence number of uncompleted operational order is identical with the transmission sequence number of the operational order of reception; Issued but slave unit that the slave unit of uncompleted operational order visit and the operational order of reception are visited is different.
Preferably, the operational order of bus interconnect module barrage reception further comprises: the bus interconnect module does not send the operational order that receives to corresponding slave unit, and buffer memory is somebody's turn to do the operational order that receives.
Preferably, system bus is for supporting the system bus of advanced extensible interface bus agreement.
The anti-deadlock device that is used for system bus according to the embodiment of the invention comprises: receiver module is used to receive the operational order of autonomous device; Judge module is used to judge issued but whether have the condition that causes system deadlock between the parameter of the operational order that the parameter of uncompleted operational order and receiver module receive; Block module, be used for if the judged result of judge module is for being, then the operational order of barrage reception module reception.
Preferably, this device further comprises: memory module, it is connected with judge module, is used to store issued but the parameter of uncompleted operational order.
Preferably, the parameter of operational order comprises: the slave unit of transmission sequence number and visit.
Preferably, judge module further comprises: first judges submodule, be used to judge the memory module storage issue but whether the transmission sequence number of uncompleted operational order identical with the transmission sequence number of the operational order of receiver module reception; With second judge submodule, be used to judge the memory module storage issue but whether slave unit that the slave unit of uncompleted operational order visit and the operational order that receiver module receives are visited different.
Compared with prior art, according to technique scheme of the present invention, when judging the condition that has possibility generation systems deadlock, obstruction rigidly connects the operational order of receiving, has prevented the generation of system bus deadlock situation effectively, has guaranteed the performance of system bus preferably.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is an AXI bus schematic diagram in the prior art;
Fig. 2 is a deadlock prevention method utilization synoptic diagram in the prior art;
Fig. 3 is the synoptic diagram according to the deadlock prevention method of the embodiment of the invention;
Fig. 4 is the synoptic diagram according to the preferred process flow process of the deadlock prevention method of the embodiment of the invention;
Fig. 5 is a block diagram of preventing the deadlock device according to an embodiment of the invention;
Fig. 6 is a block diagram of preventing the preferred structure of deadlock device according to an embodiment of the invention.
Embodiment
Main thought of the present invention mainly is, the present invention is by when receiving an operational order, judge at first whether this operational order can and have been sent before but between the still uncompleted object run order deadlock is taken place, if there is the condition of deadlock in two above-mentioned operational orders, just think deadlock may take place, then need to block, to block the condition that deadlock may take place with rigidly connecting the operational order of receiving.Therefore, prevented the generation of deadlock situation.Technical solution of the present invention is passed through judgment mechanism flexibly, can handle the condition that deadlock takes place flexibly, can prevent effectively that on the one hand the system bus deadlock situation from taking place; Guarantee simultaneously the processing speed of operational order on the whole, can guarantee the performance of system bus preferably, in actual applications, this system bus is preferably the system bus of supporting the AXI bus protocol.
For making the purpose, technical solutions and advantages of the present invention clearer,, the present invention is described in further detail below in conjunction with drawings and the specific embodiments.
According to embodiments of the invention, provide a kind of deadlock prevention method that is used for system bus.
Fig. 3 is the synoptic diagram according to the deadlock prevention method that is used for system bus of the embodiment of the invention, and as shown in Figure 3, this method comprises:
Step S302, the bus interconnect module receives the operational order of autonomous device; The parameter of operational order comprises at least: the slave unit of transmission sequence number and visit.
Step S304, bus interconnect module judge and to have issued but whether have the condition that causes system deadlock between the parameter of the parameter of uncompleted operational order and the operational order of reception, if the result of judgement is for being, and the operational order of barrage reception then.
The bus interconnect module is after receiving the operational order of autonomous device, be not issued to the processing of the slave unit corresponding with this operational order, and carry out the processing of step S304 earlier, promptly, judge and to have issued but whether have the condition that causes system deadlock between the parameter of the operational order of the parameter of uncompleted operational order and reception, that is to say, judge the operational order of this new reception and issued before but whether can cause system deadlock between the uncompleted operational order.If judged result is for being (promptly, can cause system deadlock), the operational order of then blocking this new reception, do not send this operational order to corresponding slave unit, and this operational order of buffer memory, send of the processing of this operational order up to causing the operational order (promptly above issue but uncompleted operational order) of system deadlock to finish with this operational order, just carrying out to corresponding slave unit; If for denying (that is, can not cause system deadlock), then directly carrying out, judged result sends of the processing of this operational order to corresponding slave unit.
Above-mentioned arbitration functions is an important content of the present invention, exist and to cause the condition of system deadlock to be: issued but the transmission sequence number of uncompleted operational order is identical with the transmission sequence number of the operational order of reception, and the slave unit difference of visit, that is, same main equipment adopts the different slave unit of operational order visit of same sequence number.When above-mentioned condition is satisfied in judgement, judge the condition that causes system deadlock that exists, thereby carry out the processing of the operational order of blocking this new reception.
Need to prove, the storage of bus interconnect module has been issued to the parameter of the operational order of slave unit, when slave unit was finished this operational order, then this operational order of deletion storage or this operational order of finishing were set to invalidly, guarantee not influence the normal operation of system.
Therefore, according to above-mentioned processing, when there was the condition of possibility generation systems deadlock in the embodiment of the invention by judgment mechanism judgement flexibly, obstruction rigidly connected the operational order of receiving, makes deadlock can not take place.
Describe the embodiment of the invention in detail below in conjunction with Fig. 4.Fig. 4 is the synoptic diagram according to the preferred process flow process of the deadlock prevention method of the embodiment of the invention, and as shown in Figure 4, this method may further comprise the steps:
Step S402, the bus interconnect module receives the operational order that main equipment sends to slave unit, and this operational order can include but not limited to following information: the concrete operations of the slave unit of sequence number, visit, operational order corresponding address, operational order.
Step S404 obtains the sequence number of the object run order that the bus interconnect module newly transfers and the slave unit of visit.
The bus interconnect module is judged received operational order and is issued but whether uncompleted object run order can cause system deadlock.Judge whether to cause the concrete technology of system deadlock to be in the present embodiment:
Step S406, at first by obtaining the sequence number that issues the object run order and the slave unit of visit from memory module, judging whether existing issuing but uncompleted object run order of main equipment, if, execution in step S408 then; Otherwise execution in step S414, and process ends.
Step S408 then, judges that more whether transmission that main equipment newly issues issues but uncompleted object run command transfer sequence number is identical with existing, if identical, further execution in step S410 then, otherwise execution in step S414, and process ends.
Step S410 continues to judge that whether transmission that main equipment newly issues issues but slave unit that uncompleted object run order is visited is different with existing, if difference, then there is the condition that deadlock may take place, execution in step S412, otherwise execution in step S414, and process ends.
Step S412, the bus interconnect module blocks received operational order, include but not limited to following implementation: it is invalid that this operational order of transmission in the bus interconnect module is changed to corresponding slave unit ready signal (axready), and the operational order that receives is carried out buffer memory.
Step S414, the bus interconnect module sends to corresponding slave unit by channel interface with operational order, and process ends.
According to embodiments of the invention, also provide a kind of anti-deadlock device that is used for system bus.This device can be arranged in the bus interconnect module, also can be provided with separately.
Fig. 5 is the block diagram that is used for the anti-deadlock device of system bus according to an embodiment of the invention, and Fig. 6 is the block diagram of preferred structure that is used for the anti-deadlock device of system bus according to an embodiment of the invention.
As shown in Figure 5, devices in accordance with embodiments of the present invention comprises: receiver module 10, judge module 20 blocks module 30.
Wherein, receiver module 10 is used to receive the operational order of autonomous device; Judge module 20, the parameter that is used to judge the operational order that receiver module 10 receives with issue but whether the parameter of uncompleted operational order identical, the parameter of operational order includes but not limited to: the slave unit of transmission sequence number and visit; Block module 30, be used for if the judged result of judge module 20 is for being, then the operational order of barrage reception module reception.
As shown in Figure 6, on the basis of structure shown in Figure 5, this device further comprises: memory module 40, it is connected with judge module 20, is used to store issued but the parameter of uncompleted operational order is called for judge module 20.Judge module 20 further comprises: first judges submodule 210, be used to judge memory module 40 storages issue but whether the transmission sequence number of uncompleted operational order identical with the transmission sequence number of the operational order of receiver module 10 receptions; With second judge submodule 220, be used to judge memory module 40 storages issue but whether slave unit that the slave unit of uncompleted operational order visit and the operational order that receiver module 10 receives are visited identical.
In addition, consider that can also comprise according to the device of the embodiment of the invention: module 50 takes place, and it is connected with judge module 20, is used for operational order is sent to corresponding slave unit based on integrality.
To sum up, the technique scheme according to the present invention, when having the condition of possibility generation systems deadlock by judgement, obstruction rigidly connects the operational order of receiving, has prevented the generation of system bus deadlock situation effectively, has guaranteed the performance of system bus preferably.
The above is embodiments of the invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (10)
1. a deadlock prevention method that is used for system bus is characterized in that, comprising:
The bus interconnect module receives the operational order of autonomous device;
Described bus interconnect module judges and issued but whether have the condition that causes system deadlock between the parameter of the parameter of uncompleted operational order and the operational order of reception, if the result of judgement is for being, and the described operational order of barrage reception then.
2. method according to claim 1 is characterized in that, before the operational order of described bus interconnect module reception from described main equipment, described method further comprises:
Described bus interconnect module storage has issued but the parameter of uncompleted operational order.
3. method according to claim 1 and 2 is characterized in that, the parameter of described operational order comprises at least: the slave unit of transmission sequence number and visit.
4. method according to claim 3 is characterized in that, the described condition of system deadlock that causes further comprises:
Issued but the transmission sequence number of uncompleted operational order is identical with the transmission sequence number of the operational order of reception; With
Issued but slave unit that the slave unit of uncompleted operational order visit and the operational order of reception are visited is different.
5. method according to claim 1 is characterized in that, the described operational order of described bus interconnect module barrage reception further comprises:
Described bus interconnect module does not send the operational order that receives to corresponding slave unit, and buffer memory is somebody's turn to do the operational order that receives.
6. method according to claim 1 is characterized in that, described system bus is for supporting the system bus of advanced extensible interface bus agreement.
7. an anti-deadlock device that is used for system bus is characterized in that, comprising:
Receiver module is used to receive the operational order of autonomous device;
Judge module is used to judge issued but whether have the condition that causes system deadlock between the parameter of the operational order that the parameter of uncompleted operational order and described receiver module receive;
Block module, be used for if the judged result of described judge module is for being then to block the operational order of described receiver module reception.
8. device according to claim 6 is characterized in that, further comprises:
Memory module, it is connected with described judge module, is used to store issued but the parameter of uncompleted operational order.
9. according to claim 7 or 8 described devices, it is characterized in that the parameter of described operational order comprises: the slave unit of transmission sequence number and visit.
10. device according to claim 9 is characterized in that, described judge module further comprises:
First judges submodule, be used to judge described memory module storage issue but whether the transmission sequence number of uncompleted operational order identical with the transmission sequence number of the operational order of described receiver module reception; With
Second judges submodule, be used to judge described memory module storage issue but whether slave unit that the slave unit of uncompleted operational order visit and the operational order that described receiver module receives are visited different.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102254707A CN102103560A (en) | 2009-12-16 | 2009-12-16 | Anti-deadlock method and device for system buses |
| PCT/CN2010/075839 WO2011072533A1 (en) | 2009-12-16 | 2010-08-10 | Deadlock prevention method and device from system bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102254707A CN102103560A (en) | 2009-12-16 | 2009-12-16 | Anti-deadlock method and device for system buses |
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| CN102103560A true CN102103560A (en) | 2011-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009102254707A Pending CN102103560A (en) | 2009-12-16 | 2009-12-16 | Anti-deadlock method and device for system buses |
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| CN (1) | CN102103560A (en) |
| WO (1) | WO2011072533A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017036242A1 (en) * | 2015-08-31 | 2017-03-09 | 华为技术有限公司 | Data processing method, apparatus, and system |
| WO2018107658A1 (en) * | 2016-12-15 | 2018-06-21 | 深圳市中兴微电子技术有限公司 | Method and device for avoiding deadlock of bus, and storage medium |
| CN110196826A (en) * | 2018-02-24 | 2019-09-03 | 深圳市中兴微电子技术有限公司 | A kind of deadlock judgment method and device |
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| US20030101298A1 (en) * | 2001-09-27 | 2003-05-29 | Chang Yeow Khai | Bus system and bus interface |
| CN101154210A (en) * | 2006-09-26 | 2008-04-02 | 联想(北京)有限公司 | Method and device for preventing dead lock of LPC bus line |
| CN101308477A (en) * | 2008-06-13 | 2008-11-19 | 华为技术有限公司 | System bus deadlock prevention method, device and on-chip system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7657682B2 (en) * | 2007-09-14 | 2010-02-02 | Freescale Semiconductor, Inc. | Bus interconnect with flow control |
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2009
- 2009-12-16 CN CN2009102254707A patent/CN102103560A/en active Pending
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2010
- 2010-08-10 WO PCT/CN2010/075839 patent/WO2011072533A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030101298A1 (en) * | 2001-09-27 | 2003-05-29 | Chang Yeow Khai | Bus system and bus interface |
| CN101154210A (en) * | 2006-09-26 | 2008-04-02 | 联想(北京)有限公司 | Method and device for preventing dead lock of LPC bus line |
| CN101308477A (en) * | 2008-06-13 | 2008-11-19 | 华为技术有限公司 | System bus deadlock prevention method, device and on-chip system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017036242A1 (en) * | 2015-08-31 | 2017-03-09 | 华为技术有限公司 | Data processing method, apparatus, and system |
| WO2018107658A1 (en) * | 2016-12-15 | 2018-06-21 | 深圳市中兴微电子技术有限公司 | Method and device for avoiding deadlock of bus, and storage medium |
| CN110196826A (en) * | 2018-02-24 | 2019-09-03 | 深圳市中兴微电子技术有限公司 | A kind of deadlock judgment method and device |
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| Publication number | Publication date |
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| WO2011072533A1 (en) | 2011-06-23 |
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Application publication date: 20110622 Assignee: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Assignor: ZTE Corporation Contract record no.: 2015440020319 Denomination of invention: Anti-deadlock method and device for system buses License type: Common License Record date: 20151123 |
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Application publication date: 20110622 |