CN100533417C - Method for transferring data of systems on chip, and direct memory access controller - Google Patents
Method for transferring data of systems on chip, and direct memory access controller Download PDFInfo
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- CN100533417C CN100533417C CNB2006101715596A CN200610171559A CN100533417C CN 100533417 C CN100533417 C CN 100533417C CN B2006101715596 A CNB2006101715596 A CN B2006101715596A CN 200610171559 A CN200610171559 A CN 200610171559A CN 100533417 C CN100533417 C CN 100533417C
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Abstract
A method for transmitting data of system on chip includes setting at least one data register with countermark in access controller of direct-storage at system on chip, filling data of source unit and state position of data register countermark into said data register by source stator, fetching data in said data register and transmitting fetched data to destination device by destination state when state position corresponding to destination stator is on fetch-able state. The access controller of direct-storage at system on chip is also disclosed.
Description
Technical field
The present invention relates to the SOC (system on a chip) field, particularly relate to the data transmission method and the direct memory access controller of SOC (system on a chip).
Background technology
Along with development of semiconductor, SOC (system on a chip) allows increasing module is integrated among the single chip, chip designer institute towards system applies also more sophisticated with diversified.The data transmission of SOC (system on a chip) adopts direct memory visit (DMA) form more, rely on the data between hardware realization source device and the destination device directly to transmit, and data transmission procedure does not need processor intervention.
At present, the direct memory introduced in SOC (system on a chip) visit (DMA) mainly is divided into two kinds of patterns, a kind ofly is based on centralized transmission mode, and all stream data transmission are born by one or minority dma controller system in, thereby help the shared of transfer resource; Another kind is based on distributed transmission mode, system has the module of transmission demand to set up dma controller and transmission channel separately, during the transmission data, start the dma controller of respective sources equipment and destination device, by the data bus of special use or the transmission of data channel realization data.
Consult Fig. 1,, comprise master controller 11, buffer memory 12, dma controller 13, reach processing engine 14 for adopting SOC (system on a chip) synoptic diagram based on the DMA of localized transmission pattern.Dma controller 13 is arranged on the data transmission bus, uses separate data channels, and master controller 11 through the data that buffer memory 12 sends, is sent in the processing engine 14 of appointment.But the localized transmission pattern, is tending to because the setting of dma controller 13 main interfaces is subjected to bus-structured restriction, thereby is influencing the transmission delay and the overall performance of system during to the data flow transmission towards complication system many.
Consult Fig. 2, for adopting SOC (system on a chip) synoptic diagram based on the DMA of distributing transmission mode.Each processing engine 14 is by data buffering 15 dma controller 13 that is of coupled connections.When processing engine 14 needed the transmission data, the dma controller 13 of its connection transmitted data by the data channel of special use.The distributing data-transmission mode though can reduce the shared conflict of system resource, has also improved the cost of data transmission with each module localization, proprietaryization simultaneously, and processing engine is during 14 free time, and the utilization factor of its corresponding dma controller 13 is very low.
Consulting Fig. 3, is the inner structure synoptic diagram of existing dma controller 13, comprises hardware handshaking interface 131, source state machine 132, buffering FIFO133, purpose state machine 134, moderator 135, main interface 136, reaches from interface 137.
In this dma controller 13, source state machine 132 and purpose state machine 134 are one to one, all use independently channel transmission data between the every pair of source state machine 132 and the purpose state machine 134.Therefore, no matter be centralized, or distributed dma controller 13, all be only applicable to the transmission of a plurality of independent data streams.Dma controller 13 is in the data transmission of multiple source equipment to a plurality of destination devices, and each source state machine 132 all needs access originator equipment, and source device is sent to each source state machine 132 after also must duplicating data repeatedly.The contention access of 132 pairs of source devices of source state machine has increased the total processing delay of system, and data are duplicated repeatedly back transmission and caused the volume of transmitted data of SOC (system on a chip) and bus transfer load to strengthen.
Along with the SoC designing institute towards application become increasingly complex and variation, the agreement that the field is calculated in many communications all designs based on the thought of packet transaction, these agreements comprise reception usually, handle, transmit and abandon the operation of integrated data etc.Thereby each grouping generally can be carried out a plurality of processing and safe operation, for example: in wireless local area security protocol TKIP, to do a plurality of operations such as Michael completeness check, CRC32 verification, data encryption simultaneously to an integrated data, but every kind of operation handled packet header data and not quite identical, thereby make that the data interaction of each intermodule becomes complicated unusually in the system.So just, formed a kind of new data-transmission mode---from a data source simultaneously to the transmission of a plurality of data destination devices---both multicast transmission of SOC (system on a chip).And in this multicast transmission, run into the identical or most of identical situation of the handled data of two or more purpose state machines is arranged through regular meeting; existing dma controller is in the face of such transmission the time; because of it transmits data with the buffering FIFO in the inner structure as the autonomous channel between every pair of source and purpose state machine; this needs repeatedly access originator equipment of source state machine; obtain data, be sent to each purpose state machine by buffering FIFO again.The repeatedly transmission of identical data will cause the volume of transmitted data of SOC (system on a chip) and bus transfer load to increase.
Summary of the invention
Technical matters to be solved by this invention provides a kind of data transmission method of SOC (system on a chip), can reduce repeatedly the visiting and the total processing delay of increase system of source device, reduces the volume of transmitted data of SOC (system on a chip) and loads with bus transfer.
Another object of the present invention provides a kind of dma controller of SOC (system on a chip), this dma controller is when SOC (system on a chip) is carried out data transmission, can reduce repeatedly the visiting and the total processing delay of increase system of source device, reduce the volume of transmitted data of SOC (system on a chip) and load with bus transfer.
The data transmission method of a kind of SOC (system on a chip) of the present invention comprises:
In the direct memory access controller of SOC (system on a chip) the data register that at least one has label is set, described label comprises and purpose state machine mode bit one to one;
The source state machine is filled up to described data register with the data of source device, and fills in the mode bit of described data register label;
Described purpose state machine when can read state, reads the data in the described data register at its corresponding mode bit, is sent to destination device.
Preferably, by following step, the source state machine is filled up to described data register with the data of source device:
The data that source state machine reception sources equipment transmits;
The source state machine is filled up to each described data register with data by the cycle count mode.
Preferably, by following step, fill in the mode bit of described data register label:
The source state machine need to determine the purpose state machine of reading of data, and the mode bit of this purpose state machine correspondence is extended this as the state of can read.
Preferably, read after the data in the described data register, comprise that also described purpose state machine extends this as the taboo reading state with the mode bit of correspondence.
Preferably, the size of each described data register is to preset the transfer bus effective width of multiple:
The described highest common factor that presets the burst number of burst number that multiple is a source device and destination device.
Preferably, as having the mode bit that is in the state of can read in the data register label, forbid that then described source state machine fills in data to this data register.
Preferably, all be in the taboo reading state, then hang up described purpose state machine as each mode bit of data register label.
The direct memory access controller of a kind of SOC (system on a chip) of the present invention comprises data reservation station, at least one source state machine, reaches at least one purpose state machine;
Described data reservation station comprises the data register that at least one has label, and described label comprises and purpose state machine mode bit one to one;
Described source state machine is used for the data of source device are filled up to described data register, and fills in the mode bit of its label;
Described purpose state machine is used at the mode bit of correspondence reading the data in the described data register when can read state, is sent to destination device.
Preferably, described source state machine comprises set unit, source and data transmission unit;
Described data transmission unit is used for the data of source device are sent to described data register;
Set unit, described source is used for definite purpose state machine that need read above-mentioned data, and the mode bit of this purpose state machine correspondence is extended this as the state of can read.
Preferably, described source state machine also comprises;
Forbid transmission unit, be used for when the label of data register has the mode bit that is in the state of can read, forbid that described data transmission unit fills in data to described data register.
Preferably, described purpose state machine comprises data transfer unit and purpose set unit;
Described data transfer unit is used at the mode bit of correspondence reading the data in the described data register when can read state, is sent to destination device;
Described purpose set unit is used for after described data transfer unit reading of data, and the mode bit of this purpose state machine correspondence is extended this as the taboo reading state.
Preferably, described purpose state machine also comprises;
Forbid reading unit, be used for when each mode bit of data register label all is in the taboo reading state, hanging up described purpose state machine.
Preferably, the size of each described data register is to preset the transfer bus effective width of multiple:
The described highest common factor that presets the burst number of burst number that multiple is a source device and destination device.
Compared with prior art, the present invention has the following advantages:
The present invention adopts the data reservation station to substitute the buffering FIFO that has now in the direct access controller, and former independently data transmission channel is shared.Comprise a plurality of data registers that have label in the data reservation station, label comprises and purpose state machine mode bit one to one.The source state machine arrives data register with the data forwarding that source device transmits, the state position of purpose state machine correspondence of simultaneously needs being read these data is in the state of can read, make need the purpose of these data state machine at its corresponding mode bit when can read state, read this data, and be sent to corresponding target equipment.Like this, use multicast transmission, only need source device of source state machine visit, avoid increasing the volume of transmitted data and the bus transfer load of SOC (system on a chip) in SOC (system on a chip).Simultaneously, the present invention does not need reading of data simultaneously because of each purpose state machine is to come reading of data according to its corresponding states position, therefore supports the data transmission of non-complete multicast transmission form.
The size of data register of the present invention is the highest common factor of source device burst and destination device burst.Guaranteeing that each purpose state machine once can read and transmits under the prerequisite of the total data in the data register, allow the purpose state machine can read maximum data at every turn, the overhead control logic of direct memory access (DMA) controller is reduced, the transmission of data is simpler and more direct.
The present invention adopts to write and forbids, when in the label of data register, having the mode bit that is in the state of can read, forbid that the source state machine transmits data to this data register, prevented data register before each purpose state machine is not also finished its read operation, the new data that the source state machine transmits covers former data.
The present invention adopts and to read to forbid, all is in when prohibiting reading state at each mode bit of the label of data register, hangs up, suspends the purpose state machine from this data register reading of data.Avoid when certain purpose state machine is faster than source state machine transmission data to the reading speed of data register, appearance source state machine does not also transfer data to data register, each mode bit of label is not filled in yet, but this purpose state machine is the taboo reading state because of its corresponding mode bit, and skip this data register, cause the order that reads and writes data of source state machine and purpose state machine chaotic.
Description of drawings
Fig. 1 is for adopting the SOC (system on a chip) synoptic diagram based on the DMA of localized transmission pattern;
Fig. 2 is for adopting the SOC (system on a chip) synoptic diagram based on the DMA of distributing transmission mode;
Fig. 3 is the inner structure synoptic diagram of existing dma controller;
Fig. 4 is the structural representation of dma controller one embodiment of the present invention;
Fig. 5 is the structural representation of data reservation station one embodiment of the present invention;
Fig. 6 is the read-write logic control synoptic diagram of data reservation station of the present invention;
Fig. 7 is the structural representation of another embodiment of dma controller of the present invention;
Fig. 8 is source of the present invention state machine one an example structure synoptic diagram;
Fig. 9 is the object of the invention state machine one example structure synoptic diagram;
Figure 10 is the data multicast transmission method one embodiment process flow diagram of SOC (system on a chip) of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Core concept of the present invention is the buffering FIFO that adopts in the alternative former direct access controller of data reservation station, and former independently data transmission channel is shared.Comprise a plurality of data registers that have label in the data reservation station, label comprises and purpose state machine mode bit one to one.The source state machine arrives data register with the data forwarding that source device transmits, the state position of purpose state machine correspondence of simultaneously needs being read these data is in the state of can read, make need the purpose of these data state machine at its corresponding mode bit when can read state, read this data, and be sent to corresponding target equipment.At the source state machine during from the source device reading of data, the data that will be transferred to each destination device in a read cycle read out simultaneously, be forwarded in the described data register, like this if be transferred to have in the data of each destination device part or all of when identical, same section only need read once from source device, thereby reduced repeatedly the visiting and the total processing delay of increase system of source device, reduced the volume of transmitted data and the bus transfer load of SOC (system on a chip).
Consult Fig. 4, be the structural representation of dma controller one embodiment of the present invention, comprise hardware handshaking interface 131, source state machine 132, a plurality of purpose state machine 134, moderator 135, a plurality of main interface 136, from interface 137, and data reservation station 41.
Each purpose state machine 134 detects mode bits its correspondence, data reservation station 41 interior each data register label, when mode bit numerical value is " 1 ", purpose state machine 134 reads the data in this data register, and this mode bit is extended this as " 0 ", and the expression data read.Purpose state machine 134 is sent to its corresponding destination device by moderator 135, main interface 136 with data.When mode bit numerical value was " 0 ", purpose state machine 134 did not read these data and deposits interior data.
From interface 137 connection processing devices and source state machine 132, each purpose state machine 134, the data transfer instruction of processor is sent to corresponding source state machine 132 and purpose state machine 134.
Consult Fig. 5, be the structural representation of data reservation station 41 1 embodiment of the present invention, this data reservation station 41 comprises 4 data registers, is respectively data register 1, data register 2, data register 3, reaches data register 4.Each data register all comprises the label with three mode bits, is divided into first mode bit, second mode bit, third state position.The all corresponding purpose state machine 134 of each mode bit.
Each purpose state machine 134 during reading of data, needs to detect earlier the state value of mode bit its correspondence, data register 1 label by the cycle count mode data register 1 in.The first purpose state machine 134 detects its corresponding first mode bit and is " 1 ", then reads these data, and first mode bit of data register 1 label extends this as " 0 " simultaneously.Second and third mode bit that second and third purpose state machine 134 detects its correspondence is " 0 ", then data in the read data register 1 not.
The capacity of each data register is big more, the data that each purpose state machine 134 once reads are just many more, the overhead control logic of dma controller just reduces a lot, data transmission is more convenient, but also must guarantee the data of each purpose state machine 134 in once can read data register, to prevent the data read confusion.Therefore, the capacity of data register need be taken all factors into consideration following factor, the size of the burst of source device data transmission (burst) size, each destination device transmission burst, and above-mentioned burst value between highest common factor.Burst is for sending the number of data address in transmission cycle of equipment, each equipment can only transmit in a transmission cycle and burst respective sets data.Optimal way can be the highest common factor of above-mentioned burst value for the size of each data register.
As, the size of source device burst is that the burst of 8, the first destination devices is that the burst of 4, the second destination devices is that the burst of 12, the three destination devices is 24.This shows in 132 1 transmission cycles of source state machine can transmit 8 groups of data, can read 4 groups of data in the first purpose state machine, 134 one-periods, can read 8 groups of data in the second purpose state machine, 134 one-periods, can read 12 groups of data in the 3rd purpose state machine 134 one-periods.Wherein, 8,4,8,12 highest common factor is 4, and the size of each data register is 4, and the capacity of representing each data register is the effective width of 4 times of transfer bus.
。Guaranteeing that each purpose state machine 134 once can read and transmits under the prerequisite of the total data in the data register, allow each purpose state machine 134 can read maximum data at every turn.
For fear of between purpose state machine 132 and the source state machine 134 to the read/write conflict of data reservation station 41 same registers, also need to read and write accordingly steering logic.Consult Fig. 6, be the read-write logic control synoptic diagram of data reservation station 41 of the present invention, the read-write logic control is divided into writing and forbids logic and read to forbid logic.
Each data register is not before all purpose state machines 134 are also finished read operation to it, for guaranteeing that source state machine 132 does not carry out write operation to it, avoid covering former data, the present invention adopts to write and forbids logic: with whole mode bits of data register label carry out reduction or; If the result is " 1 ", show to have the mode bit that is in the state of can read in this label, also have purpose state machine 134 not read the interior data of this data register, forbid the write operation of source state machine 132 this moment; If the result is " 0 ", show the mode bit that is not in the state of can read in this label, purpose state machine 134 has all read the data in this data register, then allows the write operation of source state machine 132.
Reading speed as 134 pairs of data reservation stations 41 of certain purpose state machine is faster than source state machine 132 writing speeds, the data that data register then can occur are not written into as yet, the mode bit of label is fill state value not also, the corresponding states position that this purpose state machine 134 detects this data register label is " 0 ", then skip this read cycle, cause source state machine 132 chaotic with the read-write order of purpose state machine 134.For avoiding this situation to occur, the present invention adopts and to read to forbid logic: to whole mode bits of data register label carry out reduction or, if the result is " 0 ", show that this data register label does not have the mode bit that is in desirable condition, forbid that then each purpose state machine 134 reads the data in this data register, hang up, suspend the condition checkout gear and the state updating device of each purpose state machine 134 inside that will read this data register; If the result is " 1 ", then normal sequence reads.
Because of source state machine 132 when the data register is filled in data, must there be a purpose state machine 134 need read these data, therefore exist the value of a mode bit to be " 1 " in the mode bit of this data register label at least, as each mode bit all is " 0 ", both stipulations or value were " 0 ", expression source state machine 132 is not also filled in data, forbids that each purpose state machine 134 skips this data register, avoids the data write confusion.
Data in the data reservation station 41 of the present invention directly come from source state machine 132, and directly are directed to each purpose state machine 134.The inquiry of the tag state position of 134 pairs of data reservation stations 41 of source state machine, fill in data, fill in the time sequential routine such as tag state position and can realize, guarantee to finish in the average one-period one time write operation by streamline.In like manner, the time sequential routines such as the tag state position detection of 134 pairs of data reservation stations 41 of purpose state machine, reading of data, renewal tag state position also can realize by streamline, guarantee that on average the phase is finished read operation one time weekly.
Because the read-write operation to data reservation station 41 of source state machine 132, purpose state machine 134 does not conflict, therefore can walk abreast and carry out, to improve data rate.If all corresponding host bus interface 136 of each state machine of this dma controller, and respective bus speed is enough high, in the time of can not becoming the bottleneck of DMA data transmission, the maximum transmission rate of the normal operation of SOC (system on a chip) can make each purpose state machine parallel transmission data simultaneously.
When the present invention uses multicast transmission in SOC (system on a chip), identical data part for all purpose state machines transmission, only need source device of source state machine 132 visits, reduced because of the repeatedly visit to source device increases the total processing delay of SOC (system on a chip), avoided increasing the volume of transmitted data and the bus transfer load of SOC (system on a chip).
Simultaneously, the present invention is to come reading of data according to its corresponding states position because of each purpose state machine 134, therefore can realize that each purpose state machine 134 does not read, transmits data simultaneously.As, the present invention can make the first purpose state machine reading of data by filling in the mode bit of data register, and second, third purpose state machine reading of data not, the a certain data that realize source device are only to first destination device, less than the transmission of second, third destination device.Therefore the present invention supports the data transmission of non-complete multicast transmission form.
Consult Fig. 7, be the structural representation of another embodiment of dma controller of the present invention, comprise hardware handshaking interface 131, multiple source state machine 132, a plurality of purpose state machine 134, moderator 135, a plurality of main interface 136, from interface 137, and data reservation station 41.
Each purpose state machine 134 detects mode bits its correspondence, data reservation station 41 interior each data register label, when mode bit numerical value is " 1 ", purpose state machine 134 reads the data in this data register, and this mode bit is extended this as " 0 ", and the expression data read.Purpose state machine 134 is sent to its corresponding destination device by moderator 135, main interface 136 with data.When mode bit numerical value was " 0 ", purpose state machine 134 did not read these data and deposits interior data.
Each source state machine 132 obtains the operation power of filling in data register by certain priority mechanism, and upgrades its inner cycle counter and address counter that points to the data register pointer only for the source state machine 132 that writes data simultaneously in this operating cycle; Other do not fill in 132 renewal cycle counters of source state machine of data, and scheduler counter not is to guarantee the correct execution of transmission configuration.
Consult Fig. 8, be source of the present invention state machine one example structure synoptic diagram, comprise data transmission unit 81, set unit, source 82, forbid transmission unit 83 and the unit 84 of avoiding a conflict.
Data transmission unit 81 is filled up to each data register in the data reservation station with the data of source device by the cycle count mode, send information to set unit, source 82 simultaneously.
The purpose state machines 134 of above-mentioned data are determined to read in set unit, source 82, and the mode bit of this data register label of these purpose state machine 134 correspondences is extended this as the state of can read " 1 ", and other mode bit extends this as prohibits reading state " 0 ".
When forbidding that transmission unit 83 has the mode bit that is in the state of can read in the label of data register, send and forbid filling in data command to data transmission unit 81, forbidden data transmission unit 81 is to these data register transmission data.
As 13 source state machine 132 in the dma controller is two or more, and then each source state machine 132 also comprises the unit 84 of avoiding a conflict.The unit 84 of avoiding a conflict utilizes arbitrated logic, solves multiple source state machine 132 simultaneously to the problem of the contention access of data register.
The unit 84 of avoiding a conflict is connected with data storage cell 81, avoid a conflict unit 84 as receive the confirmation of filling in that data transmission unit 81 sends when filling in data then upgrades its inner cycle counter and address counter that points to the data register pointer simultaneously in this operating cycle; As do not receive the information that other do not have data transmission unit 81 to send when filling in data, then only upgrade cycle counter, scheduler counter not is to guarantee the correct execution of transmission configuration.
Consult Fig. 9, be the object of the invention state machine one example structure synoptic diagram, comprise data transfer unit 91, purpose set unit 92 and forbid reading unit 93.
Purpose set unit 92 receive data transfer unit 91 read information after, the mode bit of these purpose state machine 134 correspondences is extended this as the taboo reading state.
Forbid that reading unit 93 is when each mode bit of data register label all is in the taboo reading state, send to hang up and to instruct purpose set unit 92 and data transfer unit 91, make purpose set unit 92 and data transfer unit 91 be in the temporary suspension state, time-out is from this data register reading of data, and fills in the corresponding state position.
Consult Figure 10, the data multicast transmission method one embodiment process flow diagram for a kind of SOC (system on a chip) of the present invention specifically may further comprise the steps.
Step 1001, data reservation station 41 is set in the dma controller of SOC (system on a chip), data reservation station 41 comprises a plurality of data registers that have label, and label comprises the mode bit corresponding with purpose state machine 134.
The data that step 1002, source state machine 132 reception sources equipment transmit by main interface 136, moderator 135.
Step 1003, source state machine 132 are filled up to each data register in the data reservation station 41 by the cycle count mode with data.
Step 1004, source state machine 132 need to determine each purpose state machine 134 of reading of data, and the mode bit of these purpose state machine 134 correspondences is extended this as the state of can read.
The current state of step 1005, purpose state machine 134 its corresponding mode bits of inquiry, as be the state of can read, interior data of read data register then; As for can not then abandoning reading of data by reading state.
Step 1006, purpose state machine 134 transfer data to destination device, and the mode bit of correspondence is extended this as the taboo reading state.
If the data transfer task that the dma controller of SOC (system on a chip) is born is simple relatively.As, 1 o'clock to 2 o'clock data transmission just, the present invention can merge source state machine 132 and purpose state machine 134, unified data reservation station 41 is controlled, to realize the multicast transmission of data.Equally, the present invention can with source state machine 132, and 134 pairs of data reservation stations of purpose state machine 41 in detected state position, fill state value, update mode value, and the operation such as read-write logic control of each mode bit of data register labels, unifiedly realize by a certain equipment.
The present invention adopts centralized Data Transmission Controlling, on the basis of existing dma controller, need not do change bigger, complexity and can realize, is highly suitable for present embedded SOC (system on a chip) and uses.
More than to the data transmission method and the dma controller of SOC (system on a chip) provided by the present invention, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (13)
1, a kind of data transmission method of SOC (system on a chip) is characterized in that, comprising:
In the direct memory access controller of SOC (system on a chip) the data register that at least one has label is set, described label comprises and purpose state machine mode bit one to one;
The source state machine is filled up to described data register with the data of source device, and fills in the mode bit of described data register label;
Described purpose state machine when can read state, reads the data in the described data register at its corresponding mode bit, is sent to destination device.
2, the method for claim 1 is characterized in that, by following step, the source state machine is filled up to described data register with the data of source device:
The data that source state machine reception sources equipment transmits;
The source state machine is filled up to each described data register with data by the cycle count mode.
3, the method for claim 1 is characterized in that, by following step, fills in the mode bit of described data register label:
The source state machine need to determine the purpose state machine of reading of data, and the mode bit of this purpose state machine correspondence is extended this as the state of can read.
4, the method for claim 1 is characterized in that, reads after the data in the described data register, comprises that also described purpose state machine extends this as the taboo reading state with the mode bit of correspondence.
As each described method of claim 1 to 4, it is characterized in that 5, the size of each described data register is to preset the transfer bus effective width of multiple:
The described highest common factor that presets the burst number of burst number that multiple is described source device and described destination device.
6, as each described method of claim 1 to 4, it is characterized in that,, forbid that then described source state machine fills in data to this data register as having the mode bit that is in the state of can read in the data register label.
7, as each described method of claim 1 to 4, it is characterized in that, all be in the taboo reading state, then hang up described purpose state machine as each mode bit of data register label.
8, a kind of direct memory access controller of SOC (system on a chip) is characterized in that, comprises data reservation station, at least one source state machine, reaches at least one purpose state machine;
Described data reservation station comprises the data register that at least one has label, and described label comprises and purpose state machine mode bit one to one;
Described source state machine is used for the data of source device are filled up to described data register, and fills in the mode bit of its label;
Described purpose state machine is used at the mode bit of correspondence reading the data in the described data register when can read state, is sent to destination device.
9, direct memory access controller as claimed in claim 8 is characterized in that, described source state machine comprises set unit, source and data transmission unit;
Described data transmission unit is used for the data of source device are sent to described data register;
Set unit, described source is used for definite purpose state machine that need read above-mentioned data, and the mode bit of this purpose state machine correspondence is extended this as the state of can read.
10, direct memory access controller as claimed in claim 8 or 9 is characterized in that described source state machine also comprises;
Forbid transmission unit, be used for when the label of data register has the mode bit that is in the state of can read, forbid that described data transmission unit fills in data to described data register.
11, direct memory access controller as claimed in claim 8 is characterized in that, described purpose state machine comprises data transfer unit and purpose set unit;
Described data transfer unit is used at the mode bit of correspondence reading the data in the described data register when can read state, is sent to destination device;
Described purpose set unit is used for after described data transfer unit reading of data, and the mode bit of this purpose state machine correspondence is extended this as the taboo reading state.
12, as claim 8 or 11 described direct memory access controllers, it is characterized in that described purpose state machine also comprises;
Forbid reading unit, be used for when each mode bit of data register label all is in the taboo reading state, hanging up described purpose state machine.
13, direct memory access controller as claimed in claim 8 is characterized in that, the size of each described data register is to preset the transfer bus effective width of multiple:
The described highest common factor that presets the burst number of burst number that multiple is a source device and destination device.
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| CN102306135A (en) * | 2011-06-02 | 2012-01-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | Communication method of IP module of SOC (System-On-Chip) and OCB (On-Chip Bus) |
| US20160103707A1 (en) * | 2014-10-10 | 2016-04-14 | Futurewei Technologies, Inc. | System and Method for System on a Chip |
| CN105677605B (en) * | 2014-11-20 | 2019-04-30 | 深圳市中兴微电子技术有限公司 | It is a kind of efficiently to can configure on piece interacted system and its implementation, device |
| US10496622B2 (en) | 2015-10-09 | 2019-12-03 | Futurewei Technologies, Inc. | System and method for real-time data warehouse |
| US10783160B2 (en) | 2015-10-09 | 2020-09-22 | Futurewei Technologies, Inc. | System and method for scalable distributed real-time data warehouse |
| CN108491293A (en) * | 2018-03-14 | 2018-09-04 | 北京思特奇信息技术股份有限公司 | A kind of data managing method and system |
| CN108897263B (en) * | 2018-09-13 | 2020-06-12 | 杭州华澜微电子股份有限公司 | Intelligent circuit unit with multi-dimensional data transmission and processing function, system and control method thereof |
| CN109584769A (en) * | 2018-12-12 | 2019-04-05 | 惠科股份有限公司 | Control method, display panel and the storage medium of display panel |
| CN110046114B (en) * | 2019-03-06 | 2020-08-14 | 上海熠知电子科技有限公司 | DMA controller based on PCIE protocol and DMA data transmission method |
| CN110008156B (en) | 2019-03-27 | 2020-12-15 | 无锡海斯凯尔医学技术有限公司 | Data transmission device, method and readable storage medium |
-
2006
- 2006-12-30 CN CNB2006101715596A patent/CN100533417C/en active Active
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