CN110196826A - A kind of deadlock judgment method and device - Google Patents

A kind of deadlock judgment method and device Download PDF

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Publication number
CN110196826A
CN110196826A CN201810157747.6A CN201810157747A CN110196826A CN 110196826 A CN110196826 A CN 110196826A CN 201810157747 A CN201810157747 A CN 201810157747A CN 110196826 A CN110196826 A CN 110196826A
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transmission
state
transmission data
data
delay
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CN110196826B (en
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刘毅
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Sanechips Technology Co Ltd
Shenzhen ZTE Microelectronics Technology Co Ltd
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Shenzhen ZTE Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

The embodiment of the invention discloses a kind of deadlock judgment method and devices, this method may include: to receive the first transmission data, the corresponding first object address of the first transmission data is obtained, and according to preset path time delay table, determines the first transmission data corresponding first default arrival time；When the first default arrival time the second default arrival time corresponding less than the second transmission data, preferential state is set by corresponding first transmission state of the first transmission data, and deferred mode is set by corresponding second transmission state of the second transmission data, the second transmission data are to be sent to the transmission data of first object address；According to the second transmission state, the corresponding present transmission state of transmission path from initial address to destination address is updated, and according to present transmission state and the first transmission state, judges whether the first transmission data meet default dead lock condition；When judging that the first transmission data meet default dead lock condition, transmission the first transmission data are prevented.

Description

A kind of deadlock judgment method and device
Technical field
The present invention relates to good digital chip design field more particularly to a kind of deadlock judgment method and devices.
Background technique
Advanced extensible Interface (AXI, Advanced eXtensible Interface) bus protocol is as a kind of high property The on-chip bus agreement of energy high bandwidth, is widely used, wherein AXI is total in system on chip (SOC, System-On-Chip) The transmission mechanism that line uses is read and write separation, address/control and data separating, therefore, AXI bus definition read address channel (AR, Read address channel) is read data channel (R, Read data channel), write address channel (AW, Write Address channel), write data channel (W, Write data channel), write response channel (B, Write response Channel) five independent transmission channels carry out data transmission；SOC system is made of multiple bus interconnection module-cascades, by In outstanding transmission and out-of-order transfer mode that the compatible AXI protocol of bus interconnection module is supported, so that a main equipment Can multiple address/control commands be initiated to obtain to multiple access rights from equipment, still, due to one in the channel AW simultaneously In a transmission cycle, one only allows from equipment and uniquely, has been assigned access right volume main equipment in W channel and carry out data friendship It changes, so that will increase the probability of bus deadlock in more main equipments and mostly from when carrying out data exchange between equipment.
In the prior art, AXI bus generates deadlock when data are transmitted in order to prevent, and bus interconnection module connects from equipment It is added on mouthful single effectively from equipment (SAS, Single Active Slave) mechanism, SAS mechanism regulation bus interconnection module Slave equipment interface only currently write the writing after data are all sent completely of transmission, could initiate to write transmission next time writes ground Location order, so as to avoid " when after once write transmission write address order reach the destination after, it is preceding once write transmission write data Still it is blocked in from equipment interface " the problem of.
However, using SAS mechanism, bus interconnection module can only be after once write and be transmitted, and just progress is next time Transmission is write, so that reducing the efficiency of data transmission while avoiding bus transfer deadlock.
Summary of the invention
In order to solve the above technical problems, an embodiment of the present invention is intended to provide a kind of deadlock judgment method and device, Neng Gou While avoiding bus transfer deadlock, the efficiency of improve data transfer.
The embodiment of the invention provides a kind of deadlock judgment methods, which comprises
The first transmission data are received, obtain the corresponding first object address of the first transmission data, and according to default road Diameter time delay table determines the first transmission data corresponding first default arrival time；
It, will be described when the described first default arrival time the second default arrival time corresponding less than the second transmission data Corresponding first transmission state of first transmission data is set as preferential state, and the second transmission data corresponding second are transmitted State is set as deferred mode, and the second transmission data are to be sent to the transmission data of the first object address；
According to second transmission state, the corresponding current transmission of transmission path from initial address to destination address is updated State, and according to the present transmission state and first transmission state, it is pre- to judge whether the first transmission data meet If dead lock condition；
When judging that the first transmission data meet default dead lock condition, transmission the first transmission data are prevented.
In the above scheme, described according to preset path time delay table, determine the first transmission data corresponding first Default arrival time, comprising:
Obtained from the preset path time delay table first corresponding first convergent point of transmission data monitored and First transmission delay；
According to first convergent point and first transmission delay, the first transmission data corresponding first are determined Default arrival time.
In the above scheme, it is described determine first transmission data corresponding first default arrival time after, institute It states before setting preferential state for corresponding first transmission state of the first transmission data, the method also includes:
The the second transmission data for being sent to the first object address are searched, and determine second transmission The data corresponding second default arrival time.
In the above scheme, the lookup is being sent to the second transmission data of the first object address, and Determine the second transmission data corresponding second default arrival time, comprising:
Obtain the current target address of the current transmission data monitored；
It is described the by the current transmission data record when the current target address is the first object address Two transmission data；
It monitors described second and transmits data to the second transmission delay up to the first object address, and described second is passed Defeated delay was recorded as the described second default arrival time.
In the above scheme, described according to first convergent point and first transmission delay, determine described first Transmit data corresponding first default arrival time, comprising:
The corresponding third transmission of third transmission data and third transmission data of the monitoring by first convergent point Delay；
When the first transmission delay is less than the third transmission delay, the described first default arrival time was recorded as described First transmission delay；
When first transmission delay is greater than the third transmission delay, the described first default arrival time was recorded as The sum of first transmission delay and preset time value.
In the above scheme, the first transmission data are the transmission data sent from the first initial address, described second Transmitting data is the transmission data sent from the second initial address, described according to second transmission state, is updated from starting point The corresponding present transmission state of the transmission path of location to destination address, comprising:
The second transmission data are corresponding from second initial address to the transmission shape of the first object address State is updated to deferred mode.
In the above scheme, described according to the present transmission state and first transmission state, judge described first Whether transmission data meet default dead lock condition, comprising:
Monitor corresponding first transmission path of the initial address and corresponding second transmission path of the destination address Transmission state；
When the transmission state of first transmission path includes a preferential state and a deferred mode, and second transmission When the transmission state in path includes a preferential state and a deferred mode, it is described default to judge that the first transmission data meet Dead lock condition；
When the transmission state of any of first transmission path and second transmission path transmission path does not include When one preferential state and a deferred mode, judge that the first transmission data are unsatisfactory for the default dead lock condition.
It in the above scheme, include at least one transmission channel between the initial address and the destination address, it is described The transmission state of corresponding first transmission path of the initial address and corresponding second transmission path of the destination address is monitored, Include:
When at least one described transmission channel is preferential state, the biography of the initial address and the destination address is judged Defeated state is preferential state；
When at least one described transmission channel is delay state, the biography of the starting start-stop and the destination address is judged Defeated state is delay state；
When not only having included preferential state at least one described transmission channel, but also when including deferred mode, judge described originate It is only preferential state or deferred mode with the transmission state of the destination address.
In the above scheme, after the prevention transmission described first passes data, the method also includes:
When it is default judge that the time reaches when, reacquisition first transmission state；
According to first transmission state reacquired and the present transmission state, judge that transmitting described first passes Whether transmission of data can generate bus deadlock.
The embodiment of the invention provides a kind of deadlock judgment means, the deadlock judgment means include:
Bus system；
The monitoring record module being connect with the bus system；
The multilevel iudge module being connect with the monitoring record module；
The blocking module being connect with the multilevel iudge module and the bus system；Wherein,
The bus system, for receiving the first transmission data by the corresponding coffret of the first initial address, and will The first transmission data are sent to the first destination address；
The monitoring record module obtains institute for receiving the first transmission data by monitoring the coffret The corresponding first object address of the first transmission data is stated, and according to preset path time delay table, determines first transmission Data corresponding first default arrival time；
The multilevel iudge module, for when the described first default arrival time is less than the second transmission data corresponding second When default arrival time, preferential state is set by corresponding first transmission state of the first transmission data, and by described second Corresponding second transmission state of transmission data is set as deferred mode, and the second transmission data are to be sent to first mesh Mark the transmission data of address；According to second transmission state, the transmission path updated from initial address to destination address is corresponding Present transmission state judge the first transmission data and according to the present transmission state and first transmission state Whether satisfaction presets dead lock condition；
The blocking module, for preventing transmission when judging that the first transmission data meet default dead lock condition The first transmission data.
In above-mentioned apparatus, the monitoring record module is specifically used for obtaining monitoring from the preset path time delay table Corresponding first convergent point of the first transmission data arrived and the first transmission delay；According to first convergent point and described One transmission delay determines the first transmission data corresponding first default arrival time.
In above-mentioned apparatus, the monitoring record module is also used to lookup and is being sent to the first object address The second transmission data, and determine the second transmission data corresponding second default arrival time.
In above-mentioned apparatus, the monitoring record module is current specifically for monitoring from coffret acquisition Transmit the current target address of data；When the current target address is the first object address, by the current transmission Data record is the second transmission data；Monitor described second transmit data to up to the first object address second transmission Delay, and second transmission delay was recorded as the described second default arrival time.
In above-mentioned apparatus, the monitoring record module, specifically for monitoring the third biography by first convergent point Transmission of data and the corresponding third transmission delay of third transmission data；Prolong when the first transmission delay is less than third transmission Constantly, the described first default arrival time was recorded as first transmission delay；Described in being greater than when first transmission delay When third transmission delay, the described first default arrival time was recorded as the sum of described first transmission delay and preset time value.
In above-mentioned apparatus, the first transmission data are the transmission data sent from the first initial address, described second Transmitting data is the transmission data sent from the second initial address,
The monitoring record module, be specifically used for will it is described second transmit data it is corresponding from second initial address to The transmission state of the first object address is updated to deferred mode.
In above-mentioned apparatus, the monitoring record module is also used to monitor the initial address corresponding first transmission road The transmission state of diameter and corresponding second transmission path of the destination address；
The multilevel iudge module, specifically for the transmission state when first transmission path include preferential state with One deferred mode, and the transmission state of second transmission path include a preferential state and a deferred mode when, judge institute It states the first transmission data and meets the default dead lock condition；When any in first transmission path and second transmission path When the transmission state of a transmission path does not include a preferential state and a deferred mode, judge that the first transmission data are discontented The foot default dead lock condition.
In above-mentioned apparatus, the multilevel iudge module is specifically used for sentencing when at least one transmission channel is preferential state The transmission state of the disconnected starting start-stop described out and the destination address is preferential state；When at least one described transmission channel is delay When state, judge that the transmission state of the starting start-stop and the destination address is delay state；When at least one described transmission is logical Not only included preferential state in road, but also when including deferred mode, and had judged that the transmission state of the starting start-stop and the destination address was Preferential state or deferred mode.
In above-mentioned apparatus, the deadlock judgment means further include: loop module；
The loop module, for when it is default judge that the time reaches when, first transmission state is reacquired, according to heavy First transmission state newly got and the present transmission state judge to transmit whether the first transmission data can produce Raw bus deadlock.
The embodiment of the invention provides a kind of computer readable storage mediums, are stored thereon with computer program, are applied to In deadlock judgment means, which is characterized in that the computer program realizes above-mentioned deadlock judgment method when being executed by processor.
The embodiment of the invention provides a kind of deadlock judgment method and devices, can avoid the same of bus transfer deadlock When, the efficiency of improve data transfer, this method may include: to receive the first transmission data, and it is corresponding to obtain the first transmission data First object address, and according to preset path time delay table, determine the first transmission data corresponding first default arrival time；When It is when first default arrival time is less than second transmission data corresponding second default arrival time, the first transmission data are corresponding First transmission state is set as preferential state, and sets deferred mode for corresponding second transmission state of the second transmission data, and second Transmitting data is to be sent to the transmission data of first object address；According to the second transmission state, update from initial address to The corresponding present transmission state of the transmission path of destination address, and according to present transmission state and the first transmission state, judge Whether one transmission data meet default dead lock condition；When judging that the first transmission data meet default dead lock condition, prevent to pass Defeated first transmission data.Using the above method, deadlock judgment means obtain the first transmission number when receiving the first transmission data According to corresponding first destination address, when determining that the first transmission data corresponding first preset arrival according to preset path time delay table Between, deadlock judgment means by the first arrival time and be sent to the first destination address second transmission data corresponding second Arrival time is compared, and obtains the first transmission state and the second transmission state, according to the second transmission state, updates from starting point The corresponding present transmission state of the transmission path of location to destination address, and judged according to present transmission state and the first transmission state Whether transmission the first transmission data generate bus deadlock, can be normal when data are transmitted in judgement first will not generate bus deadlock Transmission the first transmission data, without just transmitting next record data after waiting previous data to be transmitted, so that avoiding While bus transfer deadlock, the efficiency of improve data transfer.
174706-I-CP-ZXIC
Detailed description of the invention
Fig. 1 is that deadlock forms schematic diagram；
Fig. 2 is the Circular dependency figure that deadlock is formed；
Fig. 3 is a kind of flow chart one of deadlock judgment method provided in an embodiment of the present invention；
Fig. 4 is a kind of module diagram of illustrative deadlock judgment means provided in an embodiment of the present invention；
Fig. 5 is a kind of schematic diagram of illustrative bus interconnection architecture provided in an embodiment of the present invention；
Fig. 6 is a kind of illustrative transmission datacycle dependency graph provided in an embodiment of the present invention；
Fig. 7 is a kind of signal of illustrative the first transmission of obstructive root canal center obstruction data provided in an embodiment of the present invention Figure；
Fig. 8 is a kind of matrix schematic diagram of illustrative DMOT provided in an embodiment of the present invention；
Fig. 9 is provided in an embodiment of the present invention a kind of illustratively from the solution flow chart blocked when occurring；
Figure 10 is a kind of flowchart 2 of deadlock judgment method provided in an embodiment of the present invention；
Figure 11 is a kind of structural schematic diagram one of deadlock judgment means provided in an embodiment of the present invention；
Figure 12 is a kind of structural schematic diagram two of deadlock judgment means provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description.
In the prior art, as shown in Figure 1, main equipment 0 and main equipment 1 by a bus interconnection module with from equipment 0 and Data exchange is carried out from equipment 1, wherein the slave equipment interface 0 in bus interconnection module is attached with main equipment 0, and bus is mutual Slave equipment interface 1 in gang mould block is attached with main equipment 1, the host device interface 0 in bus interconnection module with from equipment 0 into Row connects, and the host device interface 1 in bus interconnection module is attached with from equipment 1, in bus interconnection inside modules, from equipment Interface 0 and it can carry out data transmission respectively with host device interface 0 and host device interface 1 from equipment interface 1.At the T0 moment, master Equipment 0 to successively and continuously having issued two write address orders of AW01 and AW00 from equipment 1 and from equipment 0, meanwhile, main equipment 1 To successively and continuously having issued two write address orders of AW10 and AW11 from equipment 0 and from equipment 1；Due to from equipment interface 0 with Path delay between host device interface 0 is less than the path delay between equipment interface 1 and host device interface 0, therefore, after AW00 Hair first extremely, is arrived at prior to AW10 from equipment 0, and obtains the access right to it, at this point, host device interface 0 opens W channel, is waited Write data command W00；Similarly, since the path delay between equipment interface 1 and host device interface 1 is less than from equipment interface 0 It with the path delay between host device interface 1, sends out first after AW11 extremely, first reaches with AW01 from equipment 1, and obtain the access to it Power waits data command W11 to be written at this point, host device interface 1 opens W channel；Because W00 is later than W01 in time sequencing, W00 has to wait for W01 and is sent just be sent to host device interface 0；And at this point, since AW11 is occupied to from equipment 1 Access right, W01 can only wait W11 to be sent, and can just be sent to host device interface 1；Similarly, because in time sequencing, W11 It is later than W10, W11 has to wait for W10 and be sent just be sent to host device interface 1；And at this point, since AW00 is still occupied pair From the access right (W00 is constantly in wait state) of equipment 0, W10 can only wait W00 to be sent and can just be sent to main equipment and connect Mouth 0.Then, it forms circulation as shown in Figure 2 and waits situation, bus transfer falls into deadlock.
Embodiment one
The embodiment of the present invention provides a kind of deadlock judgment method, as shown in figure 3, this method may include:
S101, the first transmission data are received, obtains the corresponding first object address of the first transmission data, and according to default road Diameter time delay table determines the first transmission data corresponding first default arrival time.
A kind of deadlock judgment method provided in an embodiment of the present invention be suitable for multiple main equipments and it is multiple between equipment lead to Under the scene for crossing outstanding transmission to carry out data transmission.
In the embodiment of the present invention, as shown in figure 4, deadlock judgment means include the coffret of bus interconnection module, monitoring Logging modle, multilevel iudge module and blocking module, monitoring record module monitor the transmission in bus interconnection modular system in real time Interface, when monitoring record module receives the first transmission data by coffret, monitoring record module obtains the first transmission First transmission address of data, monitoring record module obtain corresponding first starting of the first transmission data according to the first transmission address Address and first object address, later, monitoring record module determine that the first transmission data are corresponding according to preset path time delay table The first default arrival time.
In the embodiment of the present invention, when designing system on chip (SOC, System-On-Chip), designer's meeting basis is set Meter needs that at least one register slice is arranged on coffret and transmission path, and is numbered to each register slice, Designer determines to participate in the main equipment of data exchange and close from the access between equipment according to the number of these register slices System, path structure and the static time delay transmitted on path, and tied according to main equipment and from the access relation between equipment, path Structure and the static time delay transmitted on path create preset path time delay table.
Illustratively, as shown in figure 5, slave equipment interface 00 and main equipment 0 in bus interconnection module 0 connect, bus is mutual Slave equipment interface 01 and main equipment 1 in gang mould block 0 connect, and the host device interface 00 in bus interconnection module 0 connects with from equipment 0 It connects, the slave equipment interface 10 in the host device interface 01 and bus interconnection module 1 in bus bar module 0 connects, bus bar Slave equipment interface 00 in module 0 is connect with host device interface 00 and host device interface 01, the slave equipment in bus bar module 0 Interface 01 is connect with host device interface 00 and host device interface 01；Slave equipment interface 11 and main equipment 2 in bus interconnection module 1 It connects, the host device interface 10 in bus interconnection module 1 is connect with from equipment 1, the host device interface 11 in bus interconnection module 1 It is connect with from equipment 2, the slave equipment interface 10 and host device interface 10 in bus interconnection module 1 connect, in bus interconnection module 1 Slave equipment interface 11 connect with host device interface 10 and host device interface 11；And for from equipment interface 00, host device interface 00, Host device interface 01, from equipment interface 10, host device interface 10, the access between equipment interface 00 and host device interface 01, Register slice 0, register slice 1, register slice 2, register slice 3, deposit are sequentially allocated from equipment interface 11, host device interface 11 Device piece 4, register slice 5, register slice 6, register slice 7, then, the corresponding preset path time delay table of the SOC system of Fig. 5 are table One, wherein storing from main equipment to the corresponding Delay of All Paths from equipment, which may include from master Equipment is extremely from the time delay of equipment, from main equipment to the time delay coordinate from equipment and from main equipment to the time delay of convergent point.
One preset path time delay table of table
In the embodiment of the present invention, after monitoring record module gets the first transmission address of the first transmission data, monitoring Logging modle searches the first convergent point and the first transmission delay of the first transmission data, later, prison from preset path time delay table It surveys logging modle and obtains the third transmission data for passing through the first convergent point, and determine that the corresponding third transmission of third transmission data is prolonged When, the first transmission delay and third transmission delay are compared by monitoring record module, when the first transmission delay is passed less than third When defeated delay, the first default arrival time was denoted as the first transmission delay by monitoring record module；When the first transmission delay is greater than the When three transmission delays, the first default arrival time was denoted as the sum of the first transmission delay and preset time value by monitoring record module.
In the embodiment of the present invention, AW order in bus interconnection system is not yet reached purpose from equipment by deadlock judgment means The information of all transmission data is stored in dynamic routing table, and dynamic routing table specifically stores: transmission ID number, initial address, mesh Mark address, in transmission path without register slice number.
In the embodiment of the present invention, after monitoring record module monitors to a certain transmission data pass through a register slice, Deadlock judgment means search the information of the transmission data from dynamic routing table, and the register slice of process is numbered and is deleted, when When monitoring record module monitors are transmitted to a certain transmission data, monitoring record module is by the transmission data from dynamic routing table Middle deletion.
In the embodiment of the present invention, monitoring record module obtains third from dynamic routing table and transmits data to up to the first convergence The third transmission delay of point.
Illustratively, as shown in figure 5, AW11 is transmitted from equipment interface 01 between host device interface 01, main equipment 2 to AW20 is sent from equipment interface 11, at this point, the delay that AW20 reaches host device interface 10 is 1, and AW11 reaches host device interface 10 delay can reach convergent point host device interface 10 earlier than AW11 for 2, AW20, therefore, the time delay for being AW11 increases by one very big T.
In the embodiment of the present invention, when monitoring record module determines the first transmission data corresponding first default arrival time Later, the first transmission data are added in dynamic routing table by deadlock judgment means.
S102, when the first default arrival time is less than second transmission data corresponding second default arrival time, by the Corresponding first transmission state of one transmission data is set as preferential state, and corresponding second transmission state of the second transmission data is set It is set to deferred mode, the second transmission data are to be sent to the transmission data of first object address.
After deadlock judgment means determine the first transmission data corresponding first default arrival time, deadlock judgement dress The first default arrival time and second transmission data corresponding second default arrival time will be compared by setting, and according to than Compared with as a result, the first transmission data of setting and the corresponding transmission state of the second transmission data.
In the embodiment of the present invention, after monitoring record module gets the first transmission address of the first transmission data, monitoring Logging modle determines the corresponding first object address of the first transmission data according to the first transmission address, and monitoring record module is from dynamically The second transmission data that current target address is first object address are searched in routing table, and it is corresponding to search the second transmission data Without register number, monitoring record module by the second transmission data it is corresponding without register number be determined as the Two default arrival times.
In the embodiment of the present invention, multilevel iudge module compares the first default arrival time and the second default arrival time Compared with when the first default arrival time is less than the second default arrival time, multilevel iudge module is corresponding by the first transmission data First transmission state is set as preferential state, and sets deferred mode for corresponding second transmission state of the second transmission data；When When one default arrival time was greater than for the second default arrival time, the first transmission state is set deferred mode by multilevel iudge module, And by the second transmission state equipment be preferential state.
Further, when monitoring record module does not find the second transmission data in dynamic routing table, compare and sentence The first transmission state is set normal state by disconnected module.
S103, according to the second transmission state, update that the transmission path from initial address to destination address is corresponding to work as forward pass Defeated state, and according to present transmission state and the first transmission state, judge whether the first transmission data meet default dead lock condition.
When deadlock judgment means get corresponding first transmission state of the first transmission data and the second transmission data correspondence The second transmission state when, deadlock judgment means will be updated from initial address to destination address according to the second transmission state The corresponding present transmission state of transmission path, and according to present transmission state and the first transmission state, judge the first transmission data Whether satisfaction presets dead lock condition.
In the embodiment of the present invention, the transmission path pair from initial address to destination address is stored in historic transmission state table The transmission state answered, when the second transmission state of the first transmission state for getting the first transmission data and the second transmission data When, for multilevel iudge module by historic transmission state table, the first transmission data are corresponding from the first initial address to first object The transmission state of address is set as preferential state；By in historic transmission state table, the second transmission data are corresponding from the second starting point The transmission state of location to first object address is updated to deferred mode.
In the embodiment of the present invention, multilevel iudge module judges whether bus deadlock can be generated when transmission the first transmission data There are three decision conditions, these three decision conditions must all meet Shi Caineng and judge to generate when transmission the first transmission data Deadlock, these three decision conditions include:
1, topology connectivity condition: 4x4 dynamic connectivity matrix as shown in Table 2, the matrix are used to indicate a period of time in office Carve main equipment and from the write operation relationship between equipment.If main equipment i sends write address order AW to from equipment jij, then Entry (i, j) is labeled as 1；Otherwise, it is labeled as 0.
Two dynamic connectivity matrix of table
From equipment 0 From equipment 1 From equipment 2 From equipment 3
Main equipment 0 0 1 0 1
Main equipment 1 1 0 1 0
Main equipment 2 1 0 0 1
Main equipment 3 0 1 1 0
It is not difficult to derive from the Forming Mechanism of Circular dependency:
The necessary condition 1 of bus deadlock: in connectivity matrix, each column (from equipment) and every a line (main equipment) must have Two or more entry are 1；
If the corresponding Circular dependency relationship of table two is as shown in Figure 6, bus deadlock will result in.Wherein WijIndicate that master sets For i and data are write between equipment j.
2, path static state time delay condition: the root cause problems of forward direction deadlock be two (or more than two) main equipments with It is same when carry out writing data exchange from equipment, the AW order of some main equipment " rear hair and first to ".So different masters set It is standby to the difference for certainly existing static time delay on a path AW from equipment；If static time delay is identical, after hair is certain afterwards extremely, It not will form deadlock.
The necessary condition 2 of forward direction deadlock: at least having one from equipment, and has two or two of connectivity relationship therewith Static delay between above main equipment in the channel AW has differences.
That is Dij≠Dkj, wherein DijIndicate main equipment i and the static state delay from equipment j in the channel AW.
3, accessing time sequence condition: the formation of Circular dependency relationship needs main equipment to meet on writing data behavior below Condition:
The necessary condition 3 of forward direction deadlock: there are two or more main equipments to write data characteristics with below: i.e. One main equipment successively sends the order of AW write address from equipment to two, and the AW order of later transmission can be set prior to others master Allowance reaches purpose from equipment.
By taking Circular dependency relationship shown in fig. 6 as an example, if ΤιjIndicate that main equipment i writes sending AW when writing data from equipment j At the time of address command, DijIndicate main equipment i and the static state delay from equipment j in the channel AW, then to each master of deadlock before being formed Equipment accessing time sequence must meet following formula:
T10>T12
T12+D12<T32+D32
T20>T23
T20+D20<T10+D10
T03>T01
T03+D03<T23+D23
T31>T32
In the embodiment of the present invention, deadlock judgment means generate default deadlock item according to three necessary conditions that deadlock is formed Part, multilevel iudge module pass through corresponding first transmission path of initial address and destination address pair in monitoring historic transmission state table The transmission state for the second transmission path answered；When the transmission state of the first transmission path includes a preferential state and a delay State, and the transmission state of the second transmission path include a preferential state and a deferred mode when, characterization meet deadlock formed three A necessary condition；When the transmission state of any of the first transmission path and the second transmission path transmission path does not include one excellent When first state and a deferred mode, characterization is unsatisfactory for three necessary conditions of deadlock formation.
In the embodiment of the present invention, at the beginning of the design of bus interconnection system, different numbers are distributed for each initial address Transmission channel, an initial address can send transmission data to multiple destination addresses simultaneously, therefore, initial address and destination address Between include at least one transmission channel, when at least one transmission channel be preferential state when, deadlock judgment means setting originates It is only preferential state with the transmission state of destination address；When at least one transmission channel is delay state, the setting of deadlock judgment means The transmission state for originating start-stop and destination address is delay state；When at least one transmission channel not only include preferential state, but also including When deferred mode, the transmission state of deadlock judgment means setting starting start-stop and destination address is preferential state or deferred mode.
S104, when judging that the first transmission data meet default dead lock condition, prevent transmission the first transmission data.
When deadlock judgment means, which judge that the first transmission data are full, then presets dead lock condition, deadlock judgment means tissue is passed The process of defeated first transmission data.
In the embodiment of the present invention, bus deadlock can be generated when multilevel iudge module judges transmission the first transmission data in advance When, blocking module prevents transmission the first transmission data.
In the embodiment of the present invention, blocking module controls the register slice in the first initial address, forbids and the first transmission number According to the handshake procedure for carrying out AW and W.
Illustratively, as shown in fig. 7, obstructive root canal center is attached with each coffret and register slice, resistance Plug control centre forbids shaking hands with the first transmission data by controlling register slice, to prevent the transmission of the first transmission data Process.
In the embodiment of the present invention, after blocking module prevents transmission the first transmission data, deadlock judgment means wait pre- If judging the arrival of time, when it is default judge that the time reaches when, deadlock the first transmission state of reacquisition, by what is reacquired First transmission state is updated in historic transmission state table, and the historic transmission state table based on update, judges that transmission first passes Whether transmission of data can generate bus deadlock.
In the embodiment of the present invention, historic transmission state table can be deadlock relational matrix (DMOT, Deadlock Matrix With Outstanding Transactions), selection performance is specifically carried out according to the actual situation, and the embodiment of the present invention is not Do specific restriction.
In the embodiment of the present invention, as shown in figure 8, DMOT is a three-dimensional matrix, three dimensions are respectively DMOT structure Initial address, destination address and the corresponding transmission channel of initial address, when deadlock judgment means determine initial address 1 to target When the transmission state of address 1 is preferential state, deadlock judgment means set corresponding position initial address 1 and destination address 1 simultaneously It is set to 1；When deadlock judgment means determine initial address 1 to destination address 1 transmission state for delay state when, deadlock judgement dress It sets and sets -1 in corresponding position simultaneously for initial address 1 and destination address 1, what is be made of n main equipment and m from equipment In DMOT, if the bivector of i-th row jth p-th of pilot trench of column is denoted as (X0(i,j,p),X1(i, j, p)), P indicates all P= {x(i,j,p)∈CMOT|X0(i, j, p)=1 } P={ x(i,j,p)∈CMOT|X0(i, j, p)=1 } at least exist a l rank submatrix (l≤rank (ICM), if indicating P={ x with P(i,j,p)∈ CMOT | } when DMOT matrix meets following two condition, characterization First transmission data will cause bus deadlock.
1, the first train value of two-dimensional coordinate recorded in the pilot trench for including at least one entry of every row is 1, and extremely The first train value of two-dimensional coordinate of rare slot is -1；
2, there are l two-dimensional coordinate, recorded in the value of secondary series of two-dimensional coordinate be located at and do not go together and different lines Entry each column at least one entry value be 1 and at least one entry value is -1.
In the embodiment of the present invention, when bus interconnection modular matrix parameter device is unreasonable (such as initial address Outstanding depth is greater than the Outstanding depth in path), then it is likely to occur in AW order transmission process, without competing It strives access and path blockade is in the presence of.Once such case occurs, then can destroy sequential relationship in dynamic routing table and Sequence is estimated in destination queue table, forming deadlock may.For such situation, the present invention proposes emergency mechanism below, Deadlock risk is avoided, as shown in figure 9, when occurring from obstruction, judges to whether there is in dynamic routing table and to be blocked AW same Initial address but different destination addresses, and entry time is later than other AW orders for being blocked AW, when it is present, blocks the master and sets Standby later AW order enters；When it be not present, block other AW orders for being sent to the slave equipment from the obstruction destination AW.
It is corresponded to it is understood that deadlock judgment means when receiving the first transmission data, obtain the first transmission data The first destination address, the first transmission data corresponding first default arrival time, deadlock are determined according to preset path time delay table Judgment means by the first arrival time and be sent to the first destination address second transmission data it is corresponding second reach when Between be compared, obtain the first transmission state and the second transmission state, according to the second transmission state, update from initial address to mesh The corresponding present transmission state of transmission path of address is marked, and according to present transmission state and the first transmission state judgement transmission the Whether one transmission data generate bus deadlock, can when data are transmitted in judgement first will not generate bus deadlock normal transmission the One transmission data, without just transmitting next record data after waiting previous data to be transmitted, so that avoiding bus from passing While defeated deadlock, the efficiency of improve data transfer.
Embodiment two
The embodiment of the present invention provides a kind of deadlock judgment method, and as shown in Figure 10, this method may include:
S201, deadlock judgment means receive the first transmission data, obtain the corresponding first object address of the first transmission data, Corresponding first convergent point of the first transmission data and the first transmission delay monitored is obtained from preset path time delay table.
It should be noted that the realization process of step S201 is identical as the realization process of step S101, referring particularly to step The explanation of S101, the embodiment of the present invention repeat no more.
The third transmission data and third transmission data of S202, the monitoring of deadlock judgment means by the first convergent point are corresponding Third transmission delay.
When deadlock judgment means determine corresponding first convergent point of the first transmission data and the first transmission delay, deadlock Judgment means, which will be monitored, transmits data and the corresponding third transmission delay of third transmission data by the third of the first convergent point ?.
In the embodiment of the present invention, monitoring record module, which is obtained, transmits data by the third of the first convergent point, and determines the The corresponding third transmission delay of three transmission data.
In the embodiment of the present invention, AW order in bus interconnection system is not yet reached purpose from equipment by deadlock judgment means The information of all transmission data is stored in dynamic routing table, and dynamic routing table specifically stores: transmission ID number, initial address, mesh Mark address, in transmission path without register slice number.
In the embodiment of the present invention, after monitoring record module monitors to a certain transmission data pass through a register slice, Deadlock judgment means search the information of the transmission data from dynamic routing table, and the register slice of process is numbered and is deleted, when When monitoring record module monitors are transmitted to a certain transmission data, monitoring record module is by the transmission data from dynamic routing table Middle deletion.
In the embodiment of the present invention, monitoring record module obtains third from dynamic routing table and transmits data to up to the first convergence The third transmission delay of point.
Illustratively, as shown in figure 5, AW11 is transmitted from equipment interface 01 between host device interface 01, main equipment 2 to AW20 is sent from equipment interface 11, at this point, the delay that AW20 reaches host device interface 10 is 1, and AW11 reaches host device interface 10 delay can reach convergent point host device interface 10 earlier than AW11 for 2, AW20, therefore, the time delay for being AW11 increases by one very big T.
S203, when the first transmission delay is less than third transmission delay, deadlock judgment means are by the first default arrival time It is recorded as the first transmission delay.
After deadlock judgment means determine third transmission delay, deadlock judgment means will judge the first transmission delay Size between third transmission delay, when the first transmission delay is less than third transmission delay, deadlock judgment means record First default arrival time was the first transmission delay.
In the embodiment of the present invention, the first transmission delay and third transmission delay are compared by monitoring record module, when When one transmission delay is less than third transmission delay, the first default arrival time was denoted as the first transmission delay by monitoring record module.
S204, when the first transmission delay is greater than third transmission delay, deadlock judgment means are by the first default arrival time It is recorded as the sum of the first transmission delay and preset time value.
When deadlock judgment means judge that the first transmission delay is greater than third transmission delay, deadlock judgment means are by first If arrival time is recorded as the sum of the first transmission delay and preset time value.
In the embodiment of the present invention, the first transmission delay and third transmission delay are compared by monitoring record module, when One transmission delay be greater than third transmission delay when, monitoring record module by the first default arrival time be denoted as the first transmission delay with The sum of preset time value.
In the embodiment of the present invention, when monitoring record module determines the first transmission data corresponding first default arrival time Later, the first transmission data are added in dynamic routing table by deadlock judgment means.
Step S203 and step S204 be step S202 after two steps arranged side by side, specifically according to the actual situation into Row selection, the embodiment of the present invention do not do specific restriction.
S205, deadlock judgment means obtain the current target address of the current transmission data monitored.
After deadlock judgment means determine the first transmission data corresponding first default arrival time, deadlock judgment means The the second transmission data for being sent to first object address will be searched, firstly, deadlock judgment means obtain current transmission The current target address of data.
In the embodiment of the present invention, monitoring record module obtains working as the current transmission data monitored from dynamic routing table Preceding destination address.
S206, when current target address be first object address when, current transmission data record is by deadlock judgment means Second transmission data.
After deadlock judgment means obtain the current target address of current transmission data, deadlock judgment means will judge to work as Whether preceding destination address is first object address, and when current target address is first object address, deadlock judgment means will Current transmission data record is the second transmission data.
In the embodiment of the present invention, when deadlock judgment means judge that current target address is first object address, deadlock Current transmission data record is the second transmission data by judgment means.
S207, deadlock judgment means monitoring second transmit data to the second transmission delay up to first object address, and will Second transmission delay was recorded as the second default arrival time.
After deadlock judgment means determine the second transmission data, deadlock judgment means will determine the second transmission number According to corresponding second default arrival time, specifically, deadlock judgment means monitoring second is transmitted data to up to first object Second transmission delay of location, and the second transmission delay was recorded as the second default arrival time.
In the embodiment of the present invention, monitoring record module searched from dynamic routing table second transmission data it is corresponding without Register number, monitoring record module by the second transmission data it is corresponding without register number be recorded as second and preset Arrival time.
S208, when the first default arrival time is less than the second default arrival time, deadlock judgment means by first transmission Corresponding first transmission state of data is set as preferential state, and corresponding second transmission state of the second transmission data is set as prolonging Slow state.
After deadlock judgment means determine the first default arrival time and the second default arrival time, deadlock judgement dress The first default arrival time and the second default arrival time will be compared by setting, when the first default arrival time is less than When two default arrival times, corresponding first transmission state of the first transmission data is set preferential state by deadlock judgment means, and Deferred mode is set by corresponding second transmission state of the second transmission data.
In the embodiment of the present invention, multilevel iudge module compares the first default arrival time and the second default arrival time Compared with when the first default arrival time is less than the second default arrival time, multilevel iudge module is corresponding by the first transmission data First transmission state is set as preferential state, and sets deferred mode for corresponding second transmission state of the second transmission data；When When one default arrival time was greater than for the second default arrival time, the first transmission state is set deferred mode by multilevel iudge module, And by the second transmission state equipment be preferential state.
Further, when monitoring record module does not find the second transmission data in dynamic routing table, compare and sentence The first transmission state is set normal state by disconnected module.
S209, deadlock judgment means are corresponding from the second initial address to the biography of first object address by the second transmission data Defeated state is updated to deferred mode.
After the second transmission state is set deferred mode by deadlock judgment means, deadlock judgment means will be passed second The transmission state of corresponding second initial address of transmission of data and first object address is set as deferred mode.
In the embodiment of the present invention, initial address and the corresponding transmission shape of initial address are stored in historic transmission state table State, destination address and the corresponding transmission state of destination address compare when getting the second transmission state of the second transmission data For judgment module by historic transmission state table, second transmits the transmission of data corresponding second initial address and first object address State is updated to deferred mode.
Further, when getting the first transmission state of the first transmission data, multilevel iudge module is by historic transmission In state table, the transmission state of corresponding first initial address of the first transmission data and first object address is set as preferential state.
S210, corresponding first transmission path of deadlock judgment means monitoring initial address and destination address corresponding second pass The transmission state in defeated path.
When deadlock judgment means are corresponding from the second initial address to the transmission of first object address by the second transmission data State is updated to after deferred mode, and deadlock judgment means will judge the first biography according to the first transmission state and present transmission state Whether transmission of data will cause bus deadlock, firstly, deadlock judgment means determine corresponding first transmission path of initial address and The transmission state of corresponding second transmission path of destination address.
In the embodiment of the present invention, at the beginning of the design of bus interconnection system, different numbers are distributed for each initial address Transmission channel, an initial address can send transmission data to multiple destination addresses simultaneously, therefore, initial address and destination address Between include at least one transmission channel, when at least one transmission channel be preferential state when, deadlock judgment means setting originates It is only preferential state with the transmission state of destination address；When at least one transmission channel is delay state, the setting of deadlock judgment means The transmission state for originating start-stop and destination address is delay state；When at least one transmission channel not only include preferential state, but also including When deferred mode, the transmission state of deadlock judgment means setting starting start-stop and destination address is preferential state or deferred mode.
S211, when the transmission state of any of the first transmission path and the second transmission path transmission path do not include at least When one preferential state and at least one deferred mode, deadlock judgment means judge that the first transmission data are unsatisfactory for default deadlock item Part.
After deadlock judgment means determine the transmission state of initial address and destination address, deadlock judgment means will be sentenced The transmission state of disconnected corresponding first transmission path of initial address and the transmission state of corresponding second transmission path of destination address It whether include at least one preferential state and at least one deferred mode, when any of the first transmission path and the second transmission path When the transmission state of transmission path does not include a preferential state and a deferred mode, deadlock judgment means judge the first transmission number According to being unsatisfactory for default dead lock condition.
In the embodiment of the present invention, when multilevel iudge module judges any of the first transmission path and the second transmission path When the transmission state of transmission path does not include at least one preferential state and at least one deferred mode, the first transmission path of characterization is discontented Three necessary conditions that deadlock described in sufficient step S104 is formed.
In the embodiment of the present invention, historic transmission state table can be DMOT structure, specifically be selected according to the actual situation Performance is selected, the embodiment of the present invention does not do specific restriction.
In the embodiment of the present invention, the description of DMOT structure is no longer superfluous herein as consistent to the description of Fig. 8 in step S104 It states.
S212, when the first transmission path transmission state include a preferential state and a deferred mode, and second transmit road When the transmission state of diameter includes a preferential state and a deferred mode, it is pre- that deadlock judgment means judge that the first transmission data meet If dead lock condition.
When the transmission state of the first transmission path includes a preferential state and a deferred mode, and the biography of the second transmission path When defeated state includes a preferential state and a deferred mode, deadlock judgment means judge that the first transmission data meet default deadlock Condition.
In the embodiment of the present invention, the transmission state and destination address pair of corresponding first transmission path of initial address are judged Whether the transmission state for the second transmission path answered includes at least one preferential state and at least one deferred mode, when initial address pair The transmission state for the first transmission path answered includes a preferential state and a deferred mode, and destination address corresponding second is transmitted When the transmission state in path includes a preferential state and a deferred mode, deadlock judgment means judge that the first transmission data meet Default dead lock condition.
In the embodiment of the present invention, when multilevel iudge module judges that the transmission state of the first transmission path includes one preferential State and a deferred mode, and the transmission state of the second transmission path include a preferential state and a deferred mode when, characterize first Transmission path meets three necessary conditions of the formation of deadlock described in step S104.
S213, when the first transmission data meet default dead lock condition, deadlock judgment means prevent transmission the first transmission number According to.
After deadlock judgment means judge that the first transmission data meet default dead lock condition, the anticipation of deadlock judgment means Bus deadlock can be generated when disconnected the first transmission of transmission out data, at this point, deadlock judgment means prevent transmission first from transmitting data.
In the embodiment of the present invention, in the embodiment of the present invention, blocking module controls the register slice in the first initial address, prohibits The handshake procedure of AW and W is only carried out with the first transmission data.
Illustratively, as shown in fig. 7, obstructive root canal center is attached with each coffret and register slice, resistance Plug control centre forbids shaking hands with the first transmission data by controlling register slice, to prevent the transmission of the first transmission data Process.
In the embodiment of the present invention, when bus interconnection modular matrix parameter device is unreasonable (such as initial address Outstanding depth is greater than the Outstanding depth in path), then it is likely to occur in AW order transmission process, without competing It strives access and path blockade is in the presence of.Once such case occurs, then can destroy sequential relationship in dynamic routing table and Sequence is estimated in destination queue table, forming deadlock may.For such situation, the present invention proposes emergency mechanism below, Deadlock risk is avoided, as shown in figure 9, when occurring from obstruction, judges to whether there is in dynamic routing table and to be blocked AW same Initial address but different destination addresses, and entry time is later than other AW orders for being blocked AW, when it is present, blocks the master and sets Standby later AW order enters；When it be not present, block other AW orders for being sent to the slave equipment from the obstruction destination AW.
S214, when it is default judge that the time reaches when, deadlock judgment means the first transmission state of reacquisition.
After deadlock judgment means prevent transmission the first transmission data, deadlock judgment means, which wait presetting, judges that the time arrives Up to when, rejudge transmission first transmission data whether can generate bus deadlock.
In the embodiment of the present invention, after blocking module prevents transmission the first transmission data, deadlock judgment means wait pre- If judging the arrival of time, when it is default judge that the time reaches when, deadlock the first transmission state of reacquisition.
S215, deadlock judgment means judge to transmit according to the first transmission state and present transmission state that reacquire Whether the first transmission data can generate bus deadlock.
When deadlock judgment means are reacquired to the first transmission state after, deadlock judgment means are according to reacquiring First transmission state and present transmission state, judge whether transmission the first transmission data can generate bus deadlock.
In the embodiment of the present invention, the first transmission state reacquired is updated to historic transmission shape by deadlock judgment means Historic transmission state table in state table, and based on update, judges whether transmission the first transmission data can generate bus deadlock.
Step S212- step S215 and step S211 are two steps arranged side by side after step S210, specific basis Actual conditions carry out selection execution, and the embodiment of the present invention does not do specific restriction.
It is corresponded to it is understood that deadlock judgment means when receiving the first transmission data, obtain the first transmission data The first destination address, the first transmission data corresponding first default arrival time, deadlock are determined according to preset path time delay table Judgment means by the first arrival time and be sent to the first destination address second transmission data it is corresponding second reach when Between be compared, obtain the first transmission state and the second transmission state, according to the second transmission state, update from initial address to mesh The corresponding present transmission state of transmission path of address is marked, and according to present transmission state and the first transmission state judgement transmission the Whether one transmission data generate bus deadlock, can when data are transmitted in judgement first will not generate bus deadlock normal transmission the One transmission data, without just transmitting next record data after waiting previous data to be transmitted, so that avoiding bus from passing While defeated deadlock, the efficiency of improve data transfer.
Embodiment three
The embodiment of the present invention provides a kind of deadlock judgment means, and as shown in figure 11, which may include:
Bus system 10；
The monitoring record module 11 being connect with the bus system 10；
The multilevel iudge module 12 being connect with the monitoring record module 11；
The blocking module 13 being connect with the multilevel iudge module 12 and the bus system 10；Wherein,
The bus system 10, for receiving the first transmission data by the corresponding coffret of the first initial address, and The first transmission data are sent to the first destination address.
The monitoring record module 11 is obtained for receiving the first transmission data by monitoring the coffret 10 The corresponding first object address of the first transmission data is taken, and according to preset path time delay table, determines described first Transmit data corresponding first default arrival time.
The multilevel iudge module 12, for when the described first default arrival time is less than the second transmission data corresponding the When two default arrival times, preferential state is set by corresponding first transmission state of the first transmission data, and by described the Corresponding second transmission state of two transmission data is set as deferred mode, and the second transmission data are to be sent to described first The transmission data of destination address；According to second transmission state, the transmission path pair from initial address to destination address is updated The present transmission state answered, and according to the present transmission state and first transmission state, judge the first transmission number According to whether meeting default dead lock condition.
The blocking module 13, for preventing to pass when judging that the first transmission data meet default dead lock condition The defeated first transmission data.
Optionally, the monitoring record module 11 is monitored specifically for obtaining from the preset path time delay table Described first transmits corresponding first convergent point of data and the first transmission delay；It is passed according to first convergent point and described first The first transmission data corresponding first default arrival time is determined in defeated delay.
Optionally, the monitoring record module 11 is also used to lookup and is being sent to the described of the first object address Second transmission data, and determine the second transmission data corresponding second default arrival time.
Optionally, the monitoring record module 11, specifically for obtaining the current transmission monitored from the coffret The current target address of data；When the current target address is the first object address, by the current transmission data It is recorded as the second transmission data；The second transmission that described second transmits data to up to the first object address is monitored to prolong When, and second transmission delay was recorded as the described second default arrival time.
Optionally, the monitoring record module 11, specifically for monitoring the third transmission number by first convergent point According to and the corresponding third transmission delay of third transmission data；When the first transmission delay is less than the third transmission delay, Described first default arrival time was recorded as first transmission delay；When first transmission delay is passed greater than the third When defeated delay, the described first default arrival time was recorded as the sum of described first transmission delay and preset time value.
Optionally, the first transmission data are the transmission data sent from the first initial address, the second transmission number According to the transmission data to send from the second initial address, the monitoring record module 11 is specifically used for the second transmission number Deferred mode is updated to from second initial address to the transmission state of the first object address according to corresponding.
Optionally, the monitoring record module 11, be also used to monitor corresponding first transmission path of the initial address and The transmission state of corresponding second transmission path of the destination address；
The multilevel iudge module 12 includes a preferential state specifically for the transmission state when first transmission path With a deferred mode, and the transmission state of second transmission path include a preferential state and a deferred mode when, judge The first transmission data meet the default dead lock condition；When in first transmission path and second transmission path When the transmission state of one transmission path does not include a preferential state and a deferred mode, the first transmission data are judged not Meet the default dead lock condition.
Optionally, the multilevel iudge module 12 is specifically used for sentencing when at least one described transmission channel is preferential state The transmission state of the disconnected starting start-stop described out and the destination address is preferential state；When at least one described transmission channel is delay When state, judge that the transmission state of the starting start-stop and the destination address is delay state；When at least one described transmission is logical Not only included preferential state in road, but also when including deferred mode, and had judged that the transmission state of the starting start-stop and the destination address was Preferential state or deferred mode.
Optionally, Figure 11, as shown in figure 12, the deadlock judgment means 1 further include: loop module 14 are based on.
The loop module 14, for when it is default judge that the time reaches when, reacquisition first transmission state, according to First transmission state reacquired and the present transmission state judge that transmitting the first transmission data whether can Generate bus deadlock.
The embodiment of the present invention provides a kind of computer readable storage medium, is stored thereon with computer program, is applied to dead It locks in judgment means 1, the method as described in embodiment one and embodiment two is realized when which executes.
Specifically, the corresponding program instruction of method of one of embodiment of the present invention deadlock judgement can be stored in On storage medium, when one of storage medium computer program instructions corresponding with chip interconnection methodologies are read by an electronic equipment It takes or is performed, include the following steps:
The first transmission data are received, obtain the corresponding first object address of the first transmission data, and according to default road Diameter time delay table determines the first transmission data corresponding first default arrival time；
It, will be described when the described first default arrival time the second default arrival time corresponding less than the second transmission data Corresponding first transmission state of first transmission data is set as preferential state, and the second transmission data corresponding second are transmitted State is set as deferred mode, and the second transmission data are to be sent to the transmission data of the first object address；
According to second transmission state, the corresponding current transmission of transmission path from initial address to destination address is updated State, and according to the present transmission state and first transmission state, it is pre- to judge whether the first transmission data meet If dead lock condition；
When judging that the first transmission data meet default dead lock condition, transmission the first transmission data are prevented.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the present invention Formula.Moreover, the present invention, which can be used, can use storage in the computer that one or more wherein includes computer usable program code The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates, Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one The step of function of being specified in a box or multiple boxes.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.

Claims (19)

1. a kind of deadlock judgment method, which is characterized in that the described method includes:
The first transmission data are received, the corresponding first object address of the first transmission data is obtained, and when according to preset path Prolong table, determines the first transmission data corresponding first default arrival time；
When the described first default arrival time the second default arrival time corresponding less than the second transmission data, by described first Corresponding first transmission state of transmission data is set as preferential state, and transmits corresponding second transmission state of data for described second It is set as deferred mode, the second transmission data are to be sent to the transmission data of the first object address；
According to second transmission state, the corresponding current transmission shape of transmission path from initial address to destination address is updated State, and according to the present transmission state and first transmission state, it is default to judge whether the first transmission data meet Dead lock condition；
When judging that the first transmission data meet default dead lock condition, transmission the first transmission data are prevented.
2. determining described the method according to claim 1, wherein described according to preset path time delay table One transmission data corresponding first default arrival time, comprising:
Corresponding first convergent point of the first transmission data and first monitored is obtained from the preset path time delay table Transmission delay；
According to first convergent point and first transmission delay, determine that the first transmission data corresponding first are preset Arrival time.
3. the method according to claim 1, wherein described determine the first transmission data corresponding first After default arrival time, it is described set preferential state for corresponding first transmission state of the first transmission data before, institute State method further include:
The the second transmission data for being sent to the first object address are searched, and determine the second transmission data The corresponding second default arrival time.
4. according to the method described in claim 3, it is characterized in that, the lookup is being sent to the first object address The second transmission data, and determine the second transmission data corresponding second default arrival time, comprising:
Obtain the current target address of the current transmission data monitored；
It is second biography by the current transmission data record when the current target address is the first object address Transmission of data；
It monitors described second and transmits data to the second transmission delay up to the first object address, and second transmission is prolonged When be recorded as the described second default arrival time.
5. according to the method described in claim 2, it is characterized in that, described transmit according to first convergent point with described first The first transmission data corresponding first default arrival time is determined in delay, comprising:
The corresponding third transmission of third transmission data and third transmission data of the monitoring by first convergent point is prolonged When；
When the first transmission delay is less than the third transmission delay, the described first default arrival time was recorded as described first Transmission delay；
When first transmission delay is greater than the third transmission delay, the described first default arrival time was recorded as described The sum of first transmission delay and preset time value.
6. the method according to claim 1, wherein the first transmission data are to send from the first initial address Transmission data, it is described second transmission data be the transmission data sent from the second initial address, it is described according to it is described second biography Defeated state updates the corresponding present transmission state of transmission path from initial address to destination address, comprising:
By it is described second transmission data it is corresponding from second initial address to the transmission state of the first object address more It is newly deferred mode.
7. according to the method described in claim 6, it is characterized in that, described pass according to the present transmission state with described first Defeated state, judges whether the first transmission data meet default dead lock condition, comprising:
Monitor the transmission of corresponding first transmission path of the initial address and corresponding second transmission path of the destination address State；
When the transmission state of first transmission path includes a preferential state and a deferred mode, and second transmission path Transmission state include a preferential state and a deferred mode when, judge it is described first transmit data meet the default deadlock Condition；
When the transmission state of any of first transmission path and second transmission path transmission path does not include one When preferential state and a deferred mode, judge that the first transmission data are unsatisfactory for the default dead lock condition.
8. the method according to the description of claim 7 is characterized in that including extremely between the initial address and the destination address A few transmission channel, it is described to monitor corresponding first transmission path of initial address and the destination address corresponding second The transmission state of transmission path, comprising:
When at least one described transmission channel is preferential state, the transmission shape of the initial address and the destination address is judged State is preferential state；
When at least one described transmission channel is delay state, the transmission shape of the starting start-stop and the destination address is judged State is delay state；
When not only having included preferential state at least one described transmission channel, but also when including deferred mode, judge the starting start-stop with The transmission state of the destination address is preferential state or deferred mode.
9. the method according to claim 1, wherein the prevention transmission it is described first pass data after, it is described Method further include:
When it is default judge that the time reaches when, reacquisition first transmission state；
According to first transmission state reacquired and the present transmission state, judge to transmit the first transmission number According to whether bus deadlock can be generated.
10. a kind of deadlock judgment means, which is characterized in that the deadlock judgment means include:
Bus system；
The monitoring record module being connect with the bus system；
The multilevel iudge module being connect with the monitoring record module；
The blocking module being connect with the multilevel iudge module and the bus system；Wherein,
The bus system, for receiving the first transmission data by the corresponding coffret of the first initial address, and will be described First transmission data are sent to the first destination address；
The monitoring record module obtains described for receiving the first transmission data by monitoring the coffret The corresponding first object address of one transmission data, and according to preset path time delay table, determine the first transmission data Corresponding first default arrival time；
The multilevel iudge module, for being preset when the described first default arrival time less than the second transmission data corresponding second When arrival time, preferential state is set by corresponding first transmission state of the first transmission data, and described second is transmitted Corresponding second transmission state of data is set as deferred mode, and the second transmission data are with being sent to the first object The transmission data of location；According to second transmission state, transmission path of the update from initial address to destination address is corresponding to be worked as Preceding transmission state, and according to the present transmission state and first transmission state, whether judge the first transmission data Meet default dead lock condition；
The blocking module, for preventing described in transmission when judging that the first transmission data meet default dead lock condition First transmission data.
11. deadlock judgment means according to claim 10, which is characterized in that
The monitoring record module, specifically for obtaining the first transmission number monitored from the preset path time delay table According to corresponding first convergent point and the first transmission delay；According to first convergent point and first transmission delay, determine Described first transmits data corresponding first default arrival time.
12. deadlock judgment means according to claim 10, which is characterized in that
The monitoring record module is also used to search the second transmission data for being sent to the first object address, And determine the second transmission data corresponding second default arrival time.
13. deadlock judgment means according to claim 12, which is characterized in that the monitoring record module is specifically used for The current target address of the current transmission data monitored is obtained from the coffret；When the current target address is described It is the second transmission data by the current transmission data record when first object address；Monitor the second transmission data The second transmission delay of the first object address is reached, and second transmission delay is recorded as the described second default arrival Time.
14. deadlock judgment means according to claim 11, which is characterized in that
The monitoring record module, specifically for monitoring by the third transmission data of first convergent point and the third Transmit the corresponding third transmission delay of data；It is pre- by described first when the first transmission delay is less than the third transmission delay If arrival time is recorded as first transmission delay；It, will when first transmission delay is greater than the third transmission delay The first default arrival time is recorded as the sum of first transmission delay and preset time value.
15. deadlock judgment means according to claim 10, which is characterized in that the first transmission data are from the first The transmission data that beginning address is sent, the second transmission data are the transmission data sent from the second initial address,
The monitoring record module, being specifically used for will described second to transmit data corresponding from second initial address to described The transmission state of first object address is updated to deferred mode.
16. deadlock judgment means according to claim 15, which is characterized in that
The monitoring record module is also used to monitor corresponding first transmission path of the initial address and the destination address pair The transmission state for the second transmission path answered；
The multilevel iudge module includes a preferential state and one specifically for the transmission state when first transmission path Deferred mode, and when the transmission state of second transmission path includes a preferential state and a deferred mode, judge described the One transmission data meet the default dead lock condition；When any of first transmission path and second transmission path pass When the transmission state in defeated path does not include a preferential state and a deferred mode, judge that the first transmission data are unsatisfactory for institute State default dead lock condition.
17. deadlock judgment means according to claim 15, which is characterized in that
The multilevel iudge module is specifically used for judging the starting start-stop when at least one transmission channel is preferential state Transmission state with the destination address is preferential state；When at least one described transmission channel is delay state, judge described The transmission state for originating start-stop and the destination address is delay state；When both including preferential at least one described transmission channel State, and when including deferred mode, judge that the transmission state of the starting start-stop and the destination address is preferential state or delay State.
18. deadlock judgment means according to claim 10, which is characterized in that the deadlock judgment means further include: follow Ring moulds block；
The loop module, for when it is default judge that the time reaches when, reacquisition first transmission state, according to obtaining again First transmission state got and the present transmission state judge to transmit whether the first transmission data can generate always Line deadlock.
19. a kind of computer readable storage medium, is stored thereon with computer program, it is applied in deadlock judgment means, it is special Sign is, such as claim 1-9 described in any item methods are realized when which is executed by processor.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111405008A (en) * 2020-03-06 2020-07-10 精英数智科技股份有限公司 Coal mine data transmission method, device and system
CN112052074A (en) * 2020-09-29 2020-12-08 上海兆芯集成电路有限公司 Processor modeling system and processor modeling method
CN113691434A (en) * 2021-08-31 2021-11-23 深圳云天励飞技术股份有限公司 Data transmission system, method, electronic device, and storage medium

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889972A (en) * 1997-03-25 1999-03-30 Adaptec, Inc. Bus to bus bridge deadlock prevention system
US20020112104A1 (en) * 2000-12-07 2002-08-15 Porterfield A. Kent Method of pacing and disconnecting transfers on a source strobed bus
CN101308477A (en) * 2008-06-13 2008-11-19 华为技术有限公司 System bus deadlock prevention method, device and on-chip system
CN102103560A (en) * 2009-12-16 2011-06-22 中兴通讯股份有限公司 Anti-deadlock method and device for system buses
CN103986664A (en) * 2014-05-15 2014-08-13 厦门大学 Mixed interconnection Mesh topological structure for on-chip network and routing algorithm thereof
CN106649180A (en) * 2016-09-09 2017-05-10 锐捷网络股份有限公司 Method and device for relieving I2C bus deadlock
CN106776272A (en) * 2016-11-11 2017-05-31 西北工业大学 Embedded system real-time performance testing method
CN107111572A (en) * 2014-10-31 2017-08-29 赛灵思公司 Method and circuit for avoiding deadlock

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889972A (en) * 1997-03-25 1999-03-30 Adaptec, Inc. Bus to bus bridge deadlock prevention system
US20020112104A1 (en) * 2000-12-07 2002-08-15 Porterfield A. Kent Method of pacing and disconnecting transfers on a source strobed bus
CN101308477A (en) * 2008-06-13 2008-11-19 华为技术有限公司 System bus deadlock prevention method, device and on-chip system
CN102103560A (en) * 2009-12-16 2011-06-22 中兴通讯股份有限公司 Anti-deadlock method and device for system buses
CN103986664A (en) * 2014-05-15 2014-08-13 厦门大学 Mixed interconnection Mesh topological structure for on-chip network and routing algorithm thereof
CN107111572A (en) * 2014-10-31 2017-08-29 赛灵思公司 Method and circuit for avoiding deadlock
CN106649180A (en) * 2016-09-09 2017-05-10 锐捷网络股份有限公司 Method and device for relieving I2C bus deadlock
CN106776272A (en) * 2016-11-11 2017-05-31 西北工业大学 Embedded system real-time performance testing method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GUANGDA ZHANG等: ""Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip"", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 *
齐鹏: ""基于未来锁集的死锁规避技术研究"", 《中国优秀硕士学位论文全文数据库 信息科技辑》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111405008A (en) * 2020-03-06 2020-07-10 精英数智科技股份有限公司 Coal mine data transmission method, device and system
CN112052074A (en) * 2020-09-29 2020-12-08 上海兆芯集成电路有限公司 Processor modeling system and processor modeling method
CN112052074B (en) * 2020-09-29 2024-05-03 上海兆芯集成电路股份有限公司 Processor modeling system and processor modeling method
CN113691434A (en) * 2021-08-31 2021-11-23 深圳云天励飞技术股份有限公司 Data transmission system, method, electronic device, and storage medium
CN113691434B (en) * 2021-08-31 2022-09-20 深圳云天励飞技术股份有限公司 Data transmission system, method, electronic device, and storage medium

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