CN102097130B - EEPROM erasing and writing method and device - Google Patents
EEPROM erasing and writing method and device Download PDFInfo
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- CN102097130B CN102097130B CN200910188822.6A CN200910188822A CN102097130B CN 102097130 B CN102097130 B CN 102097130B CN 200910188822 A CN200910188822 A CN 200910188822A CN 102097130 B CN102097130 B CN 102097130B
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Abstract
The invention relates to an electrically erasable programmable read-only memory (EEPROM) method, which comprises the following steps of: 1, controlling a charge pump circuit by using a column selected signal (V1) to realize column selection; and 2, controlling a high-level column selected signal (WL) by using a first logic signal to make the high-level column selected signal (WL) at least have voltage of the logic 1 so as to increase breakdown voltage, wherein the first logic signal is equal to the sum of a writing signal (W), a reading signal (R) and the column selected signal (V1). By the EEPROM erasing and writing device and the EEPROM erasing and writing method, the column selection is realized by the method of controlling the charge pump circuit, so the voltage on the WL at least has the level of the logic 1 to increase the breakdown voltage; moreover, the effectiveness of a clock is controlled by adding an NAND logic of the column selected signal (V1) onto the clock.
Description
Technical field
The present invention relates to memory circuitry design field, more particularly, relate to a kind of EEPROM erasing-writing method and device.
Background technology
Electrically Erasable Read Only Memory (EEPROM) is for the circuit of storing digital information.As shown in Figure 1, its circuit symbol as shown in Figure 2 for the floating-gate device structure of EEPROM.On control gate, adding high voltage is to carry out erasing move, and the high voltage differential of control gate and drain terminal causes electron tunneling to floating boom.Cause like this cut-in voltage of device to uprise, when control gate connecting to neutral current potential, source not conducting of drain terminal, for " 1 " of representative digit signal.On drain terminal, adding high voltage is to write action, and the high voltage differential of drain terminal and control gate causes electron tunneling, is from floating boom to drain terminal specifically.Cause like this cut-in voltage of device to become negative, when control gate connecting to neutral current potential, source drain terminal conducting, for " 0 " of representative digit signal.
As shown in Figure 3, M1 is for selecting erasable byte for corresponding erasable circuit, and whether M2 controls erasable, and M3 is floating-gate pipe, and M4 is isolated tube, and pump is charge pump circuit.V1 is decoding output, and high expression is chosen and wanted erasable row, otherwise does not choose.When V1 is logical one, after M4 pipe, the voltage on WL is high, charge pump circuit starts, and the upper voltage of WL is by logic promotion to high voltage, and the gate voltage of M1 is high voltage, high voltage V2(is higher than 14V like this) just can go to by M1 the grid of floating-gate pipe, just can carry out erasable action.When V1 is " 0 ", after M4 pipe, the voltage on WL is zero, and charge pump circuit is motionless, and the upper voltage of WL keeps the voltage of logical zero, and the gate voltage of M1 is zero, and high voltage V2 just cannot go to by M1 the grid of floating-gate pipe like this, cannot carry out erasable action.
Fig. 4 shows the charge pump circuit in described erasable circuit.Carrying out when erasable, if only a line is operated, the WL of other row is zero.For M5 and M1, in grid, be zero, and drain terminal is the situation of high pressure.For these high-voltage tubes, all can have punch-through, both voltage breakdown moved as shown in Figure 5 to high-pressure side.Subject matter is initial duty several times, breakdown potential is forced down and is large to substrate leakage current, at the large EEPROM of memory capacity, carry out when erasable, initially having several times very large substrate leakage current like this, cause V2 load overweight and cannot maintain erasable required high-voltage value.Will cause operation failure like this.And device do not have after high-pressure work in the long period, can reappear punch-through again.
In addition, when WL is zero, the clock of charge pump circuit still, in action, increases certain power consumption, and M5 pipe is closed simultaneously, and charge pump can cause M5 source to occur negative voltage, occurs the situation to substrate leakage.
Summary of the invention
The technical problem to be solved in the present invention is, for the above-mentioned defect of prior art, provides a kind of EEPROM erasing-writing method, comprising:
S1, employing row selected signal are controlled charge pump circuit and are chosen to realize row;
S2, adopt the first logical signal to control the capable selected signal of high level so that the capable selected signal of described high level at least has the voltage of logical one and then improves voltage breakdown, the capable selected signal of described the first logical signal=write signal+read signal &.
In EEPROM erasing-writing method of the present invention, in described step S1, adopt the second logical signal to control the clock signal of charge pump circuit effective, described the second logical signal is the non-signal of logical and of clock signal and row selected signal.
In EEPROM erasing-writing method of the present invention, described clock signal comprises anti-phase non-overlapping clock signal.
In EEPROM erasing-writing method of the present invention, described method further comprises:
S3, divide EEPROM into a plurality of, in each piece, comprise a plurality of row, in the process of described anti-phase non-overlapping clock signal being delivered to piece, carry out the selection of piece and control.
In EEPROM erasing-writing method of the present invention, in execution step during S3 or before, described anti-phase non-overlapping clock signal is divided into the anti-phase non-overlapping clock signal of multilayer.
In EEPROM erasing-writing method of the present invention, the supply voltage of clamp charge pump circuit.
The present invention solves another technical scheme that its technical matters adopts, and constructs a kind of EEPROM erasing apparatus, comprises the first metal-oxide-semiconductor for selecting erasable byte, erasable circuit, isolated tube and charge pump circuit; Wherein, the drain electrode of described isolated tube receives the first logical signal, grid connects power supply signal, the capable selected signal of source electrode output high level to the grid of charge pump circuit, the first metal-oxide-semiconductor and the first signal input end of erasable circuit, the capable selected signal of described the first logical signal=write signal+read signal &;
The clock control termination of described charge pump circuit is received the second logical signal, and described the second logical signal is the non-signal of logical and of clock signal and row selected signal;
The drain electrode of described the first metal-oxide-semiconductor is connected to the supply voltage of charge pump circuit, and source electrode connects the secondary signal input end of described erasable circuit;
The power input of described erasable circuit is connected to power supply, earth terminal ground connection.
In EEPROM erasing apparatus of the present invention, described erasable circuit comprises a plurality of erasable unit in parallel, each erasable unit comprises respectively erasable control tube and floating-gate pipe; Wherein
The grid of described erasable control tube receives the capable selected signal of high level, and drain electrode connects power supply, and source electrode is connected to the drain electrode of described floating-gate pipe,
The control floating boom utmost point of described floating-gate pipe is connected to the source electrode of described the first metal-oxide-semiconductor, the source ground of described floating-gate pipe.
In EEPROM erasing apparatus of the present invention, described erasable circuit further comprises the second metal-oxide-semiconductor, the drain electrode of described the second metal-oxide-semiconductor is connected to the supply voltage of charge pump circuit, and the grid of described the second metal-oxide-semiconductor and source electrode are connected to the grid of described the first metal-oxide-semiconductor.
In EEPROM erasing apparatus of the present invention, described EEPROM comprises a plurality of, comprises a plurality of row in each piece, carries out the selection of piece and control in the process of described anti-phase non-overlapping clock signal being delivered to piece.
Implement EEPROM erasing apparatus of the present invention and method, by controlling the mode of charge pump circuit, realize row and choose, make voltage on WL have at least logic " 1 " and current potential improve voltage breakdown.In addition, also, further by the NAND Logic of increase and row selected signal V1 on clock, whether effectively control clock.Prevent the generation of negative voltage, reduced electric leakage.Also further used clamping device, and then reduced power consumption and reduce clamping voltage.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the structural representation of EEPROM;
Fig. 2 is the circuit symbol figure of EEPROM;
Fig. 3 is the circuit diagram of the erasable circuit of EEPROM;
Fig. 4 is the circuit diagram of the charge pump circuit in the erasable circuit of EEPROM;
Fig. 5 is the voltage breakdown schematic diagram of the erasable circuit of EEPROM;
Fig. 6 is the process flow diagram of the erasing-writing method of EEPROM of the present invention;
Fig. 7 is the block diagram of the erasing apparatus of EEPROM of the present invention;
Fig. 8 is the circuit diagram of charge pump circuit of the erasing apparatus of EEPROM of the present invention;
Fig. 9 is the circuit theory diagrams of the another embodiment of erasing apparatus of EEPROM of the present invention;
Figure 10 is the piecemeal schematic diagram of the erasing apparatus of EEPROM of the present invention;
Schematic diagram is processed in the layering of the erasing apparatus of the EEPROM of the present invention of Figure 11.
Embodiment
Fig. 6 is the process flow diagram of the erasing-writing method of EEPROM of the present invention.As shown in Figure 6, in step S1, adopt row selected signal V1 to control charge pump circuit and choose to realize row.In one embodiment of the invention, can adopt the second logical signal to control the clock signal of charge pump circuit effective, described the second logical signal is the non-signal of logical and of clock signal and row selected signal V1.Described clock signal comprises anti-phase non-overlapping clock signal, i.e. clock signal clk and clock signal clk B.
In step S2, adopt the first logical signal to control the capable selected signal WL of high level so that the capable selected signal WL of described high level at least has the voltage of logical one and then improves voltage breakdown, the capable selected signal V1 of described the first logical signal=write signal W+ read signal R &.
In another preferred embodiment of the present invention, supply voltage V2 that also can clamp charge pump circuit, and then reduce power consumption and reduce clamping voltage.
In a preferred embodiment of the invention, when the capacity of EEPROM increases, the logical circuit of increase becomes considerable, can carry out subregion to it and control to reduce logical circuit.Namely divide EEPROM into a plurality of, in each piece, comprise a plurality of row, in the process of described anti-phase non-overlapping clock signal being delivered to piece, carry out the selection of piece and control.When piece is a lot, the selection control hierarchy of piece can be controlled, first clock layering is processed, namely described anti-phase non-overlapping clock signal is divided into the anti-phase non-overlapping clock signal of multilayer.
From the above analysis, the EEPROM erasing-writing method in the present invention, the physical characteristics that the voltage breakdown of utilizing MOS device increases with grid reduces the electric leakage problem of circuit original state, thereby stablize the erasable voltage of EEPROM, and assurance operates successfully.Adopt in addition the clock of digital control charge pump, prevented the generation of negative voltage, reduce electric leakage.By EEPROM being carried out to piecemeal processing, can reduce logical circuit, reduce costs.
Fig. 7 is the block diagram of the erasing apparatus of EEPROM of the present invention.As shown in Figure 7, the erasing apparatus of EEPROM of the present invention comprises for selecting the first metal-oxide-semiconductor M1, erasable circuit 100, isolated tube M4 and the charge pump circuit pump of erasable byte.The drain electrode of described isolated tube M4 receives the first logical signal, grid connects power supply signal VDD, the capable selected signal WL of source electrode output high level to the grid of charge pump circuit, the first metal-oxide-semiconductor M1 and the first signal input end of erasable circuit 100, the capable selected signal V1 of described the first logical signal=write signal W+ read signal R &.The clock control termination of described charge pump circuit is received the second logical signal, and described the second logical signal is the non-signal of logical and of clock signal and row selected signal V1; The drain electrode of described the first metal-oxide-semiconductor M1 is connected to the supply voltage V2 of charge pump circuit, and source electrode connects the secondary signal input end of described erasable circuit 100; The power input of described erasable circuit 100 is connected to power vd D, earth terminal ground connection.Described erasable circuit 100 comprises a plurality of erasable unit in parallel, and each erasable unit comprises respectively M2 and the floating-gate pipe M3 of erasable control tube; The grid of wherein said erasable control tube M2 receives the capable selected signal WL of high level, drain electrode connects power vd D, source electrode is connected to the drain electrode of described floating-gate pipe M3, and the control floating boom utmost point of described floating-gate pipe M3 is connected to the source electrode of described the first metal-oxide-semiconductor M1, the source ground of described floating-gate pipe M3.
Having adopted above-mentioned mode of using control charge pump circuit instead to realize row chooses.Make voltage on the capable selected signal WL of high level have at least logic " 1 " and current potential improve voltage breakdown.
Fig. 8 is the circuit diagram of charge pump circuit of the erasing apparatus of EEPROM of the present invention.As shown in Figure 8, whether effective by controlling clock signal with the non-signal of logical and of clock signal and row selected signal V1, prevented the generation of negative voltage, reduce electric leakage.Described clock signal comprises anti-phase non-overlapping clock signal, i.e. clock signal clk and clock signal clk B.They are input to control electrical appliances for electric charge pump so that it is controlled respectively at row selected signal V1 through Sheffer stroke gate.
When read-write is different conventionally, carry out, read signal R can regard the designature of write signal W as so, and logic " the capable selected signal V1 of write signal W+ read signal R & " can be converted to logic " the capable selected signal V1 of write signal W+ ".
Fig. 9 is the circuit theory diagrams of the another embodiment of erasing apparatus of EEPROM of the present invention.As shown in Figure 9, when read-write is different, carry out, read signal R can regard the designature of write signal W as so, and logic " the capable selected signal V1 of write signal W+ read signal R & " can be converted to logic " the capable selected signal V1 of write signal W+ ".Therefore, to receive the first logical signal be the capable selected signal V1 of write signal W+ in the drain electrode of isolated tube M4.Because the voltage on the capable selected signal WL of high level is when very high, can cause physical damnification to MOS device.Therefore as shown in Figure 9, adopted the second metal-oxide-semiconductor M6 to carry out clamp.The drain electrode of described the second metal-oxide-semiconductor M6 is connected to the supply voltage V2 of charge pump circuit, and the grid of described the second metal-oxide-semiconductor M6 and source electrode are connected to the grid of the first metal-oxide-semiconductor M1.When the high threshold voltage of voltage ratio supply voltage V2 is to make supply voltage V2 electric leakage, can reduce the power consumption on supply voltage V2, can limit again the voltage of supply voltage V2.
When the capacity of EEPROM increases, the logical circuit of increase becomes considerable, can carry out subregion to it and control to reduce logical circuit.Following clock signal clk and clock signal clk B being described as a clock signal clk, is that piece is processed EEPROM subregion, can have several rows in every.In clock is delivered to the process of piece, carry out the selection of piece and control, as shown in figure 10.Not so just that every provisional capital needs digital control charge pump, can reduce logical circuit.When piece is a lot, the selection control hierarchy of piece can be controlled, first clock layering is processed, as shown in figure 11.
From the above analysis, the erasing apparatus in the present invention, the physical characteristics that the voltage breakdown of utilizing MOS device increases with grid reduces the electric leakage problem of circuit original state, thereby stablize the erasable voltage of EEPROM, and assurance operates successfully.The clock of digital control charge pump, has prevented the generation of negative voltage, reduces electric leakage.By EEPROM being carried out to piecemeal processing, can reduce logical circuit, reduce costs.
Although the present invention describes by specific embodiment, it will be appreciated by those skilled in the art that, without departing from the present invention, can also carry out various conversion and be equal to alternative the present invention.Therefore, the present invention is not limited to disclosed specific embodiment, and should comprise the whole embodiments that fall within the scope of the claims in the present invention.
Claims (9)
1. an EEPROM erasing-writing method, is characterized in that, comprising:
S1, employing row selected signal (V1) are controlled charge pump circuit and are chosen to realize row;
S2, adopt the first logical signal to control the capable selected signal of high level (WL) so that the capable selected signal of described high level (WL) at least has the voltage of logical one and then improves voltage breakdown, the capable selected signal of described the first logical signal=write signal (W)+read signal (R) & (V1);
In described step S1, adopt the second logical signal to control the clock signal of charge pump circuit effective, described the second logical signal is the non-signal of logical and of clock signal and row selected signal (V1).
2. EEPROM erasing-writing method according to claim 1, is characterized in that, described clock signal comprises anti-phase non-overlapping clock signal.
3. EEPROM erasing-writing method according to claim 2, is characterized in that, described method further comprises:
S3, divide EEPROM into a plurality of, in each piece, comprise a plurality of row, in the process of described anti-phase non-overlapping clock signal being delivered to piece, carry out the selection of piece and control.
4. EEPROM erasing-writing method according to claim 3, is characterized in that, in execution step during S3 or before, described anti-phase non-overlapping clock signal is divided into the anti-phase non-overlapping clock signal of multilayer.
5. EEPROM erasing-writing method according to claim 1, is characterized in that, the supply voltage of clamp charge pump circuit (V2).
6. an EEPROM erasing apparatus, comprises for selecting first metal-oxide-semiconductor (M1) of erasable byte, erasable circuit (100), isolated tube (M4) and charge pump circuit (pump); It is characterized in that,
The drain electrode of described isolated tube (M4) receives the first logical signal, grid connects power supply signal (VDD), the source electrode output capable selected signal of high level (WL) to charge pump circuit, the grid of the first metal-oxide-semiconductor (M1) and the first signal input end of erasable circuit (100), the capable selected signal of described the first logical signal=write signal (W)+read signal (R) & (V1);
The clock control termination of described charge pump circuit is received the second logical signal, and described the second logical signal is the non-signal of logical and of clock signal and row selected signal (V1);
The drain electrode of described the first metal-oxide-semiconductor (M1) is connected to the supply voltage (V2) of charge pump circuit, and source electrode connects the secondary signal input end of described erasable circuit (100);
The power input of described erasable circuit (100) is connected to power supply (VDD), earth terminal ground connection.
7. EEPROM erasing apparatus according to claim 6, is characterized in that, described erasable circuit (100) comprises a plurality of erasable unit in parallel, and each erasable unit comprises respectively erasable control tube (M2) and floating-gate pipe (M3); Wherein
The grid of described erasable control tube (M2) receives the capable selected signal of high level (WL), and drain electrode connects power supply (VDD), and source electrode is connected to the drain electrode of described floating-gate pipe (M3),
The control floating boom utmost point of described floating-gate pipe (M3) is connected to the source electrode of described the first metal-oxide-semiconductor (M1), the source ground of described floating-gate pipe (M3).
8. EEPROM erasing apparatus according to claim 6, it is characterized in that, described erasable circuit (100) further comprises the second metal-oxide-semiconductor (M6), the drain electrode of described the second metal-oxide-semiconductor (M6) is connected to the supply voltage (V2) of charge pump circuit, and the grid of described the second metal-oxide-semiconductor (M6) and source electrode are connected to the grid of described the first metal-oxide-semiconductor (M1).
9. EEPROM erasing apparatus according to claim 6, it is characterized in that, described clock signal comprises anti-phase non-overlapping clock signal, described EEPROM comprises a plurality of, in each piece, comprise a plurality of row, in the process of described anti-phase non-overlapping clock signal being delivered to piece, carry out the selection of piece and control.
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| CN200910188822.6A CN102097130B (en) | 2009-12-10 | 2009-12-10 | EEPROM erasing and writing method and device |
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| CN200910188822.6A CN102097130B (en) | 2009-12-10 | 2009-12-10 | EEPROM erasing and writing method and device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1542858A (en) * | 1999-07-22 | 2004-11-03 | ���ǵ�����ʽ���� | High-density nor-type flash memory device and a program method thereof |
| CN101206923A (en) * | 2006-12-14 | 2008-06-25 | 三星电子株式会社 | Method of programming multi-level cells and non-volatile memory device including the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1542858A (en) * | 1999-07-22 | 2004-11-03 | ���ǵ�����ʽ���� | High-density nor-type flash memory device and a program method thereof |
| CN101206923A (en) * | 2006-12-14 | 2008-06-25 | 三星电子株式会社 | Method of programming multi-level cells and non-volatile memory device including the same |
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Address after: 518057, room 10, building 5-8, Changhong science and technology building, twelve South tech Road, Nanshan District Science Park, Shenzhen, Guangdong Patentee after: Huimang Microelectronics (Shenzhen) Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province science and Technology Park of Nanshan District high SSMEC building 4 floor Patentee before: FREMONT MICRO DEVICES (SZ) Ltd. |
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