CN102096389A - Automatic cataplasm coating control system based on FPGA (field programmable gate array) fuzzy pattern recognition - Google Patents
Automatic cataplasm coating control system based on FPGA (field programmable gate array) fuzzy pattern recognition Download PDFInfo
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Abstract
The invention relates to the fields of computer technology, automatic control technology and drug coating. In order to realize full automation of the process of controlling and detecting the cataplasm coating uniformity and thickness, improve the practicability and reliability of a system, lower the blindness in the production process and enhance the product quality, the invention adopts the technical scheme that an automatic cataplasm coating control system based on FPGA (field programmable gate array) fuzzy pattern recognition comprises a camera CCD (charge coupled device), a high capacity cache SDRAM (synchronous dynamic random access memory) which is taken as an external cache to store a digital video image signal and a programmable logic device FPGA, wherein the interior of the FPGA is provided with an SDRAM controller, a pattern recognition module comprises a division auxiliary functional module and is used for judging and recognizing a signal by applying the fuzzy pattern recognition principle and providing a control feedback signal, and the interior of the FPGA is also provided with a configuration initialization module used for initialization configuration on a video decoder. The invention is mainly applied to drug coating.
Description
Technical field
The present invention relates to computer technology and automatic control technology, medicament coating, specifically relate to cataplasm coating automatic control system based on the FPGA Fuzzy Pattern Recognition.
Background technology
In recent years, transdermal delivery system is in its unique and effective disease treatment mode, be subjected to the attention of domestic and international medicine and pharmacology research institution and pharmacy corporation deeply, in view of the wide market demand at home and abroad of TDDS system and application prospect with and at the therapeutic efficiency of field of medicaments uniqueness, with the pharmacy molding procedure of cataplasm push robotization to, the intelligentized trend of formation industry is irresistible.Cataplasm is coated with the proposition of automatic Control Study, belongs to an important research link of the novel transdermal delivery system new drug initiative of Chinese medicine problem in fact.
At present, the cataplasm end product quality detects and much all adopts the artificial method of identifying, its shortcoming is:
Analysis and assessment to uniformity coefficient and thickness have certain subjectivity, are difficult to form the normalization standard;
Its result's feedback can only be for referencial use for the production control of next paste preparation, and this product does not meet mark
Standard is eliminated, and therefore waste is serious, dirigibility is low.
Summary of the invention
For overcoming the deficiencies in the prior art, make the control detection process full automation of cataplasm coating uniformity coefficient and thickness, the practicality of raising system and reliability, be lowered into the blindness of product process, improve the quality of products, for achieving the above object, the technical solution used in the present invention is, cataplasm coating automatic control system based on the FPGA Fuzzy Pattern Recognition comprises:
Camera CCD at cataplasm coating scanning back pickup image, sends into then and carries out analog-to-digital conversion in the video a/d transducer, 4:2:2 digital video image signal Y, Cr and the Cb of output ITU-R BT.601-A standard, and ITU is the abbreviation of International Telecommunications Union (ITU);
Large capacity cache device SDRAM stores digital video image signal as external cache;
Programmable logic device (PLD) FPGA, FPGA inside is provided with sdram controller, sdram controller is used for controlling the data image signal that collects and is temporary in SDRAM, after treating that the whole whole buffer memorys of frame data finish, the inner pattern recognition module that is provided with of FPGA is reading of data from SDRAM again, and for accelerating arithmetic speed, pattern recognition module includes division arithmetic subsidiary function module, pattern recognition module is used to use the Fuzzy Pattern Recognition principle that signal is judged identification, provides the Control and Feedback signal; FPGA inside also is provided with the configuration initialization module, is used for the video a/d transducer is carried out initial configuration.
FPGA inside is provided with data transmission module, be used to receive clock signal from the output of video a/d transducer, the horizontal-drive signal HS of video a/d transducer output, vertical synchronizing signal VS is as the input control signal of data transmission module, 8 bit digital video decode input signals of video a/d transducer output are that this module is about to write data cached among the SDRAM, it also is the identifying object of pattern recognition module, this module with clock signal as timing reference signal, in valid data are capable, extract the YCrCb signal of 720 effective pixel points, and to merge the 8bit digital data converting by displacement be 16bit.
The sdram controller module port is, input port: clk100M is a clock signal input terminal, by output port clk the 100MHz clock is sent among the SDRAM as its internal timing benchmark, cmd is the activation command input end, rtc_flag is a read order input order end, addr[13:0] be 14 bit address signals, Destination Storage Unit among the addressing SDRAM, datain[15:0] x is 16 read/write data, output port: except cmd_ack, dataout[15:0] and the data_valid signal end, all the other signals are all corresponding with the SDRAM external pin to link to each other, finish the random access of data with control SDRAM sequential logic, the sdram controller module is provided with read_en and two of read_ack shake hands the answer signal port with coordination, and signal wire cmd, rtc_flag and addr are two module time division multiplexes, when data transmission module is worked, cmd, rtc_flag and addr[13:0] transmit and write control command and Input Address signal, and datain[15; 0] the input data are write in transmission; When the Fuzzy Pattern Recognition module is worked, cmd, rtc_flag and addr[13:0] transmit and read control command and OPADD signal, and dataout[15:0] transmit and read output data, follow output data_valid data read completion status signal, show read data output this moment effectively, feedback of status signal when cmd_ack is system busy, the running status that is used for judging SDRAM with and data whether can continue read-write.
Pattern recognition module is realized by finite state machine, and is worked according to the following procedure: during state State0, and three characteristic index Y, Cr of separating video picture signal and Cb; When changing State1 over to, input Y, Cr, Cb and three pattern scale values are asked respectively and are differed from and take absolute value; When changing State2 over to, input Y, Cr, Cb and three pattern scale values are sued for peace respectively; When changing State3 over to, with discussing among difference among the State1 and the State2 with value; When changing State4 over to, ask fuzzy Lambert distance; When changing State5 and State6 over to, utilize the subordinate function evaluation, do pattern-recognition, and provide the cataplasm automatic control signal according to maximum subjection principle; In order to guarantee the validity of control action, State7 design system response time-delay.
When the subordinate function of structural model identification, at first will be from fuzzy pattern A
iIn select K
iIndividual model, and, calculate this K then to the vectorial measured value of gathering of the characteristic index of each model
iThe mean value of individual characteristic index vector, i.e. model average;
Distance between the vedio data that calculating is read from SDRAM and each the pattern average model, the Lambert distance function is blured in design alternative, establish (U d) is metric space,
Promptly fuzzy Lambert distance is
Order
D＝max{d
1(U，a
1)，d
2(U，a
2)，d
3(U，a
3)}(2)
Fuzzy pattern A then
iSubordinate function be
At A
i(u) in the result of calculation, if A
1(u) maximum, the pattern-recognition judgement belongs to Mode A
1, output control control[2:0]=3 ' b100; If A
2(u) maximum, the pattern-recognition judgement belongs to Mode A
2, output control control[2:0]=3 ' b010; If A
3(u) maximum, the pattern-recognition judgement belongs to Mode A
3, output control control[2:0]=3 ' b001, the Fuzzy Pattern Recognition process is finished.
The present invention has following technique effect:
1, compared with prior art, cataplasm among the present invention coating automatic control system has adopted a kind of technical scheme of the Digital Image Processing based on Fuzzy Pattern Recognition Theory, target problem is converted into signal processing problems, make the control detection process full automation of cataplasm coating uniformity coefficient and thickness, the practicality of raising system and reliability are lowered into the blindness of product process;
2, one aspect of the present invention is attempted for the useful exploration that turned into automatically that realizes the production of TDDS preparations shaping, expanded the application of Fuzzy Pattern Recognition Theory on the other hand, to the reference energetically that moved towards the industrialization of TDDS forming production device from now in digital image processing field.
Description of drawings
Fig. 1 is the cataplasm coating automatic control system general frame block diagram that the present invention is based on the FPGA Fuzzy Pattern Recognition.
Fig. 2 is a FPGA system design process flow diagram.
Fig. 3 is the cataplasm coating automatic control system system module block scheme based on the FPGA Fuzzy Pattern Recognition.
Fig. 4 is a video a/d transducer ADV7181B configuration module state transition graph.
Fig. 5 is a video a/d transducer ADV7181B configuration module synthesis result.
Fig. 6 is that video a/d transducer ADV7181B configuration module is realized analogous diagram.
Fig. 7 is the data transmission module synthesis result.
Fig. 8 is a data transmission module sequential analogous diagram.
Fig. 9 is the sdram controller fundamental block diagram.
Figure 10 is sdram controller module synthesis result.
Figure 11 is a sdram controller modular simulation sequential chart.
Figure 12 realizes state transition graph for the Fuzzy Pattern Recognition module.
Figure 13 is the synthesis result of Fuzzy Pattern Recognition module.
Figure 14 is the sequential analogous diagram of Fuzzy Pattern Recognition module.
Figure 15 is the state transition graph of divider.
Figure 16 comprehensively reaches simulation result figure for the PLL frequency division module.
Embodiment
(transdermal drug delivery systems, TDDS) powerful development trend the invention discloses a kind of cataplasm coating automatic control system based on the FPGA Fuzzy Pattern Recognition in order to comply with transdermal delivery system.CCD camera and video a/d transducer have been installed at front end by this system, for the realization of total system provides reliable analysis input data, ambiguity according to room and time correlativity between the picture signal pixel and feature boundary thereof, in the Fuzzy Pattern Recognition Theory embedded system, by online detection, to being analyzed, handle and discerned by the digital video frequency flow of video a/d transducer conversion, finally successfully feedback is exported automatic control signal.Native system adopts the EP2C35 fpga chip based on Cyclone II series, and utilization Verilog HDL hardware description language is realized the online detection of cataplasm, coating control closed-loop system automatically.
Further describe the present invention below in conjunction with drawings and Examples.
The present invention proposes a kind of cataplasm coating automatic control system based on the FPGA Fuzzy Pattern Recognition, CCD camera and video a/d transducer ADV7181B have installed at front end in this system, for the realization of total system provides reliable analysis input data, ambiguity according to room and time correlativity between the picture signal pixel and feature boundary thereof, the Fuzzy Pattern Recognition Theory embedded system is designed, by online detection, to analyzing by the digital video frequency flow of video a/d transducer ADV7181B conversion, handle and identification, finally successfully feedback is exported automatic control signal.
The integral frame of this cataplasm coating automatic control system as shown in Figure 1, the CCD camera is absorbing a frame plaster image to cataplasm coating scanning back, send into then among the video a/d transducer ADV7181B and carry out analog-to-digital conversion, 4:2:2 digital video image signal Y, Cr and the Cb of output and ITU-RBT.601-A standard.Because the quantity of information of a frame of digital vision signal is very big, the necessary external large capacity cache device SDRAM of system is as external cache.Programmable logic device (PLD) FPGA is the kernal hardware of native system framework.Complicacy at the SDRAM control timing, at first on FPGA, realized bridge module---the sdram controller of image data transmission, like this, data transmission module just can be temporary in the data image signal that collects among the SDRAM, after treating that the whole whole buffer memorys of frame data finish, based on the pattern recognition module of FPGA reading of data from SDRAM again, and utilization Fuzzy Pattern Recognition principle is judged identification to signal, provide the Control and Feedback signal, realize cataplasm coating control closed system automatically.In addition, some characteristic of video a/d transducer and mode of operation must also comprise an ADV7181B configuration initialization module in the native system, and the Divide module be the division arithmetic subsidiary function module of Fuzzy Pattern Recognition module among the figure through being provided with and could using.
The present invention is when making up whole hardware system, utilization Verilog hardware description language realizes that interface connects, when finishing control, data-switching, buffer memory and pattern-recognition and output feedback signal, each Devices Characteristics is the basis of design concept, but of paramount importance is the control that realizes the sequential logic of each system core module by programmable logic device (PLD) FPGA, is FPGA system design process flow diagram as shown in Figure 2.
As shown in Figure 3, system module block scheme for this system, wherein frame of broken lines partly is the kernal hardware fpga chip of native system framework, and the programming of utilization Verilog HDL hardware language has realized respectively video a/d transducer ADV7181B initial configuration module, data transmission module, sdram controller module, Fuzzy Pattern Recognition module and PLL frequency division module and each intermodule interface based on the video a/d transducer are connected and data transmission.The present invention realizes the program design and the sequential emulation of whole system function on Quartus II platform, and downloads in the EP2C35 fpga chip of altera corp.
ADV7181B carries out initial configuration to the video a/d transducer, is to pass through I
2The C bus carries out to it that write operation finishes, and by the realization of programming on FPGA of Verilog HDL hardware description language, its major state transition diagram is shown in 4.After system powers on, enter the S0 state of time-delay 0.5ms immediately based on the ADV7181B configuration module of FPGA, after treating that all circuit are stable, the S0 status transition is to the S1 state, send into write address, register subaddressing and the control word serial-shift able to programme thereof of ADV7181B among the ADV7181B successively by interface, after configuration is finished, enter the S2 state by the S1 state, i.e. the normal mode of operation state.
ADV7181B configuration module interface schema after comprehensive on the Quartus II as shown in Figure 5, the left side is an input interface, the right is an output interface.Sclk100k connects the serial time clock line SCL of ADV7181B, and sdata connects the serial data line SDA of ADV7181B, is the bi-directional data interface, and sda_ack is this module data delivery status feedback interface.Clk200k is the internal system time clock of module, and rst_n is a reset signal, and Fig. 6 is an ADV7181B configuration module sequential analogous diagram.
Data transmission module receives 27MHz (clk27M) clock signal from ADV7181B output, horizontal-drive signal HS (hs), and vertical synchronizing signal VS (vs), they are as the input control signal of whole module; It is data cached that 8 bit digital video input signals are that this module is about to write among the SDRAM, also is the pattern-recognition object.Most crucial design partly is a utilization Verilog HDL language in this module, realized with the 27MHz clock signal as timing reference signal, in valid data are capable, extract Y, Cr, the Cb signal of 720 effective pixel points, and to merge the 8bit digital data converting by displacement be 16bit.
Data transmission module interface schema after comprehensive on the Quartus II as shown in Figure 7, the left end input, right-hand member output, clk27M, hs, vs and td_data are input clock, synchronous control signal and the video data streams from ADV7181B, read_ack is the read states return path signal from the Fuzzy Pattern Recognition module, be the communication handshake answer signal to avoid reading and writing data conflict to SDRAM, guarantee that the next frame image data acquiring occurs in pattern-recognition and finishes after.The right output signal cmd1, rtc_flag, saddr[13:0] with data_out[15:0] all link to each other with sdram controller, produce write operation order, address and data, read_en reads to enable control for the Fuzzy Pattern Recognition module provides, that is data storage done state sign, rowaddr[11:0] and coladdr[7:0] output after all send into pattern recognition module, doing to stop judging for its reading of data from SDRAM, is the sequential analogous diagram of data transmission module as shown in Figure 8.
The sdram controller module is made up of three submodules again, comprising system interface module, command analysis and respond module and data channel module.Three Module Design realized respectively in utilization Verilog HDL language, then can sdram controller of complete realization with corresponding just is connected of the port of system interface module, command analysis and respond module and data channel module, the interface connection between these three parts and the system architecture of entire controller module are as shown in Figure 9.
Sdram controller module interface figure after comprehensive on the Quartus II as shown in figure 10, in the input interface of the left side, clk100M is a clock signal input terminal, by output port clk the 100MHz clock is sent among the SDRAM as its internal timing benchmark, cmd is the activation command input end, and rtc_flag is a read order input order end, addr[13:0] be 14 bit address signals, Destination Storage Unit among the addressing SDRAM, datain[15:0] be 16 read/write data.The right is the output signal end of module, except cmd_ack, dataout[15:0] and the data_valid signal, all the other signals are all corresponding with the SDRAM external pin to link to each other, and finishes the random access of data with control SDRAM sequential logic.In order to guarantee that data read/write does not clash, system is provided with read_en and two answer signals of shaking hands of read_ack with coordination, and signal wire cmd, rtc_flag and addr are two module time division multiplexes.When data transmission module is worked, cmd, rtc_flag and addr[13:0] transmit and write control command and Input Address signal, and datain[15; 0] the input data are write in transmission; When the Fuzzy Pattern Recognition module is worked, cmd, rtc_flag and addr[13:0] transmit and read control command and OPADD signal, and dataout[15:0] transmit and read output data, follow output data_valid data read completion status signal, show read data output this moment effectively.Feedback of status signal when cmd_ack is system busy, the running status that is used for judging SDRAM with and data whether can continue read-write, its emulation sequential chart is as shown in figure 11.
A most important part is exactly the Fuzzy Pattern Recognition Module Design and and realizes in the cataplasm coating automatic control system.The Fuzzy Pattern Recognition module embeds Digital Image Processing with the Fuzzy Pattern Recognition algorithm, and concrete steps comprise:
Extract characteristic index;
Set the fuzzy pattern classification and construct subordinate function;
Utilize maximum subjection principle to discern judgement.
Mode identification procedure is that the pixel of image is differentiated one by one, and discrimination standard is that the image feature value according to the plaster standard thickness carries out category attribution, and then realizes the adjustment and the control of uniformity coefficient.The characteristic index value of establishing criteria thickness is divided into three major types with recognition mode, promptly meets thickness calibration (Mode A
1), almost meet thickness calibration (Mode A
2) and do not meet thickness calibration (Mode A
3), and relative three patterns of input digital image sample value to be done to be subordinate to sort out identification, the conversion discriminant value exports cataplasm coating shower nozzle to for the Control and Feedback signal, and what of control painting medicine amount are realized the automatic control adjustment of cataplasm uniformity coefficient and thickness.
When the subordinate function of structural model identification, at first will be from fuzzy pattern A
iIn select K
iIndividual model, and, calculate this K then to the vectorial measured value of gathering of the characteristic index of each model
iThe mean value of individual characteristic index vector, i.e. model average, computed range is prepared during for the structure subordinate function.A kind of corresponding three mode characteristic index Y, C
rAnd C
bThe model average as shown in table 1.
The equal value list of model of table 1 associative mode characteristic index
| Type | Y | C b | C r |
| A 1 | 01011011 | 11110000 | 01010010 |
| A 2 | 01000101 | 10110100 | 00111101 |
| A 3 | 00101110 | 01111000 | 00101001 |
Distance between the vedio data that calculating is read from SDRAM and each the pattern average model, according to the characteristic of native system hardware programmable logical device FPGA, the Lambert distance function is blured in design alternative, establish (U d) is metric space,
Promptly fuzzy Lambert distance is
Order
D＝max{d
1(U，a
1)，d
2(U，a
2)，d
3(U，a
3)}(2)
Fuzzy pattern A then
iSubordinate function be
At A
i(u) in the result of calculation, if A
1(u) maximum, the pattern-recognition judgement belongs to Mode A
1, output control control[2:0]=3 ' b100; If A
2(u) maximum, the pattern-recognition judgement belongs to Mode A
2, output control control[2:0]=3 ' b010; If A
3(u) maximum, the pattern-recognition judgement belongs to Mode A
3, output control control[2:0]=3 ' b001.The Fuzzy Pattern Recognition process is finished.
In program design, module mainly realizes that by finite state machine its detailed process as shown in figure 12.During state State0, three characteristic index Y, Cr of separating video picture signal and Cb; When changing State1 over to, input Y, Cr, Cb and three corresponding substitution formula 1 molecules of pattern scale value ask to differ from and take absolute value; When changing State2 over to, input Y, Cr, Cb and three corresponding substitution formula 1 denominators of pattern scale value, summation; When changing State3 over to, with discussing among difference among the State1 and the State2 with value; When changing State4 over to, ask fuzzy Lambert distance; When changing State5 and State6 over to, utilize the subordinate function evaluation, do pattern-recognition, and provide the cataplasm automatic control signal according to maximum subjection principle; In order to guarantee the validity of control action, State7 design system response time-delay.
Fuzzy Pattern Recognition module interface figure after comprehensive on the Quartus II as shown in figure 13, the left side is an input signal, the right is an output signal.Clk25MHz is the internal system timing base clock of the pattern recognition module that obtained by the PLL frequency division, is 1/4 of SDRAM work clock; Required time is finished in read-write sequence and instruction thereof according to SDRAM, Active order or the read/write command of the SDRAM of execution that clk25MHz clock period can be complete.With data transmission module roughly the same, the Fuzzy Pattern Recognition module also will be separated triggering with activation command to the read/write command of SDRAM, when arriving, first clk25M rising edge clock produces activation command, produce read/write command when and then next rising edge clock arrives, two order timesharing are carried out, are not conflicted mutually.Read_en is two communication handshake answer signals that link to each other with data transmission module with read_ack, read_en is the input signal from data transmission module, the digital of digital video data of exporting when the ADV7181B analog to digital conversion all is cached among the SDRAM, data transmission module sends read_en and shows that this module design task execution finishes, and triggers fuzzy pattern recognition module reading of data from SDRAM and carry out pattern-recognition; Finish the Fuzzy Pattern Recognition processing of whole two field picture when pattern recognition module after, output automatic control signal control[2:0], and producing read_ack feedback of status signal, the notification data transport module can preparation for acquiring next frame vedio data.Input signal rowaddr[11:0] and coladdr[7:0] be the last reference address of data transmission module metadata cache to SDRAM, send into pattern recognition module and judge, guarantee the integrality of video image information collection and take along closing property as data read termination address value.Input signal vs is the vertical synchronizing signal from ADV7181B equally, greatly different with the effect in data transmission module is, when the vs rising edge arrives, rowaddr[11:0] and coladdr[7:0] in address counting stop value can send into system and stop judge index as addressed command.Output signal cmd2 and rtc_flag2 are the SDRAM read control signals, saddr[13:0] output addressing address; Input signal data_valid characterizes the SDRAM data and is output as effectively dq[15:0] be the input digital image data, i.e. Fuzzy Pattern Recognition object.The sequential simulation result of fuzzy pattern module on Quartus II as shown in figure 14.
Embedded two integers that keep 5 position effective digitals behind the radix point in the Fuzzy Pattern Recognition module and made merchant's divider module, in program design, this module mainly realizes that by finite state machine its detailed process as shown in figure 15.
Each module has nothing in common with each other to the requirement of its inside input clock among the present invention, the PLL module is carried out frequency division and frequency multiplication with outside input clock 50MHz, output 100MHz clock is sent in the sdram controller module, the 100KHz clock is sent in the ADV7181B configuration module, the 25MHz clock is sent in the Fuzzy Pattern Recognition module, for each module provides timing reference signal, the operation of assurance system is in order strict.Its synthesis result and sequential analogous diagram are as shown in figure 16.
After each module all realizes, carry out the module merging and obtain the FPGA of kernal hardware system, carry out the emulation and the test of The whole control system then.Download among the FPGA, through actual motion, respond well.
One aspect of the present invention is attempted for the useful exploration that turned into automatically that realizes the production of TDDS preparations shaping, expanded the application of Fuzzy Pattern Recognition Theory on the other hand, to the reference energetically that moved towards the industrialization of TDDS forming production device from now in digital image processing field.
Annotate: the CCIR601 standard name has now changed ITU-R BT.601-A into, and CCIR is the abbreviation of Consultative Committee on International Radio (CCIR), and its English full name is: International Consultative Committee for Radio.ITU is the abbreviation of International Telecommunications Union (ITU), and its English full name is: International Telecommunication Union.
Claims (5)
1. the cataplasm coating automatic control system based on the FPGA Fuzzy Pattern Recognition is characterized in that, comprising:
Camera CCD at cataplasm coating scanning back pickup image, sends into then and carries out analog-to-digital conversion in the video a/d transducer, 4:2:2 digital video image signal Y, Cr and the C of output ITU-R BT.601-A standard
b, ITU is the abbreviation of International Telecommunications Union (ITU);
Large capacity cache device SDRAM stores digital video image signal as external cache;
Programmable logic device (PLD) FPGA, FPGA inside is provided with sdram controller, sdram controller is used for controlling the data image signal that collects and is temporary in SDRAM, after treating that the whole whole buffer memorys of frame data finish, the inner pattern recognition module that is provided with of FPGA is reading of data from SDRAM again, pattern recognition module includes division arithmetic subsidiary function module, and pattern recognition module is used to use the Fuzzy Pattern Recognition principle that signal is judged identification, provides the Control and Feedback signal; FPGA inside also is provided with the configuration initialization module, is used for Video Decoder is carried out initial configuration.
2. a kind of cataplasm coating automatic control system according to claim 1 based on the FPGA Fuzzy Pattern Recognition, it is characterized in that, FPGA inside is provided with data transmission module, be used to receive clock signal from the output of video a/d transducer, the horizontal-drive signal HS of video a/d transducer output, vertical synchronizing signal VS is as the input control signal of data transmission module, 8 position digital signals of video a/d transducer output are that this module is about to write data cached among the SDRAM, it also is the identifying object of pattern recognition module, this module with clock signal as timing reference signal, in valid data are capable, extract the Y of 720 effective pixel points, Cr, the Cb signal, and to merge the 8bit digital data converting by displacement be 16bit.
3. a kind of cataplasm coating automatic control system according to claim 1 based on the FPGA Fuzzy Pattern Recognition, it is characterized in that, the sdram controller module port is, input port: clk100M is a clock signal input terminal, by output port the 100MHz clock is sent among the SDRAM as its internal timing benchmark; Cmd is the activation command input end; Rtc_flag is the read command input end; Addr[13:0] be 14 bit address signals, Destination Storage Unit among the addressing SDRAM; Datain[15:0] be 16 read/write data.Output port: except cmd_ack, dataout[15:0] and the data_valid signal end, all the other signals are all corresponding with the SDRAM external pin to link to each other, and finishes the random access of data with control SDRAM sequential logic.The sdram controller module is provided with read_en and two of read_ack shake hands the answer signal port with coordination, and signal wire cmd, rtc_flag and addr are two module time division multiplexes.When data transmission module is worked, cmd, rtc_flag and addr[13:0] transmit and write control command and Input Address signal, and datain[15; 0] the input data are write in transmission; When the Fuzzy Pattern Recognition module is worked, cmd, rtc_flag and addr[13:0] transmit and read control command and OPADD signal, and dataout[15:0] transmit and read output data, follow output data_valid data read completion status signal, show read data output this moment effectively, feedback of status signal when cmd_ack is system busy, the running status that is used for judging SDRAM with and data whether can continue read-write.
4. a kind of cataplasm coating automatic control system according to claim 1 based on the FPGA Fuzzy Pattern Recognition, it is characterized in that, pattern recognition module is realized by finite state machine, and work according to the following procedure: during state State0, three characteristic index Y, Cr of separating video picture signal and Cb; When changing State1 over to, input Y, Cr, Cb and three pattern scale values are asked respectively and are differed from and take absolute value; When changing State2 over to, input Y, Cr, Cb and three pattern scale values are sued for peace respectively; When changing State3 over to, with discussing among difference among the State1 and the State2 with value; When changing State4 over to, ask fuzzy Lambert distance; When changing State5 and State6 over to, utilize the subordinate function evaluation, do pattern-recognition, and provide the cataplasm automatic control signal according to maximum subjection principle; In order to guarantee the validity of control action, State7 design system response time-delay.
5. a kind of cataplasm coating automatic control system based on the FPGA Fuzzy Pattern Recognition according to claim 4 is characterized in that, when the subordinate function of structural model identification, and at first will be from fuzzy pattern A
iIn select K
iIndividual model, and, calculate this K then to the vectorial measured value of gathering of the characteristic index of each model
iThe mean value of individual characteristic index vector, i.e. model average;
Distance between the vedio data that calculating is read from SDRAM and each the pattern average model, the Lambert distance function is blured in design alternative, establish (U d) is metric space,
Promptly fuzzy Lambert distance is
Order
D＝max{d
1(U，a
1)，d
2(U，a
2)，d
3(U，a
3)}(2)
Fuzzy pattern A then
iSubordinate function be
At A
i(u) in the result of calculation, if A
1(u) maximum, the pattern-recognition judgement belongs to Mode A
1, output control control[2:0]=3 ' b100; If A
2(u) maximum, the pattern-recognition judgement belongs to Mode A
2, output control control[2:0]=3 ' b010; If A
3(u) maximum, the pattern-recognition judgement belongs to Mode A
3, output control control[2:0]=3 ' b001, the Fuzzy Pattern Recognition process is finished.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103110518A (en) * | 2013-03-08 | 2013-05-22 | 桂林电子科技大学 | Automatic spread coating machine of black plaster |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2497783Y (en) * | 2001-03-09 | 2002-07-03 | 天津大学 | Automatic high sticky colloid ointment spreading and sheet-cutting apparatus |
| JP2010160038A (en) * | 2009-01-08 | 2010-07-22 | Seiko Epson Corp | Substrate to be inspected, method for manufacturing the same, and flaw inspecting device |
| CN101916103A (en) * | 2010-08-19 | 2010-12-15 | 常州市泛亚电器制造有限公司 | Process flow data acquisition system of patch production line |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2497783Y (en) * | 2001-03-09 | 2002-07-03 | 天津大学 | Automatic high sticky colloid ointment spreading and sheet-cutting apparatus |
| JP2010160038A (en) * | 2009-01-08 | 2010-07-22 | Seiko Epson Corp | Substrate to be inspected, method for manufacturing the same, and flaw inspecting device |
| CN101916103A (en) * | 2010-08-19 | 2010-12-15 | 常州市泛亚电器制造有限公司 | Process flow data acquisition system of patch production line |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103110518A (en) * | 2013-03-08 | 2013-05-22 | 桂林电子科技大学 | Automatic spread coating machine of black plaster |
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