FT method of testing based on the VIP module of FPGA
[technical field]
The present invention relates to chip testing technology, specifically be meant a kind of FT method of testing of the VIP module based on FPGA.
[background technology]
Test before dispatching from the factory after the IC encapsulation is FT (final test) test.The FT test comprises LCDC, VIP, I
2The test of modules such as S.
VIP module (Video Input Processor, vision signal input processor), it is a signal processor that the various video signal can be changed into various forms.
The method of testing of VIP module in the prior art: the VSYNC negate in the RGB sequential of LCD, the sequential that obtains is just in full accord with the sequential of VIP, therefore utilize this point, allow lcd controller produce the RGB sequential of VSYNC negate, gather the LCD data line by VIP, relatively the data sent of lcd controller and the VIP data of adopting just can verify whether LCD module and VIP module be working properly.
The shortcoming of the method for testing of prior art is when any part existing problems of LCDC or VIP module, and whether all can not test out an other functions of modules correct.Just say also whether can not test out the LCDC functions of modules normal if the VIP functions of modules is undesired; Whether conversely when the LCDC functions of modules is unusual, it is normal to test out the VIP functions of modules, and the final test yield of chip can be subjected to bigger influence like this.Now these two are separately tested separately and avoided this situation, thereby improved the test yield.
[summary of the invention]
Technical matters to be solved by this invention is to provide a kind of FT method of testing of the VIP module based on FPGA, this method can realize any digital circuit flexibly, break away from the interference of simulating signal, reduce the constraint that is limited by special chip, assist the FT test of chip to be measured.
The present invention solves above-mentioned technical matters by the following technical solutions:
FT method of testing based on the VIP module of FPGA comprises the steps:
Step 100: one of design sends data module in FPGA;
Step 200:, send the sequential of data as FPGA with the VSYNC negate of LCDC;
Step 300:FPGA sends the data of CCIR656 or YUV422 form and samples to VIP, and the sequential of VIP sampling is consistent with the sequential that sends data;
Step 400: with the data contrast of the data that sample and transmission, whether test VIP operate as normal.
When in the described step 400 data of the data that sample and transmission being compared, only need read into the data of two files in two arrays, these two arrays are compared.
When in the described step 400 data of the data that sample and transmission being compared, in FPGA, embed the ARM9 processor, the data that collect are deposited in certain address field of memory, begin comparison from the first address that sends data and image data during contrast.
The invention has the advantages that: the present invention can realize any digital circuit flexibly, data transmission blocks at the VIP reasonable module design of chip to be measured, break away from the interference of simulating signal and other irrelevant signals, reduce the constraint that is limited by special chip, assist the FT test of chip to be measured.
[description of drawings]
The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is a VIP module testing synoptic diagram.
[embodiment]
See also Fig. 1, clk among Fig. 1, hsync, rst, vsync are the input control signals that is provided by chip to be measured, as long as the sequential of these four signals is correct, so just can produce correct enable control signal, the enable signal is used for controlling when begin to send data.Data_in[7..0] be the input data signal that provides by chip to be measured, the data bit of VIP test module comes to 8.The data_out[7..0 that collects] send to the VIP module of chip to be measured.It is VIP module testing step synoptic diagram.Specifically comprise the steps:
Step 100: one of design sends data module in FPGA;
Step 200:, send the sequential of data as FPGA with the VSYNC negate of LCDC;
Step 300:FPGA sends the data of CCIR656 or YUV422 form and samples to VIP, and the sequential of VIP sampling is consistent with the sequential that sends data;
Step 400: with the data contrast of the data that sample and transmission, whether test VIP operate as normal.When the data of the data that sample and transmission are compared, only need read into the data of two files in two arrays, these two arrays are compared.Also can in FPGA, embed the ARM9 processor, the data that collect be deposited in certain address field of memory, begin comparison from the first address that sends data and image data during contrast.
The present invention can realize any digital circuit flexibly, breaks away from the interference of simulating signal, reduces the constraint that is limited by special chip, assists the FT test of chip to be measured.