CN102096038B - FPGA (Field Programmable Gate Array) based FT (Functional Test) method of VIP (Video Input Processor) module - Google Patents
FPGA (Field Programmable Gate Array) based FT (Functional Test) method of VIP (Video Input Processor) module Download PDFInfo
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- CN102096038B CN102096038B CN 201010555392 CN201010555392A CN102096038B CN 102096038 B CN102096038 B CN 102096038B CN 201010555392 CN201010555392 CN 201010555392 CN 201010555392 A CN201010555392 A CN 201010555392A CN 102096038 B CN102096038 B CN 102096038B
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Abstract
The invention relates to an FPGA (Field Programmable Gate Array) based FT (Functional Test) method of a VIP (Video Input Processor) module. The method comprises the following steps of: designing a data sending module in the FPGA; negating VSYNC (Vertical Synchronization) of an LCDC (LCD Controller) and using the negated VSYNC as a time sequence for sending data; sending data in the form of CCIR656 or YUV422 to the VIP for sampling, wherein the time sequence of VIP sampling is consistent with the time sequence of sending the data; and comparing the sampled data with the sent data to test whether the VIP normally works or not. The method provided by the invention can flexibly realize any digital circuit, get rid of the interference of analog signals and reduce the constraint at the mercy of a special chip so as to assist the FT of a chip to be tested.
Description
[technical field]
The present invention relates to chip testing technology, specifically refer to a kind of FT method of testing of the VIP module based on FPGA.
[background technology]
Test before dispatching from the factory after the IC encapsulation is FT (final test) test.The FT test comprises LCDC, VIP, I
2The test of the modules such as S.
VIP module (Video Input Processor, vision signal input processor), it is a signal processor that various video signal can be changed into various forms.
The method of testing of VIP module in the prior art: the VSYNC negate in the RGB sequential of LCD, the sequential that obtains is just in full accord with the sequential of VIP, therefore utilize this point, allow lcd controller produce the RGB sequential of VSYNC negate, gather the LCD data line by VIP, relatively the data sent of lcd controller and the VIP data of adopting just can verify whether LCD module and VIP module be working properly.
The shortcoming of the method for testing of prior art is whether correct when LCDC or any part existing problems of VIP module if all can not test out an other functions of modules.Also just say whether normal if the VIP functions of modules is undesired if can not test out the LCDC functions of modules; Whether when the LCDC functions of modules is unusual, it is normal to test out the VIP functions of modules conversely, and the final test yield of chip can be subject to larger impact like this.Now these two are separately tested separately and avoided this situation, thereby improved the test yield.
[summary of the invention]
Technical matters to be solved by this invention is to provide a kind of FT method of testing of the VIP module based on FPGA, the method can realize any digital circuit flexibly, break away from the interference of simulating signal, reduce the constraint that is limited by special chip, assist the FT test of chip to be measured.
The present invention solves above-mentioned technical matters by the following technical solutions:
FT method of testing based on the VIP module of FPGA comprises the steps:
Step 100: one of design sends data module in FPGA;
Step 200: with the VSYNC negate of LCDC, send the sequential of data as FPGA;
Step 300:FPGA sends the data of CCIR656 or YUV422 form and samples to VIP, and the sequential of VIP sampling is consistent with the sequential that sends data;
Step 400: with the data that sample and the Data Comparison of transmission, whether test VIP works.
When in the described step 400 data of the data that sample and transmission being compared, only need in the data reading to two of two files array, these two arrays be compared.
When in the described step 400 data of the data that sample and transmission being compared, in FPGA, embed the ARM9 processor, the data that collect are deposited in certain address field of memory, begin comparison from the first address that sends data and image data during contrast.
The invention has the advantages that: the present invention can realize any digital circuit flexibly, data transmission blocks for the VIP reasonable module design of chip to be measured, break away from the interference of simulating signal and other irrelevant signals, reduce the constraint that is limited by special chip, assist the FT test of chip to be measured.
[description of drawings]
The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is VIP module testing synoptic diagram.
[embodiment]
See also Fig. 1, clk among Fig. 1, hsync, rst, vsync are the input control signals that is provided by chip to be measured, as long as the sequential of these four signals is correct, so just can produce correct enable control signal, the enable signal is used for controlling when begin to send data.Data_in[7..0] be the input data signal that is provided by chip to be measured, the data bit of VIP test module comes to 8.The data_out[7..0 that collects] send to the VIP module of chip to be measured.It is VIP module testing step synoptic diagram.Specifically comprise the steps:
Step 100: one of design sends data module in FPGA;
Step 200: with the VSYNC negate of LCDC, send the sequential of data as FPGA;
Step 300:FPGA sends the data of CCIR656 or YUV422 form and samples to VIP, and the sequential of VIP sampling is consistent with the sequential that sends data;
Step 400: with the data that sample and the Data Comparison of transmission, whether test VIP works.When the data of the data that sample and transmission are compared, only need in the data reading to two of two files array, these two arrays be compared.Also can in FPGA, embed the ARM9 processor, the data that collect be deposited in certain address field of memory, begin comparison from the first address that sends data and image data during contrast.
The present invention can realize any digital circuit flexibly, breaks away from the interference of simulating signal, reduces the constraint that is limited by special chip, assists the FT test of chip to be measured.
Claims (2)
1. based on the FT method of testing of the VIP module of FPGA, this VIP module is the vision signal input processor, it is characterized in that: comprise the steps:
Step 100: one of design sends data module in FPGA;
Step 200: with the VSYNC negate of LCDC, as sending the sequential that data module sends data described in the FPGA;
Send the data that data module sends CCIR656 or YUV422 form described in the step 300:FPGA, the sequential of VIP module samples is consistent with the sequential that sends data;
Step 400: with the data that sample and the Data Comparison of transmission, whether test VIP works; When in the described step 400 data of the data that sample and transmission being compared, only need to read into the data of the data that sample and transmission respectively in two arrays, these two arrays are compared.
2. based on the FT method of testing of the VIP module of FPGA, this VIP module is the vision signal input processor, it is characterized in that: comprise the steps:
Step 100: one of design sends data module in FPGA;
Step 200: with the VSYNC negate of LCDC, as sending the sequential that data module sends data described in the FPGA;
Send the data that data module sends CCIR656 or YUV422 form described in the step 300:FPGA, the sequential of VIP module samples is consistent with the sequential that sends data;
Step 400: with the data that sample and the Data Comparison of transmission, whether test VIP works;
When in the described step 400 data of the data that sample and transmission being compared, in FPGA, embed the ARM9 processor, the data that sample are deposited in certain address field of memory, begin comparison from the data that send and the first address that samples data during contrast.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010555392 CN102096038B (en) | 2010-11-23 | 2010-11-23 | FPGA (Field Programmable Gate Array) based FT (Functional Test) method of VIP (Video Input Processor) module |
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| CN 201010555392 CN102096038B (en) | 2010-11-23 | 2010-11-23 | FPGA (Field Programmable Gate Array) based FT (Functional Test) method of VIP (Video Input Processor) module |
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| CN102096038A CN102096038A (en) | 2011-06-15 |
| CN102096038B true CN102096038B (en) | 2013-01-16 |
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| CN103093713B (en) * | 2011-10-31 | 2016-03-09 | 安凯(广州)微电子技术有限公司 | A kind of chip verification method based on FPGA, Apparatus and system |
| CN103377103B (en) * | 2012-04-28 | 2017-10-03 | 珠海格力电器股份有限公司 | Data storage method of testing, apparatus and system |
Citations (2)
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| CN1979187A (en) * | 2005-12-07 | 2007-06-13 | 比亚迪股份有限公司 | Testing device of multi-drive-mode LCD drive circuit and testing method |
| CN201269958Y (en) * | 2008-10-17 | 2009-07-08 | 天马微电子股份有限公司 | Test apparatus for liquid crystal display |
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| US6999051B2 (en) * | 2003-06-11 | 2006-02-14 | Toppoly Optoelectronics Corp. | Light-on aging test system for flat panel display |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979187A (en) * | 2005-12-07 | 2007-06-13 | 比亚迪股份有限公司 | Testing device of multi-drive-mode LCD drive circuit and testing method |
| CN201269958Y (en) * | 2008-10-17 | 2009-07-08 | 天马微电子股份有限公司 | Test apparatus for liquid crystal display |
Non-Patent Citations (2)
| Title |
|---|
| 安吉宇，等.基于FPGA的TFT LCD快检信号源的设计.《自动化仪表》.2008,(第2期),全文. * |
| 郑国惠,等.一种基于FPGA 的误码测试仪.《浙江工业大学学报》.2005,第33卷(第5期),全文. * |
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Address after: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Patentee after: FUZHOU ROCKCHIP ELECTRONICS CO., LTD. Address before: 350000 Fuzhou Gulou District, Fujian, software Avenue, building 89, No. 18 Patentee before: Fuzhou Rockchip Semiconductor Co., Ltd. |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |