CN102082570B - A kind of clock circuit and the method that clock signal is provided - Google Patents
A kind of clock circuit and the method that clock signal is provided Download PDFInfo
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- CN102082570B CN102082570B CN201010573314.2A CN201010573314A CN102082570B CN 102082570 B CN102082570 B CN 102082570B CN 201010573314 A CN201010573314 A CN 201010573314A CN 102082570 B CN102082570 B CN 102082570B
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Abstract
The embodiment provides a kind of clock circuit and the method that clock signal is provided, relate to circuit engineering field, invent for effectively optimizing circuit performance.Described clock circuit, including: self-adaptation clock produces circuit, for output adaptive clock signal；Self-adaptation clock drive circuit, works under driving at described self-adaptation clock signal, described self-adaptation clock drive circuit the highest can operating frequency more than or equal to the frequency of described self-adaptation clock signal；When the working condition of described self-adaptation clock drive circuit changes, the the highest of described self-adaptation clock drive circuit can operating frequency change, described self-adaptation clock produces the frequency of self-adaptation clock signal of circuit output and changes, and the frequency change of described self-adaptation clock signal with described the highest can operating frequency change direction consistent.The present invention can be used in design and the making of digital circuit.
Description
Technical field
The present invention relates to circuit engineering field, particularly relate to a kind of clock circuit and clock letter is provided
Number method.
Background technology
Generally, digital integrated electronic circuit can reach the highest can operating frequency Fmax with
Circuit physical characteristic P (by manufacturing process, the factor impact such as aging), running voltage V and work temperature
Degree T-phase is closed, it may be assumed that Fmax=f (P, V, T).
Along with digital integrated electronic circuit manufactures constantly reducing of live width, on the one hand, chip manufacturing process
Randomness increase, design identical circuit after manufacturing, circuit physical characteristic P is distributed
Wider；On the other hand, the Fmax of Same Physical circuit is for parameters such as voltage V and temperature T
Change more sensitive, above two aspects all cause the highest of digital integrated electronic circuit can operating frequency
Fmax is distributed in wider range.
At present, the clock source used by digital integrated electronic circuit, i.e. clock generation circuit, whether set
Put the crystal outside circuit chip, crystal oscillator, TCXO (Temperature Compensate X ' tal
(crystal) Oscillator, temperature compensating type quartz oscillator), or chip internal
(Delay locked loop, time delay is locked for PLL (Phase Lock Loop, phaselocked loop), DLL
Determine loop), frequency dividing circuit etc., all with frequency stable as target, i.e. in circuit physical characteristic,
Operating temperature, keeps output clock signal as far as possible under the different parameters distribution occasion such as running voltage
Frequency constant.
But, scattered at Parameter Conditions such as circuit physical characteristic, operating temperature, running voltages
In the case of, it is desirable to digital integrated electronic circuit works under constant frequency, is necessary for this digital integration
The operating frequency of circuit is set in the most workable frequency under worst parameter with the circuit ensured
Steady operation, such as, is set in maximum operating temperature by the operating frequency of this digital integrated electronic circuit,
Work frequency under minimum running voltage or the worst circuit physical characteristic (production technology as the worst)
Rate.Due to digital integrated electronic circuit under canonical parameter the highest can operating frequency far above set
Operating frequency under the most severe parameter, therefore, this mode limits digital integrated electronic circuit potentiality
Performance, constrain the performance of digital integrated electronic circuit, also will cause the power consumption of digital integrated electronic circuit
Increase.
Summary of the invention
Embodiments of the invention provide a kind of clock circuit and the method providing clock signal, it is possible to
Effectively optimize circuit performance.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
A kind of clock circuit, including:
Self-adaptation clock produces circuit, for output adaptive clock signal；
Self-adaptation clock drive circuit, works under driving at described self-adaptation clock signal,
Described self-adaptation clock drive circuit the highest can operating frequency more than or equal to described self adaptation time
The frequency of clock signal；
Wherein, when the working condition of described self-adaptation clock drive circuit changes, described
The the highest of self-adaptation clock drive circuit can operating frequency change, and described self-adaptation clock produces
The frequency of the self-adaptation clock signal of raw circuit output changes, and described self-adaptation clock letter
Number frequency change direction with described the highest can operating frequency change direction consistent.
A kind of method that clock signal is provided, including:
Self-adaptation clock produces circuit output adaptive clock signal, so that self-adaptation clock drives
Circuit works under described self-adaptation clock signal drives, described self-adaptation clock drive circuit
The highest can operating frequency more than or equal to the frequency of described self-adaptation clock signal；
When the working condition of described self-adaptation clock drive circuit changes, described self adaptation
The the highest of clock driver circuit can operating frequency change, and described self-adaptation clock produces circuit
The frequency of the self-adaptation clock signal of output changes, and the frequency of described self-adaptation clock signal
The change direction of rate with described the highest can operating frequency change direction consistent.
The embodiment of the present invention provide clock circuit and provide clock signal method, for described from
Adapting to clock driver circuit provides frequency to change and adaptive change according to the working condition of this circuit
Clock signal, say, that, it is possible to make described self-adaptation clock drive circuit be operated at any time
Equal or close to this circuit the highest can in operating frequency, therefore, it is possible to give full play to described from
Adapt to the potentiality of clock driver circuit, hence it is evident that improve the process of described self-adaptation clock drive circuit
Speed, and then effectively optimize the performance of described self-adaptation clock drive circuit.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below
The accompanying drawing used required in embodiment or description of the prior art will be briefly described, aobvious and
Easily insight, the accompanying drawing in describing below is only some embodiments of the present invention, for this area
From the point of view of those of ordinary skill, on the premise of not paying creative work, it is also possible to according to this
A little accompanying drawings obtain other accompanying drawing.
A kind of logical structure schematic diagram of the clock circuit that Fig. 1 provides for the embodiment of the present invention.
The another kind of logical structure schematic diagram of the clock circuit that Fig. 2 provides for the embodiment of the present invention.
The self-adaptation clock of the clock circuit that Fig. 3 provides for the embodiment of the present invention produces the one of circuit
Plant circuit diagram；
The self-adaptation clock of the clock circuit that Fig. 4 provides for the embodiment of the present invention produces the another of circuit
A kind of circuit diagram；
A kind of circuit postponing regulation circuit of the clock circuit that Fig. 5 provides for the embodiment of the present invention
Schematic diagram；
The another kind of electricity postponing regulation circuit of the clock circuit that Fig. 6 provides for the embodiment of the present invention
Road schematic diagram；
The another kind of logical structure schematic diagram of the clock circuit that Fig. 7 provides for the embodiment of the present invention；
Fig. 8 is a kind of logical structure schematic diagram of the clock circuit shown in Fig. 7；
Fig. 9 is the another kind of logical structure schematic diagram of the clock circuit shown in Fig. 7；
The another kind of logical structure schematic diagram of the clock circuit that Figure 10 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, to the technical side in the embodiment of the present invention
Case is clearly and completely described, it is clear that described embodiment is only the present invention one
Divide embodiment rather than whole embodiments.Based on the embodiment in the present invention, this area is general
The every other embodiment that logical technical staff is obtained under not making creative work premise,
Broadly fall into the scope of protection of the invention.
As it is shown in figure 1, the clock circuit that the embodiment of the present invention provides, this clock circuit is numeral
Circuit, including:
Self-adaptation clock produces circuit 1, for output adaptive clock signal；
Self-adaptation clock drive circuit 2, works under driving at described self-adaptation clock signal,
The the highest of self-adaptation clock drive circuit 2 operating frequency can be more than or equal to described self-adaptation clock
The frequency of signal；
When the working condition of self-adaptation clock drive circuit 2 changes, self-adaptation clock drives
The the highest of galvanic electricity road 2 can operating frequency change, and self-adaptation clock produces circuit 1 output
The frequency of self-adaptation clock signal changes, and the change of the frequency of described self-adaptation clock signal
Change direction with described the highest can operating frequency change direction consistent, the most simultaneously increase or reduce simultaneously,
Ensure the functional reliability of self-adaptation clock drive circuit 2.
The clock circuit that the embodiment of the present invention provides, it is possible to carry for self-adaptation clock drive circuit 2
Working condition for this circuit of frequency following changes and the clock signal of adaptive change, namely
Say, it is possible to make self-adaptation clock drive circuit 2 be operated in the Gao Kegong close to this circuit at any time
On working frequency, therefore, it is possible to give full play to the potentiality of self-adaptation clock drive circuit 2, hence it is evident that
Improve the processing speed of self-adaptation clock drive circuit 2, and then effectively optimization self-adaptation clock drives
The performance on galvanic electricity road 2.
Concrete, the working condition of self-adaptation clock drive circuit 2 includes that self-adaptation clock drives
Circuit physical characteristic, running voltage and operating temperature etc. when circuit 2 works, self-adaptation clock
The working condition of drive circuit 2 changes and includes the circuit thing of self-adaptation clock drive circuit 2
At least one in reason characteristic, running voltage and operating temperature changes, when in above-mentioned three kinds
At least one when changing, self-adaptation clock drive circuit 2 the highest can operating frequency also
Change therewith, self-adaptation clock produce circuit 1 output self-adaptation clock signal frequency also with
Change.
Owing to self-adaptation clock produces the frequency of the self-adaptation clock signal of circuit 1 output along with certainly
Adapt to the change of working condition of clock driver circuit 2 and change, therefore, the present embodiment time
Clock circuit, self-adaptation clock produces the circuit physical of circuit 1 and self-adaptation clock drive circuit 2
Characteristic, running voltage are identical with operating temperature or close, concrete, in clock circuit, from
Adapt to clock generation circuit 1 close with the physical location of self-adaptation clock drive circuit 2, and belong to
In identical voltage domain, same or like with the operating temperature both ensureing, running voltage is identical.
Additionally, it is preferred that, self-adaptation clock produces circuit 1 and self-adaptation clock drive circuit 2 by belonging to
Base unit in same basic cell library forms.So, both circuit things can either be ensured
Reason characteristic is same or like, meanwhile, can make both performances, such as delay performance etc., and
Similar to the sensitivity that working condition changes etc., optimize self-adaptation clock drive circuit 2 further
Performance.
It should be noted that base unit storehouse is the basis of the design of large-scale digital ic
Module, it is achieved such as phase inverter, and logic, or logic, the basis of the Digital Designs such as depositor is patrolled
Volume functional circuit, simultaneously base unit storehouse by abstract for the impact of manufacturing process be the parameter of correspondence,
Facilitate design and the physics realization of extensive logic circuit.Identical manufacturing process can have not
The multiple base unit storehouse provided with supplier, and different base unit storehouses becomes with working condition
Change the possible difference of the delay caused bigger.
It should be noted that the clock circuit of the embodiment of the present invention, along with circuit physical characteristic,
Running voltage and/or operating temperature etc. change, and self-adaptation clock produces the self adaptation of circuit 1 output
The frequency of clock signal changes, and is substantially produced the physics of circuit 1 by self-adaptation clock
Character determines, the change of above-mentioned working condition will cause self-adaptation clock to produce letter in circuit 1
Number transmission speed change, such as, when self-adaptation clock produce circuit occur aging time,
When namely circuit physical characteristic changes, in this circuit, signaling rate changes,
So that the frequency that self-adaptation clock produces the self-adaptation clock signal that circuit 1 exports changes.
It is pointed out that to make the stable normal work of self-adaptation clock drive circuit 2,
Self-adaptation clock produces circuit 1 and can meet: in each permission of self-adaptation clock drive circuit 2
Working condition under, i.e. in particular job voltage, operating temperature and circuit physical characteristic, adaptive
The frequency answering the clock signal that clock generation circuit 1 exports is respectively less than self-adaptation clock drive circuit
The highest can operating frequency；And, when the working condition of self-adaptation clock drive circuit 2 becomes
During change, self-adaptation clock produce circuit 1 output self-adaptation clock signal frequency variation
With self-adaptation clock drive circuit 2 the highest can the variable quantity of operating frequency close.
Meet above-mentioned condition to make self-adaptation clock produce circuit 1, carry out the embodiment of the present invention
When the design of the clock circuit provided or configuration, concrete, can be designed according to following rule
And configuration, including:
Self-adaptation clock to be made produces the working environment of circuit 1 and self-adaptation clock drive circuit 2
As close possible to, concrete, both can be made close at physical location, and belong to identical voltage zone
Territory；
And, self-adaptation clock to be made produces the working cycle of the output clock signal of circuit 1,
More than the critical path of this drive circuit under all of working condition of self-adaptation clock drive circuit 2
Electrical path length, and close with critical path depth as far as possible after staying certain surplus.Here and this
In inventive embodiments, critical path depth means the minimum can born under all of working condition
Working cycle.The critical path depth of self-adaptation clock drive circuit can be on the design rank of this circuit
Section, uses the methods such as STA, SPICE emulation to obtain；
And, self-adaptation clock to be made produce circuit 1 output clock signal working cycle and
The difference (surplus) of the critical path depth of self-adaptation clock drive circuit 2 is more than following portion
/ and, including:
Under the conditions of the different operating of self-adaptation clock drive circuit 2, self-adaptation clock produces circuit 1
The maximum difference of working cycle and described critical path depth of output clock signal；
Working condition causes the frequency change of clock signal to accept with self-adaptation clock drive circuit 2
Before the frequency change of clock signal, self-adaptation clock produces the output clock signal of circuit 1
The difference of working cycle and described critical path depth；
When the described critical path depth that chip internal characteristic or working condition difference cause and self adaptation
Clock produces the difference of the working cycle of the output clock signal of circuit 1.
In order to make those skilled in the art be better understood by the technical scheme of the embodiment of the present invention,
Below by specific embodiment, the clock circuit of the embodiment of the present invention is carried out the most in detail
Explanation.
As in figure 2 it is shown, the clock circuit of the present embodiment, it it is the circuit of an integrated several functions
System, including: self-adaptation clock produces circuit 1 and self-adaptation clock drive circuit 2, also includes
Ordinary clock circuit 3 and other operating circuits 4；
Wherein, self-adaptation clock produces circuit 1 and provides adaptive for self-adaptation clock drive circuit 2
Answering clock signal, the frequency of described self-adaptation clock signal is less than self-adaptation clock drive circuit 2
The highest can operating frequency, when the working condition of self-adaptation clock drive circuit 2 changes,
The the highest of self-adaptation clock drive circuit 2 can operating frequency change, and self-adaptation clock produces
In circuit 1, the transmission speed of signal changes so that described self-adaptation clock generation circuit is defeated
The frequency of the self-adaptation clock signal gone out changes, and the frequency of described self-adaptation clock signal
Change direction with described the highest can operating frequency change direction consistent；
Ordinary clock circuit 3 provides the clock signal of fixed frequency for other operating circuits 4.
In concrete circuit, self-adaptation clock produces circuit 1 and self-adaptation clock drive circuit 2
Being in a synchronous circuit island, ordinary clock circuit 3 and other operating circuits 4 are in another
In individual synchronous circuit island, each synchronous circuit island is pertaining only to a voltage domain.And, self adaptation
The synchronous circuit island at clock generation circuit 1 and self-adaptation clock drive circuit 2 place with common time
Clock circuit 3 and the most asynchronous isolation in synchronous circuit island at other operating circuit 4 places.
It should be noted that in digital circuit, same clock-driven circuit belong to same
One clock zone.If it is multiple to drive that digital circuit have employed multiple clock not having a phase relation
Different submodules, then need to use asynchronous process at the interactive interface of these submodules, the most different
Step isolation, it is ensured that the correct transmission of signal cross clock domain, after asynchronous isolation, by same
Individual clock-driven circuit part (the most same clock zone) is referred to as synchronous circuit island, if whole
Circuit is driven by a clock, then need not asynchronous isolation, it is also possible to regarded as by whole circuit
One synchronous circuit island.
It is understood that Fig. 1 is only the logical structure schematic diagram of the present embodiment, time actual
In clock circuit, it may include the synchronous circuit island of the most asynchronous multiple isolation.
In the present embodiment, self-adaptation clock produces circuit 1 and self-adaptation clock drive circuit 2
Physical location close, and belong to identical voltage domain, i.e. both operating temperatures are identical or connect
Closely, running voltage is identical.So, the operating temperature of self-adaptation clock drive circuit 2 and/or work
When making voltage change, self-adaptation clock produces the operating temperature of circuit 1 and/or changing of running voltage
Becoming close or identical with self-adaptation clock drive circuit 2, self-adaptation clock produces circuit 1 can
The change of the working condition of accurate perception self-adaption clock driver circuit 2.
In the present embodiment, it is resonant ring circuit that self-adaptation clock produces circuit 1, utilizes from impulsing
Swinging output clock signal, the progression of resonant ring can be according to the key of self-adaptation clock drive circuit 2
Path determines, to ensure that self-adaptation clock produces the self-adaptation clock signal of circuit 1 output
Self-adaptation clock drive circuit 2 is made normally to work.And, it is preferred that form described resonant ring electricity
The base unit on road and the base unit forming self-adaptation clock drive circuit 2 belong to identical base
Plinth cell library, say, that if self-adaptation clock drive circuit 2 is formed by gate, described
Resonant ring circuit is the gate resonant ring circuit of same cell library.So that both circuit physical
Characteristic is same or like, meanwhile, can make both performances, such as delay performance etc., and right
The sensitivity that working condition changes is similar, along with self-adaptation clock drive circuit 2 working condition
Changing, self-adaptation clock produces the time delay change of circuit 1 and self-adaptation clock drive circuit 2
Ratio is close, when self-adaptation clock produces frequency and the self adaptation of the clock signal of circuit 1 output
Under clock drive circuit 2 current operating conditions the highest can the difference of operating frequency less, the most excellent
Change the performance of self-adaptation clock drive circuit 2.Concrete, as it is shown on figure 3, self-adaptation clock
Producing circuit 1 is the phase inverter resonant ring circuit including phase inverter resonant ring 11.
As a kind of improvement of the present embodiment, as shown in Figure 4, self-adaptation clock produces circuit 1
Resonant ring circuit in also include delay adjustment circuit 12, self-adaptation clock produces circuit 1
Self-adaptation clock signal exports after delay adjustment circuit 12 time delay and drives to described self-adaptation clock
Circuit.This is because, the self-adaptation clock drive circuit 2 obtained at the clock circuit design initial stage
Critical path depth there may be difference with domain after realizing, and by delay adjustment circuit 12 energy
Enough work frequencies that even after circuit manufactures, self-adaptation clock is produced after domain realizes circuit 1
Point is adjusted, and produces circuit 1 with coupling self-adaptation clock the most under various operating conditions
Output frequency and the highest of self-adaptation clock drive circuit 2 can operating frequency.With resonant ring electricity
Road is as a same reason, it is preferred that form base unit and the formation self adaptation of delay adjustment circuit 12
The base unit of clock driver circuit belongs to identical base unit storehouse.
Such as, delay adjustment circuit 12 can be formed by the cascade of n level delay cell, and wherein n is big
In the integer of 0, delay adjustment circuit 12 by control clock signal the described delay of process single
The progression of unit, and obtain different delay times.Concrete, in one embodiment of the present of invention
In, delay adjustment circuit 12 can be as it is shown in figure 5, be patrolled by n (wherein n is more than or equal to 1) level
Collecting gate circuit 51 and two not gates connected 52 formation in parallel, each logic gates is equipped with control
End S [1] processed is to S [n], and input and outfan, and this delay adjustment circuit can be by joining
Put the input controlling end, adjust the progression of the logic gate of signal process, and obtain different
Delay time.Such as, when control line S [0] to S [n] is complete 1, this delay adjustment circuit 5
Having maximum delay, about 2n NAND gate adds the time delay of two not gates, when S [0] to S [n] is complete
When 0, this delay adjustment circuit 5 has minimum time delay, the time delay of about two NAND gate, controls end
Other configuration time delay between minimum and maximum time delay.
In another embodiment of the present invention, delay adjustment circuit 12 can as shown in Figure 6, should
Circuit include multiplex selector 53, multiplexing selector 53 include control end and two defeated
Enter end；Two inputs of multiplexing selector 53 are respectively with the door list with two different delayed time
Unit 54 and 55 is linked, and multiplexing selector 53 is provided with control end S, can be by configuring
The input of the control end S of multiplexing selector 53, selects clock signal by different delayed time
Gate cell, thus adjust signal from the delay time being input to output.This regulation of electrical circuit step-length is relatively
Carefully, and can to obtain different delayed time poor by replacing different gate cells 54 and 55.Separately
Outward, series connection delay adjustment circuit shown at least two Fig. 6 can be as having prolonging of different delayed time
Time regulation circuit.
It is, of course, understood that in yet another embodiment of the present invention, delay adjustment electricity
Road 12 is by the delay adjustment circuit shown at least one Fig. 5 and the delay adjustment circuit described in Fig. 6
Series connection is formed.
Self-adaptation clock drive circuit is the most significantly changed when artificial or the most disposable
During running voltage, self-adaptation clock produces circuit 1 and exports the frequency change of clock signal with adaptive
The frequency change answering the clock signal that clock driver circuit 2 experiences is asynchronous, thus affects this
Stable and the reliability of the clock circuit of embodiment, accordingly, as a kind of improvement of the present embodiment,
As it is shown in fig. 7, the clock circuit of the present embodiment also includes clock control circuit 6, it is possible to efficient solution
Certainly the problems referred to above, are effectively ensured the reliability of clock circuit.
Concrete, as shown in Figure 8, clock control circuit 6 is asynchronous clock switching circuit, its
Input produces circuit 1 respectively with self-adaptation clock and ordinary clock produces circuit 3 and is connected,
Its outfan, with from using clock driver circuit 2 to be connected, is used for driving electricity at self-adaptation clock
Before the running voltage on road 2 changes, the clock signal of self-adaptation clock drive circuit is switched to
Ordinary clock produces the clock signal of the fixing safety frequency that circuit 3 provides, at self-adaptation clock
After the running voltage of drive circuit changes and stablizes, by the clock of self-adaptation clock drive circuit 2
Signal switches to self-adaptation clock to produce the clock signal that circuit 1 provides.This asynchronous clock switches
Circuit can use asynchronous clock switching circuit commonly known in the art, and the present embodiment does not limits.
Wherein, trouble free service frequency is defined as under any working condition, self-adaptation clock drive circuit 2
The fixed clock frequency that all can normally work.
Concrete, as it is shown in figure 9, clock control circuit 6 is clock gating circuit, its input
Hold and be connected with self-adaptation clock generation circuit 1, its outfan and self-adaptation clock drive circuit 2
It is connected, before changing in the running voltage of self-adaptation clock drive circuit 2, stops certainly
Adapt to the clock signal of clock driver circuit 2, at the work electricity of self-adaptation clock drive circuit 2
After pressure changes and be stable, the clock signal of self-adaptation clock drive circuit 2 is switched to self adaptation
The clock signal that clock generation circuit 1 provides.This clock gating circuit can use in prior art
Known clock gating circuit, the present embodiment does not limits.
Further, as a kind of improvement of the present embodiment, as shown in Figure 10, the present embodiment
Clock circuit also includes performance monitoring module 101 and voltage control module 102, and wherein, performance is supervised
Control module 101 is connected with self-adaptation clock drive circuit 2, drives for monitoring adaptive clock
The performance parameter on galvanic electricity road 2, is carried out according to described performance parameter instruction energy supply control module 102
The adjustment of running voltage, thus Indirect method circuit work frequency, make self-adaptation clock produce electricity
The frequency of the clock signal of road 1 output according to the adaptive change of change of described running voltage,
Under the effect of above-mentioned two modules, it is possible to fully regulate the performance of circuit, effectively reduce self adaptation
The energy consumption of clock driver circuit 2.
Concrete, as a example by self-adaptation clock drive circuit 2 is as CPU, it is assumed that current task
CPU usage ratio relatively low only 20%, now can reduce running voltage and the work frequency of CPU
Rate makes same task complete with lower energy consumption.Performance monitoring module 101 can monitoring CPU
Occupancy, send semaphore request voltage control module 102 when occupancy is too low and turn down work
Voltage, after running voltage is turned down, self-adaptation clock produces circuit 1 and automatically lowers frequency,
The CPU usage made rises, and repeats this process until CPU usage meets requirement, and makes certainly
Adapt to the energy consumption optimization of clock driver circuit 2.
Wherein, when self-adaptation clock drive circuit 2 is CPU, the performance parameter that can monitor is
CPU usage or do-nothing instruction number；When self-adaptation clock drive circuit 2 is GPU, can supervise
The number that performance parameter is picture triangle of control or 3D figure frame per second；When self-adaptation clock drives electricity
When road 2 is video coder-decoder, the performance parameter that can monitor is coding and decoding video frame per second；When adaptive
When answering clock driver circuit 2 for DSP, the performance parameter that can monitor is in the unit time specific
Business performance；Certainly, if desired for the frequency of directly control self-adaptation clock drive circuit 2, also
Can be using frequency as the performance parameter monitored.
Corresponding with preceding method, the embodiment of the present invention additionally provides a kind of clock signal of providing
Method, including:
Self-adaptation clock produces circuit output adaptive clock signal, so that self-adaptation clock drives
Circuit works under described self-adaptation clock signal drives, described self-adaptation clock drive circuit
The highest can operating frequency more than or equal to the frequency of described self-adaptation clock signal；
When the working condition of described self-adaptation clock drive circuit changes, described self adaptation
The the highest of clock driver circuit can operating frequency change, and described self-adaptation clock produces circuit
The frequency of the self-adaptation clock signal of output changes, and the frequency of described self-adaptation clock signal
The change direction of rate with described the highest can operating frequency change direction consistent.
The method of the offer clock signal that the embodiment of the present invention provides, drives for described self-adaptation clock
Galvanic electricity road provides frequency to change and the clock of adaptive change letter according to the working condition of this circuit
Number, say, that, it is possible to make described self-adaptation clock drive circuit be operated at any time close to this electricity
The the highest of road can be in operating frequency, therefore, it is possible to give full play to described self-adaptation clock to drive electricity
The potentiality on road, hence it is evident that improve the processing speed of described self-adaptation clock drive circuit, and then effectively
Optimize the performance of self-adaptation clock drive circuit.
Concrete, the working condition of self-adaptation clock drive circuit includes that self-adaptation clock drives electricity
Circuit physical characteristic, running voltage and operating temperatures the etc. during work of road, self-adaptation clock drives
The working condition of circuit change include self-adaptation clock drive circuit circuit physical characteristic,
At least one in running voltage and operating temperature changes, at least in above-mentioned three kinds
When kind changes, the highest of self-adaptation clock drive circuit can operating frequency change the most therewith,
The frequency of the self-adaptation clock signal that self-adaptation clock produces circuit 1 output changes the most therewith.
Further, when artificial or disposably quickly significantly change described self adaptation automatically
During the running voltage of clock driver circuit, the frequency of described self-adaptation clock signal and described the highest
Can operating frequency all become according to the change of the running voltage of described self-adaptation clock drive circuit
Change, the frequency change of described self-adaptation clock drive circuit output clock signal and self-adaptation clock
The frequency change of the clock signal that drive circuit is experienced is asynchronous, affects self-adaptation clock and drives
The functional reliability of circuit.For ensureing the functional reliability of self-adaptation clock drive circuit, in institute
Before stating the running voltage change of self-adaptation clock drive circuit, the offer clock letter of the present embodiment
Number method also include:
The clock signal of described self-adaptation clock drive circuit is switched to fixing safety frequency time
Clock signal or stop the clock signal of described self-adaptation clock drive circuit；
Change the running voltage of described self-adaptation clock drive circuit；
After described stable operating voltage after the change by described self-adaptation clock drive circuit time
Clock signal switches to described self-adaptation clock signal.
Further, the method for the offer clock signal of the present embodiment, also include:
Monitor the performance parameter of described self-adaptation clock drive circuit；
According to described performance parameter, carry out the running voltage of described self-adaptation clock drive circuit
Adjust, the frequency of described self-adaptation clock signal and described the highest can operating frequency all according to described
The adjustment of running voltage and change.
So, it is operated the adjustment of voltage according to performance parameter, thus Indirect method self adaptation
The operating frequency of clock driver circuit, it is possible to effectively reduce described self-adaptation clock drive circuit
Energy consumption, optimizes the performance of self-adaptation clock drive circuit.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is also
Being not limited to this, any those familiar with the art is at the technology model that the invention discloses
In enclosing, change can be readily occurred in or replace, all should contain within protection scope of the present invention.
Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (10)
1. a clock circuit, it is characterised in that including:
Self-adaptation clock produces circuit, for output adaptive clock signal；
Self-adaptation clock drive circuit, works under driving at described self-adaptation clock signal,
Described self-adaptation clock drive circuit the highest can operating frequency more than or equal to described self adaptation time
The frequency of clock signal,
Wherein, described self-adaptation clock drive circuit and self-adaptation clock generation circuit meet:
Self-adaptation clock generation circuit connects with the physical location of described self-adaptation clock drive circuit
Closely, and belong to identical voltage domain；
Described self-adaptation clock produces circuit and described self-adaptation clock drive circuit by belonging to identical
The base unit composition in base unit storehouse；And
Described clock driver circuit and described self-adaptation clock produce circuit respectively by belonging to same base
The gate composition of plinth cell library,
Wherein, when the working condition of described self-adaptation clock drive circuit changes, described
The the highest of self-adaptation clock drive circuit can operating frequency change, and described self-adaptation clock produces
The frequency of the self-adaptation clock signal of raw circuit output changes, and described self-adaptation clock letter
Number frequency change direction with described the highest can operating frequency change direction consistent.
Clock circuit the most according to claim 1, it is characterised in that
The working condition of described self-adaptation clock drive circuit changes when including described self adaptation
At least one in circuit physical characteristic, running voltage and the operating temperature of clock drive circuit occurs
Change.
Clock circuit the most according to claim 1, it is characterised in that
It is the resonant ring circuit being made up of gate that described self-adaptation clock produces circuit, utilizes certainly
Impulse and swing output adaptive clock signal.
Clock circuit the most according to claim 1, it is characterised in that described self adaptation
The resonant ring circuit of clock generation circuit also includes delay adjustment circuit, during described self adaptation
Clock signal exports to described self-adaptation clock drive circuit after described delay adjustment circuit time delay.
Clock circuit the most according to claim 4, it is characterised in that described time delay is adjusted
Economize on electricity route n level delay cell cascade forms, and wherein n is greater than the integer of 0, described time delay
Regulation circuit by control clock signal the progression of described delay cell of process, and obtain not
Same delay time.
Clock circuit the most according to claim 5, it is characterised in that
Described n level delay cell includes that n-level logic gate circuit, every grade of logic gates are equipped with
Control end, input and outfan；
Described delay adjustment circuit controls the input of end by configuring, and regulation clock signal is passed through
The progression of logic gates, and obtain different delay times.
Clock circuit the most according to claim 4, it is characterised in that described time delay is adjusted
Economize on electricity road includes multiplexing selector, and described multiplexing selector includes controlling end and two
Input；
Two inputs of described multiplexing selector respectively with the delay list of two different delayed time
Unit connects, and this delay adjustment circuit is by configuring the defeated of the control end of described multiplexing selector
Enter, select the described delay cell that clock signal is passed through, thus obtain different delay times.
Clock circuit the most according to claim 1, it is characterised in that also include clock
Control circuit, before changing in the running voltage of described self-adaptation clock drive circuit, will
The clock signal of described self-adaptation clock drive circuit switches to the clock signal of fixing safety frequency
Or stop the clock signal of described self-adaptation clock drive circuit, described self adaptation after the change
After the stable operating voltage of clock driver circuit, the clock of described self-adaptation clock drive circuit is believed
Described self-adaptation clock number is switched to produce the clock signal that circuit provides.
Clock circuit the most according to claim 1, it is characterised in that also include performance
Monitoring module and voltage control module, wherein, described performance monitoring module be used for monitoring described from
Adapt to the performance parameter of clock driver circuit, indicate described Control of Voltage according to described performance parameter
Module is operated the adjustment of voltage, so that described self-adaptation clock produces the clock of circuit output
The frequency of signal is according to the adaptive change of change of described running voltage.
Clock circuit the most according to claim 1, it is characterised in that described adaptive
Answer clock driver circuit to include central processing unit, graphic process unit, digital signal processor, compile
Code circuit, decoding circuit or hardware accelerator.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010573314.2A CN102082570B (en) | 2010-12-03 | A kind of clock circuit and the method that clock signal is provided | |
| US13/311,069 US8570087B2 (en) | 2010-12-03 | 2011-12-05 | Circuitry for clock and method for providing clock signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010573314.2A CN102082570B (en) | 2010-12-03 | A kind of clock circuit and the method that clock signal is provided |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102082570A CN102082570A (en) | 2011-06-01 |
| CN102082570B true CN102082570B (en) | 2016-11-30 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794587A (en) * | 2002-08-27 | 2006-06-28 | 富士通株式会社 | Clock generator for generating accurate and low-jitter clock |
| CN101588165A (en) * | 2008-05-21 | 2009-11-25 | 联发科技股份有限公司 | Voltage controlled oscillators and phase-frequency locked loop circuit using the same |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794587A (en) * | 2002-08-27 | 2006-06-28 | 富士通株式会社 | Clock generator for generating accurate and low-jitter clock |
| CN101588165A (en) * | 2008-05-21 | 2009-11-25 | 联发科技股份有限公司 | Voltage controlled oscillators and phase-frequency locked loop circuit using the same |
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Effective date of registration: 20230909 Address after: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee after: HUAWEI TECHNOLOGIES Co.,Ltd. Patentee after: Beijing Huawei Digital Technology Co.,Ltd. Address before: 518129 headquarters building of Bantian HUAWEI base, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |