CN102074574A - CMOS Device Stacked Gate Formation Method and Structure - Google Patents

Abstract

The present invention proposes a gate dielectric structure of a metal oxide semiconductor MOS device, comprising: an interface layer film formed on the surface of a semiconductor substrate; and at least two insulating films formed on the surface of the interface layer film, wherein , each of the at least two insulating films has a different elemental composition and/or a different concentration than other adjacent insulating films, and the interface layer film and the at least two insulating films are optimized for annealing process, the optimized annealing process is related to the element composition and/or concentration of the interface layer film and the at least two insulating films, so as to achieve the desired distribution of the elements and/or concentration. The present invention forms the stacked gate dielectric structure of the MOS device by depositing multiple layers of different material components or different concentrations of films in a certain order, and then uses an optimized annealing process to promote the various element groups in the stacked gate dielectric structure points and concentrations to achieve the ideal distribution state.

Description

CMOS Device Stacked Gate Formation Method and Structure

technical field

The invention relates to a method and structure for forming a semiconductor device, in particular to a method for forming a stacked gate dielectric of a CMOS device and its structure.

Background technique

In the decades since the development of microelectronics technology, logic chip manufacturers have been using SiO ₂ as the gate dielectric and heavily doped polysilicon as the gate electrode material when manufacturing MOS devices. However, as feature sizes continue to shrink, the _SiO2 gate dielectric in MOS transistors is approaching its limit. For example, in the 65nm process, the thickness of the _SiO2 gate has been reduced to 1.2nm, which is about 5 silicon atomic layers thick. If it continues to shrink, the leakage current and power consumption will increase sharply. At the same time, problems such as the diffusion of doped boron atoms caused by the polysilicon gate electrode, the polysilicon depletion effect, and the excessively high gate resistance will become more and more serious. For each technology generation of 32nm and below, problems such as the sharp increase in leakage current and power consumption will urgently need to be solved by the development of new materials, new processes, and new device structures.

In order to reduce leakage current and power consumption, an improved technique is to use a "high-k/metal gate" structure. At present, all major semiconductor companies in the world have started to develop the "high-k/metal gate" technology for the technology generation of 32nm and below. Intel disclosed that after using a high-k gate dielectric material, the leakage current of the device is reduced to one-tenth of the original, but at the same time, it also brings about the threshold voltage control problem of the MOS device. Since the MOS process requires both nMOS and pMOS devices, in order to maximize device performance, it is required that the threshold voltages of nMOS and pMOS devices be kept roughly equal in absolute value, and the value of the threshold voltage should be reduced as much as possible. Therefore, how to reduce the threshold voltage is an urgent problem to be solved.

At present, in order to reduce the threshold voltage of devices, it is the most direct, feasible and effective method to use suitable materials to adjust the effective work function. Studies have found that some elements, such as La, Yb, Dy and other rare earth elements and Al, Mg, etc., can shift the flat-band voltage and adjust the threshold voltage after being doped into high-k films or metal gate films, and, The distribution positions of these elements in the vertical direction of the entire gate dielectric will affect the adjustment capability of the threshold voltage. There are also some elements, such as N, Si, etc., that can improve the thermal stability of the film after doping into the high-k film. In addition, some elements will form a certain amount of charges or defects when they are close to the channel of the MOS device, which will greatly scatter the channel carriers, resulting in a decrease in carrier mobility, resulting in poor device performance. Degradation, such as N, Al, La, etc.

Therefore, in the new generation of high-k gate dielectric/metal gate technology, it is necessary to introduce some required elements at ideal positions, so as to improve the performance of the device.

Contents of the invention

In order to overcome the above-mentioned defects in the prior art, the performance of the MOS device is improved especially through the stacked gate dielectric structure of the MOS device and its forming method proposed by the present invention.

In order to achieve the above object, the present invention proposes a gate dielectric structure of a metal oxide semiconductor MOS device, comprising: an interface layer film formed on the surface of the semiconductor substrate; and at least two interfacial layer films formed on the surface of the interface layer film. Layers of insulating films, each insulating film comprising at least two elements, wherein each of the at least two insulating films has a different element composition and/or different concentration from other adjacent insulating films, and the The interface layer film and the at least two insulating films are subjected to an optimized annealing process, and the optimized annealing process is related to the elemental composition and/or concentration of the interface layer film and the at least two insulating films to achieve the desired The distribution of the elements and/or concentrations.

According to another aspect of the present invention, the present invention also provides a CMOS device, including the above-mentioned gate dielectric structure.

According to another aspect of the present invention, the present invention also proposes a method for forming the gate dielectric structure of the above-mentioned MOS device, including the following steps: forming an interface layer film on the surface of the semiconductor substrate; forming at least two insulating films, each insulating film comprising at least two elements, wherein each of the at least two insulating films has a different element composition and/or a different concentration than other adjacent insulating films; According to the element composition and/or concentration of the interface layer film and the at least two insulation films, an optimized annealing process is performed on the interface layer film and the at least two insulation films to achieve the desired elements and and/or distribution of concentrations.

The present invention forms the stacked gate dielectric structure of the MOS device by depositing multiple layers of different material components or different concentrations of films in a certain order, and then uses an optimized annealing process to promote the various element groups in the stacked gate dielectric structure points and concentrations to achieve the ideal distribution state. By controlling the distribution of various element components and concentrations in the stacked gate dielectric structure, it is possible to control the EOT (equivalent oxide thickness) of the MOS device, adjust the threshold voltage, increase the channel mobility, and reduce the gate Leakage current, etc., which can comprehensively improve the overall performance of MOS devices.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a gate dielectric structure of a MOS device proposed in an embodiment of the present invention;

2-5 are schematic diagrams of forming a gate stack structure of the present invention according to Embodiment 1 of the present invention;

6-11 are schematic diagrams of forming a gate stack structure of the present invention according to Embodiment 2 of the present invention;

12-15 are schematic diagrams of forming a gate stack structure of the present invention according to Embodiment 3 of the present invention;

16-18 are schematic diagrams of forming a gate stack structure of the present invention according to Embodiment 4 of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

The stacked gate dielectric structure of the MOS device proposed by the present invention is formed by depositing multiple layers (2-5 layers) of different material components or thin films with different concentrations in a certain order, and cooperates with the optimized annealing proposed by the present invention process, the optimized annealing process is related to the material composition and/or concentration of the above-mentioned material layer, so as to obtain the desired element and/or concentration distribution, thereby controlling the EOT of the MOS device, adjusting the threshold voltage, and improving the channel mobility , and reduce the gate leakage current, etc., to comprehensively improve the overall performance of the MOS device.

However, it should be noted that the focus of the present invention is to propose a gate dielectric structure, which has a plurality of thin films, each of which has a different material composition from its adjacent films or has the same material composition but has different concentration to achieve the desired distribution. According to the performance of the MOS device that needs to be promoted, each film may have different materials, different thicknesses or different concentrations, which need to be determined according to the performance that needs to be improved. The following embodiments of the present invention will introduce some methods for improving the performance of the MOS device. Examples, these examples are only to enable those skilled in the art to have a clearer understanding of the present invention, it does not mean that the present invention can only be realized through the following examples.

In addition, in the present invention, the performance of the MOS device can be improved through various methods, and these methods can be implemented alone or in combination. For example, in order to increase the dielectric constant of the high-k dielectric layer, La elements can be added to the dielectric layer. In addition, the distribution of La elements in the high-k dielectric layer can be controlled to reduce the effect of La elements on channel carriers. Scattering, thereby increasing the mobility of channel carriers. Or, doping Al elements to adjust the flat band voltage, so as to achieve the purpose of controlling the threshold voltage, at the same time, through the present invention, the control of Al elements will not diffuse too much to SiO ₂ or near the channel, thereby reducing the impact of Al elements on the channel load. Effects on flow rate, etc. It can be seen that there are many ways to realize the present invention, and the following examples are only preferred implementation modes for realizing the present invention, and those skilled in the art can also make many equivalent modifications, transformations or substitutions according to the thinking of the present invention, and these should all be Included within the protection scope of the present invention.

As shown in Figure 1, it is a schematic diagram of the gate dielectric structure of the MOS device proposed by the embodiment of the present invention, including an interface layer film 102 formed on the surface of the semiconductor substrate 101, and at least two layers formed on the surface of the interface layer film 102 insulating films 104 (103-1 to 103-n), wherein each of at least two insulating films 104 (103-1 to 103-n) has a different element composition and/or different concentrations, and the interface layer film 102 and at least two layers of insulating films 104 are subjected to an optimized annealing process, the optimized annealing process is related to the elemental composition and/or concentration of the interface layer film 102 and at least two layers of insulating films 104, to To achieve the desired element and/or concentration profile.

In one embodiment of the present invention, the interface layer film 102 and the insulating films 103-1 to 103-n may include: HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ , La ₂ O ₃ , Y ₂ O ₃ , HfLaO _x , LaAlO _x , LaSiO _x , nitrides of the above materials, nitrogen oxides of the above materials, oxides of other rare earth elements, nitrides of other rare earth elements, SiO _2. SiNx, SiON, or a combination of the above materials, or other suitable materials and combinations thereof.

The present invention also proposes a CMOS device including the above-mentioned gate dielectric structure. Except for the gate dielectric structure, the configuration of other parts of the CMOS device is the same as that of the prior art, and will not be repeated here.

As mentioned above, the different components and different concentrations in the interfacial layer film 102 and the insulating films 103-1 to 103-n are to improve one or several performances of the MOS device. These embodiments are only illustrative, and it does not mean that the present invention can be realized only through the following embodiments.

Embodiment one,

As shown in Figures 2-5, it is a schematic diagram of forming the gate stack structure of the present invention in Embodiment 1 of the present invention. In this embodiment, the multilayer insulating film is a three-layer film with the same thickness and different atomic percentages. Of course, in other Insulation film also can be different in the embodiment, comprises the following steps:

Step 1: As shown in Fig. 2, grow interface layer film 102 on the silicon substrate 101 that pre-process process has been done well, and its thickness is about 0.5nm, and in the embodiment of the present invention, interface layer film 102 is _SiO2 interface layer film. In this embodiment, the interface layer film 102 is described by taking SiO ₂ as an example. In other embodiments, other materials mentioned above can be selected as the interface layer film 102 .

Step 2: As shown in Figure 3, grow the first layer of insulating film 103-1 with ALD technology on the _SiO2 interface layer film 102, its thickness is about 1nm, in the embodiment of the present invention, the first layer of insulating film 103-1 1 is Hf _0.8 La _0.2 O thin film, wherein the atomic percentage of La element is 20%.

Step 3: As shown in Figure 4, on the first layer of insulating film 103-1 (Hf _0.8 La _0.2 O film), use ALD technology to generate the second layer of insulating film 103-2, its thickness is about 1nm, the second layer of insulating film Thin film 103-2 is a Hf _0.5 La _0.5 O thin film, wherein the atomic percentage of La element is 50%.

Step 4: As shown in Figure 5, grow the third layer of insulating film 103-3 with ALD technology on the second layer of insulating film 103-2 (Hf _0.5 La _0.5 O film), its thickness is about 1nm, the third layer of insulating film Thin film 103-3 is a Hf _0.2 La _0.8 O thin film, in which the atomic percentage of La element is 80%.

Step 5: Annealing the structure at 500° C. for 30 s.

This embodiment of the invention can achieve the following special beneficial effects:

1. Increase the dielectric constant of the entire high-k dielectric layer (La element helps to increase the dielectric constant).

2. The distribution of the La element in the entire high-k dielectric layer produces a gradient, and the concentration of the La element in the area close to the silicon substrate is smaller than that in the area far away from the silicon substrate, which effectively reduces the scattering of La to the channel carriers and improves the The mobility of the channel carriers.

Embodiment two,

As shown in FIG. 6-11, it is a schematic diagram of forming the gate stack structure of the present invention according to Embodiment 2 of the present invention, including the following steps:

Step 1: grow a 0.5nm-thick interface layer film 102 on the silicon substrate 101 that has been pre-processed, as shown in FIG. 6 , the interface layer film 102 is SiO ₂ in this embodiment. In this embodiment, the interface layer film 102 is described by taking SiO ₂ as an example. In other embodiments, other materials mentioned above can be selected as the interface layer film 102 .

Step 2: As shown in Figure 6, grow the first layer of insulating film 103-1 with ALD technology on the interface layer film 102, its thickness is about 1nm, in this embodiment, the first layer of insulating film 103-1 is HfO ₂ films.

Step 3: As shown in Figure 7, grow a second layer of insulating film 103-2 with ALD technology on the first layer of insulating film 103-1, its thickness is about 0.5nm, in this embodiment, the second layer of insulating film 103-2 is Al ₂ O ₃ film.

Step 4: As shown in Figure 8, grow the third layer of insulating film 103-3 with ALD technology on the second layer of insulating film 103-2, its thickness is about 0.5nm, in this embodiment, the third layer of insulating film 103-3 is _HfO2 film.

Step 5: In a nitrogen atmosphere, perform a first annealing treatment at 500° C. for 30 s on the structure formed through the above steps.

Step 6: As shown in Figure 9, grow the fourth layer of insulating film 103-4 with ALD technology on the third layer of insulating film 103-3, its thickness is about 1nm, in this embodiment, the fourth layer of insulating film 103 -4 is Al ₂ O ₃ film.

Step 7: As shown in Figure 10, grow the fifth layer of insulating film 103-5 with ALD technology on the fourth layer of insulating film 103-4, its thickness is about 0.5nm, in this embodiment, the fifth layer of insulating film 103-5 is _HfO2 film.

Step 8: Perform a second annealing treatment at 500° C. for 15 s on the structure formed through the above steps.

Through this embodiment, the following special beneficial effects can be achieved:

1. Adjust the flat-band voltage by doping Al element, and finally achieve the purpose of adjusting the threshold voltage.

2. By setting the position of the Al ₂ O ₃ film and the setting of the annealing process (the purpose of setting the parameters of the annealing process is to make the annealing temperature of the film containing less Al elements longer and the annealing time shorter after growing the film containing more Al elements , which not only achieves the purpose of reducing defects and interface charges in the annealing process itself, but also ensures the concentration distribution of Al elements in the high-k dielectric layer, as shown in Figure 11), so that Al elements will not diffuse too much into SiO ₂ Or near the channel, thereby reducing the influence of Al element on the carrier mobility of the channel.

Embodiment three,

As shown in Figures 12-15, it is a schematic diagram of forming a gate stack structure of the present invention according to Embodiment 3 of the present invention, including the following steps:

Step 1: As shown in FIG. 12 , grow a 0.3nm-thick HfO ₂ thin film 102 on the silicon substrate 101 that has been pre-processed by ALD technology.

Step 2: In a nitrogen atmosphere, perform the first annealing treatment on the structure at 700° C. for 20 s to form a HfSiO _x interface layer film 102 , as shown in FIG. 13 .

Step 3: As shown in Figure 13, on the HfSiO _x interface layer film 102, grow the first layer of insulating film 103-1 with ALD technology, its thickness is about 0.5nm, in this embodiment, the first layer of insulating film 103-1 1 is HfLaON film.

Step 4: as shown in Figure 14, grow the second layer insulating film 103-2 with ALD technology on the first layer insulating film 103-1, its thickness is about 2nm, in this embodiment, the second layer insulating film 103 -2 is _{La2O3 film} .

Step 5: As shown in Figure 15, grow the third layer of insulating film 103-3 with ALD technology on the second layer of insulating film 103-2, its thickness is about 1nm, in this embodiment, the third layer of insulating film 103 -3 is _HfO2 film.

Step 6: Perform a second annealing treatment at 700° C. for 30 s on the structure formed through the above steps.

Through this embodiment, the following special beneficial effects can be achieved:

1. Use HfSiO _x surface film instead of SiO ₂ film to reduce the EOT of the gate dielectric.

2. Using HfLaON film, the introduction of N elements limits the diffusion of La elements during annealing, reduces the influence of La elements diffusing to the vicinity of the channel on the scattering of channel carriers, and improves the migration of channel carriers Rate.

3. The La ₂ O ₃ thin film effectively increases the dielectric constant of the entire gate dielectric layer (the dielectric constant of La ₂ O ₃ is very high), and reduces the EOT of the gate dielectric.

4. The HfO ₂ film can prevent problems such as moisture absorption and film deterioration caused by the direct contact of the La ₂ O ₃ film with air.

Embodiment four,

As shown in Figures 16-18, it is a schematic diagram of forming a gate stack structure of the present invention according to Embodiment 4 of the present invention, including the following steps:

Step 1: As shown in FIG. 16 , grow a SiO ₂ interface layer film 102 with a thickness of 0.5 nm on the silicon substrate 101 that has been pre-processed.

Step 2: On the SiO ₂ interface layer film 102, grow the first layer of insulating film 103-1 with ALD technology, and its thickness is about 1nm. In this embodiment, the first layer of insulating film 103-1 is HfO ₂ film, such as Figure 16 shows.

Step 3: On the first layer of insulating film 103-1, grow a second layer of insulating film 103-2 with a thickness of about 1 nm by ALD technology. In this embodiment, the second layer of insulating film 103-2 is a SiN _x film , as shown in Figure 16.

Step 4: As shown in Figure 17, grow the third layer of insulating film 103-3 with ALD technology on the second layer of insulating film 103-2, its thickness is about 1nm, in this embodiment, the third layer of insulating film 103 -3 is HfN film.

Step 5: In a nitrogen atmosphere, perform the first annealing treatment at 900° C. for 30 s on the structure formed in the above steps to form HfSiON (103-2 and 103-3), as shown in FIG. 18 .

Step 6: As shown in Figure 18, grow a fourth insulating film 103-4 by ALD on the HfSiON (103-2 and 103-3) formed after annealing, with a thickness of about 1 nm. In this embodiment, The fourth insulating film 103-4 is a HfO ₂ film.

Step 7: Perform a second annealing treatment at 700° C. for 30 s on the structure formed in the above steps.

Through this embodiment, the following special beneficial effects can be achieved:

1. A thin film layer containing Si and N elements is added to the dielectric, which effectively reduces the leakage current of the entire gate dielectric layer and improves thermal stability.

2. The N element is in the thin film layer away from the channel, which avoids the scattering of the N element to the channel carriers.

3. The HfO ₂ thin film increases the dielectric constant of the entire gate dielectric layer, so that the EOT of the entire gate dielectric is effectively reduced.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and modifications, the scope of the invention is defined by the appended claims and their equivalents.

Claims (33)

1. A gate dielectric structure of a metal oxide semiconductor MOS device, characterized in that it comprises: an interfacial layer film formed on the surface of the semiconductor substrate; and At least two insulating films formed on the surface of the interface layer film, each insulating film includes at least two elements, wherein each of the at least two insulating films has an element different from other adjacent insulating films Element components and/or different concentrations, and the interface layer film and the at least two insulating films undergo an optimized annealing process, and the optimized annealing process is compatible with the interface layer film and the at least two insulating films The element composition and/or concentration are related to achieve the desired distribution of said elements and/or concentration. 2. The gate dielectric structure of a MOS device according to claim 1, wherein the interface layer film comprises: HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ , La ₂ O ₃ , Y ₂ O ₃ , HfLaO _x , LaAlO _x , LaSiO _x , nitrides of the above materials, nitrogen oxides of the above materials, oxides of other rare earth elements, nitrides of other rare earth elements, SiO ₂ , SiNx, SiON, or a combination of the above materials. 3. The gate dielectric structure of a MOS device according to claim 1, wherein the insulating film comprises: HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ , La ₂ O ₃ , Y ₂ O ₃ , HfLaO _x , LaAlO _x , LaSiO _x , nitrides of the above materials, nitrogen oxides of the above materials, oxides of other rare earth elements, nitrides of other rare earth elements, SiO _2. SiNx, SiON, or a combination of the above materials. 4. The gate dielectric structure of a MOS device according to claim 1, wherein any one of the at least two insulating films contains elements different from those of other adjacent films, or contains the same elements but elements The components are not the same. 5 . The gate dielectric structure of a MOS device according to claim 4 , wherein at least one layer of the insulating films includes Al element. 6 . The gate dielectric structure of a MOS device according to claim 5 , wherein at least one layer of the insulating film comprises Hf element or La element. 7. The gate dielectric structure of a MOS device according to claim 4, wherein at least one layer of the insulating films comprises Hf element. 8. The gate dielectric structure of a MOS device according to claim 7, wherein at least one layer of the insulating film comprises La element. 9. The gate dielectric structure of a MOS device according to claim 4, wherein at least one layer of the insulating films comprises Si element. 10. The gate dielectric structure of a MOS device according to any one of claims 5-9, wherein at least one layer of the insulating film contains O element or 14, the insulating film according to claims 6-12 , characterized in that at least one layer of the insulating film contains N element. 11. The gate dielectric structure of a MOS device according to claim 4, wherein the insulating film comprises at least one layer of Al ₂ O ₃ film. 12 . The gate dielectric structure of a MOS device according to claim 11 , wherein the insulating film further comprises at least one layer of HfO ₂ film. 13 . 13. The gate dielectric structure of a MOS device according to claim 4, wherein at least one layer of the insulating films comprises a LaAlO film. 14. The gate dielectric structure of a MOS device according to claim 5, wherein at least one layer of the insulating films comprises a HfLaON film. 15 . The gate dielectric structure of a MOS device according to claim 14 , wherein the insulating film further comprises a layer of La ₂ O ₃ film or HfO ₂ film. 16. The gate dielectric structure of a MOS device according to claim 4, wherein the insulating film comprises a HfSiON film. 17. A CMOS device, characterized by comprising the gate dielectric structure according to any one of claims 1-16. 18. A method for forming a gate dielectric structure of a MOS device, comprising the steps of: Forming an interfacial layer film on the surface of the semiconductor substrate; At least two layers of insulating films are formed on the surface of the interface layer film, each layer of insulating films includes at least two elements, wherein each of the at least two layers of insulating films has elements different from other adjacent insulating films components and/or different concentrations; According to the element composition and/or concentration of the interface layer film and the at least two insulation films, an optimized annealing process is performed on the interface layer film and the at least two insulation films to achieve the desired elements and and/or distribution of concentrations. 19. The method for forming a gate dielectric structure of a MOS device according to claim 18, wherein the interface layer film comprises: HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ , La ₂ O ₃ , Y ₂ O ₃ , HfLaO _x , LaAlO _x , LaSiO _x , nitrides of the above materials, nitrogen oxides of the above materials, oxides of other rare earth elements, other rare earth elements Nitride, SiO ₂ , SiNx, SiON, or a combination of the above materials. 20. The method for forming a gate dielectric structure of a MOS device according to claim 18, wherein the insulating film comprises: HfO ₂ , HfSiO _x , HfON, HfSiON, HfAlO _x , Al ₂ O ₃ , ZrO ₂ , ZrSiO _x , Ta ₂ O ₅ , La ₂ O ₃ , Y ₂ O ₃ , HfLaO _x , LaAlO _x , LaSiO _x , nitrides of the above materials, nitrogen oxides of the above materials, oxides of other rare earth elements, nitrogen of other rare earth elements compound, SiO ₂ , SiNx, SiON, or a combination of the above materials. 21. The method for forming a gate dielectric structure of a MOS device according to claim 18, wherein any one of the at least two insulating films contains elements different from other adjacent films, or contains the same elements but the composition of the elements is not the same. 22. The gate dielectric structure of a MOS device according to claim 21, wherein at least one layer of the insulating films comprises Al element. 23. The method for forming a gate dielectric structure of a MOS device according to claim 22, wherein at least one layer of the insulating film comprises Hf element or La element. 24. The method for forming a gate dielectric structure of a MOS device according to claim 21, wherein at least one layer of the insulating films comprises Hf element. 25. The method for forming a gate dielectric structure of a MOS device according to claim 24, wherein at least one layer of the insulating film comprises La element. 26. The method for forming a gate dielectric structure of a MOS device according to claim 21, wherein at least one layer of the insulating films comprises Si element. 27. The method for forming a gate dielectric structure of a MOS device according to any one of claims 22-26, wherein at least one layer of the insulating film contains O element or N element. 28. The method for forming a gate dielectric structure of a MOS device according to claim 21, wherein the insulating film comprises at least one layer of Al ₂ O ₃ film. 29. The method for forming a gate dielectric structure of a MOS device according to claim 28, wherein at least one layer of HfO ₂ film is included in the insulating film. 30. The method for forming a gate dielectric structure of a MOS device according to claim 21, wherein at least one layer of the insulating films comprises a LaAlO film. 31. The method for forming a gate dielectric structure of a MOS device according to claim 22, wherein at least one layer of the insulating films comprises a HfLaON film. 32. The method for forming a gate dielectric structure of a MOS device according to claim 31, wherein the insulating film further comprises a layer of La ₂ O ₃ film or HfO ₂ film. 33. The method for forming a gate dielectric structure of a MOS device according to claim 21, wherein the insulating film comprises a HfSiON film.

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