CN102064804A - On-chip clock generator circuit - Google Patents
On-chip clock generator circuit Download PDFInfo
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- CN102064804A CN102064804A CN 201010546205 CN201010546205A CN102064804A CN 102064804 A CN102064804 A CN 102064804A CN 201010546205 CN201010546205 CN 201010546205 CN 201010546205 A CN201010546205 A CN 201010546205A CN 102064804 A CN102064804 A CN 102064804A
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Abstract
The invention discloses an on-chip clock generator circuit and relates to the designing field of digital-analog mixed integrated circuits. The on-chip clock generator circuit is formed by connecting n grades of phase inverter in series, wherein the output end of an nth phase inverter is respectively connected with the input end of the primary phase inverter and the output end of a clock, and n=2k+1 (k=1, 2, 3......); each grade of phase inverter comprises an NOT gate, a programmable resistor and a programmable capacitor, the output end of the NOT gate is connected with one end of the programmable resistor, and the other end of the programmable resistor is connected with the programmable capacitor; the resistance values of the programmable resistors are regulated through a resistance calibration circuit; and the capacitance values of the programmable capacitors are regulated through a capacitance calibration circuit. In the invention, through the matched use of the resistance calibration circuit, the capacitance calibration circuit, an off-chip high-precision resistor and an off-chip high-precision capacitor, the calibrations of the programmable resistors and the programmable capacitors are finished, thereby a high-precision on-chip clock is realized, and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to the hybrid digital-analog integrated circuit design field, particularly go up clock generator circuit for a kind of.
Background technology
Along with integrated circuit (IC) design and manufacture level improve constantly, the function of chip is become stronger day by day, the integrated level of chip is also more and more higher, especially in consumer electronics product, need AFE (Analog Front End, AFE (analog front end)), ADC (Analog to Digital Converter, analog to digital converter), DAC (Digital to Analog Converter, digital to analog converter) combines with digital circuit, finish complicated product function jointly.Requirement according to product, chip may need different functional units, but sheet internal clock generator is a widely used functional module, because it not only can be used for providing system clock to digital circuit, can also provide sampling clock for ADC or DAC, sheet internal clock generator is one of requisite module in the hybrid integrated circuit design.
At present, clock generator circuit generally uses crystal oscillator (Crystal Oscillator) or PLL (Phase Lock Loop, analog phase-locked look) to realize on the sheet, as depicted in figs. 1 and 2.
No matter be that crystal oscillator or phase-locked loop all need chip exterior that crystal oscillation module or reference clock (general reference clock also is to be produced by the crystal oscillator on the system board) are provided in the practical application, therefore the entire circuit system needs one or more crystal oscillators, and this will increase manufacturing cost; And of the prior art precision that goes up clock generator circuit is not high, can not satisfy the needs in the practical application.
Summary of the invention
In order to improve calibration accuracy, reduce manufacturing cost, satisfy the needs in the practical application, the invention provides a kind of and go up clock generator circuit, go up clock generator circuit for described and be connected in series by n level inverter, the output of n level inverter links to each other with input, the output terminal of clock of first order inverter respectively, n=2k+1, (k=1,2,3 ...); Each grade inverter comprises: not gate, programmable resistance and programmable capacitor, one end of the output of described not gate and described programmable resistance links to each other, the other end of described programmable resistance links to each other with described programmable capacitor, by the resistance calibration circuit resistance value of described programmable resistance is regulated, the capacitance of described programmable capacitor is regulated by the electric capacity calibration circuit.
Described resistance calibration circuit comprises: the outer precisely resistance of resistance calibration circuit and sheet in the sheet, any one input pin of described outer precisely resistance and described interior resistance calibration circuit links to each other.
Described interior resistance calibration circuit comprises: first current source, second current source, programmable resistance, comparator and digital circuit,
Described first current source and described outer precisely resistance are connected on the same input pin; Described second current source links to each other with described programmable resistance; Described outer precisely resistance is connected the positive polarity input of described comparator by input pin, and the negative polarity input of described programmable resistance and described comparator links to each other; The output of described comparator links to each other with described digital circuit, by the control of described digital circuit described programmable resistance is regulated.
Described electric capacity calibration circuit comprises: the outer precisely electric capacity of electric capacity calibration circuit and sheet in the sheet, any one input pin of described outer precisely electric capacity and described interior electric capacity calibration circuit links to each other.
Described interior electric capacity calibration circuit comprises: first current source, second current source, first switch, second switch, programmable capacitor, comparator and digital circuit,
Described first current source is connected on the same input pin by described first switch and described outer precisely electric capacity; Described second current source links to each other with described programmable capacitor by described second switch; Described outer precisely electric capacity is connected the positive polarity input of described comparator by input pin, and the negative polarity input of described programmable capacitor and described comparator links to each other; The output of described comparator links to each other with described digital circuit, by the control of described digital circuit described programmable capacitor is regulated.
The beneficial effect of technical scheme provided by the invention is:
The invention provides a kind of and go up clock generator circuit, by being used of the outer precision resister of resistance calibration circuit, electric capacity calibration circuit and sheet, the outer high-accuracy capacitor of sheet, finish the calibration of interior programmable resistance of sheet and programmable capacitor, realize high-precision internal clock, reduced manufacturing cost; And clock generator circuit can be widely used in the clock generation system in signal sample circuit and the digital system on provided by the invention.
Description of drawings
The structured flowchart of the crystal oscillator that Fig. 1 provides for prior art;
The structured flowchart of the analog phase-locked look that Fig. 2 provides for prior art;
Fig. 3 is provided by the invention and goes up clock generator circuit figure;
Fig. 4 is a resistance calibration circuit diagram provided by the invention;
Fig. 5 is electric capacity calibration circuit figure provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
In order to improve calibration accuracy, reduce manufacturing cost, satisfy the needs in the practical application, the embodiment of the invention provides a kind of to go up clock generator circuit.
Referring to Fig. 3, clock generator circuit is connected in series by n level inverter on the sheet that the embodiment of the invention provides, and the output of n level inverter links to each other with input, the output terminal of clock clkout of first order inverter respectively, n=2k+1, (k=1,2,3 ...); Each grade inverter comprises: not gate, programmable resistance and programmable capacitor, and an end of the output of not gate and programmable resistance links to each other, and the other end of programmable resistance links to each other with programmable capacitor.
In the clock generator circuit, every grade of inverter time-delay is approximately τ=RC on the sheet that the embodiment of the invention provides, and total time-delay is n τ, so clock generator output clock frequency is f=1/ (2 π n τ).
But, in semiconductor technology, the size of resistance and electric capacity can fluctuate along with technique change, if resistance and electric capacity are not proofreaied and correct, can influence the precision of clock generator circuit output frequency on the sheet, for example: the resistance R value changes ± 20%, the capacitor C value changes ± 10%, will make on the sheet clock generator circuit output clock frequency change can to reach ± about 30%, can influence the precision of clock generator circuit on the sheet so significantly, generally do not wish that in actual applications clock signal has so big excursion, if do not calibrate then can't obtain the satisfied clock signal of precision.
For this reason, the embodiment of the invention provides resistance calibration circuit and electric capacity calibration circuit, by the resistance calibration circuit resistance value of programmable resistance is regulated, and by the electric capacity calibration circuit capacitance of programmable capacitor is regulated.
Referring to Fig. 4, this resistance calibration circuit comprises: the outer precisely resistance of resistance calibration circuit and sheet in the sheet, the outer precisely resistance of sheet links to each other with any one input pin of resistance calibration circuit in the sheet.
The resistance calibration circuit comprises in this sheet: first current source, second current source, programmable resistance, comparator and digital circuit, and the outer precisely resistance of first current source and sheet is connected on the same input pin; Second current source links to each other with programmable resistance; The outer precisely resistance of sheet is connected the positive polarity input of comparator by input pin, and the negative polarity input of programmable resistance and comparator links to each other; The output of comparator links to each other with digital circuit, by the control of described digital circuit programmable resistance is regulated.
Wherein, first current source and second current source are same current source.
During specific implementation, behind the chip power, by first current source electric current is input among the outer precisely resistance R ext of sheet, by second current source identical electric current is input among the programmable resistance R, the outer precisely voltage of resistance R ext of sheet is sent into the positive polarity input of comparator, the voltage of programmable resistance R is sent into the negative polarity input of comparator, comparator can detect the voltage difference of the negative polarity input of the positive polarity input of comparator and comparator, when the voltage of the positive polarity input of comparator during, can export the high signal of judging greater than the voltage of the negative polarity input of comparator; When the voltage of the positive polarity input of comparator during less than the voltage of the negative polarity input of comparator, can output hang down the judgement signal, digital circuit finally makes the resistance value of programmable resistance approach the outer precisely resistance of resistance R ext of sheet according to the resistance value size of the output adjustment programmable resistance of comparator.
Referring to Fig. 5, this electric capacity calibration circuit comprises: the outer precisely electric capacity of electric capacity calibration circuit and sheet in the sheet, the outer precisely electric capacity of sheet links to each other with any one input pin of electric capacity calibration circuit in the sheet.
The electric capacity calibration circuit comprises in this sheet: first current source, second current source, first switch, second switch, programmable capacitor, comparator, digital circuit blocks, and first current source is connected on the same input pin by first switch and the outer precisely electric capacity of sheet; Second current source links to each other with programmable capacitor by second switch; The outer precisely electric capacity of sheet is connected the positive polarity input of comparator by input pin, and the negative polarity input of programmable capacitor and comparator links to each other; The output of comparator links to each other with digital circuit, by the control of digital circuit programmable capacitor is regulated.
Wherein, first switch and second switch are same switch.
During specific implementation, behind the chip power, first switch and second switch are closed simultaneously, by first current source outer precisely capacitor C ext of sheet is charged, by second current source programmable capacitor C is charged, first switch and second switch disconnect simultaneously, the outer precisely voltage of capacitor C ext of sheet is sent into the positive polarity input of comparator, the voltage of programmable capacitor C is sent into the negative polarity input of comparator, comparator can detect the voltage difference of the negative polarity input of the positive polarity input of comparator and comparator, when the voltage of the positive polarity input of comparator during, can export the high signal of judging greater than the voltage of the negative polarity input of comparator; When the voltage of the positive polarity input of comparator during less than the voltage of the negative polarity input of comparator, can output hang down the judgement signal, digital circuit finally makes the capacitance of programmable capacitor C approach the outer precisely capacitance of capacitor C ext of sheet according to the capacitance size of the output adjustment programmable capacitor C of comparator.
The process aforesaid operations has been realized the calibration to programmable resistance and programmable capacitor, be used on the sheet in the clock generator circuit by calibration control word programmable resistance and programmable capacitor, clock generator circuit is adjusted the size of programmable resistance R and programmable capacitor C on the sheet according to Digital Circuit Control, realized calibration further to clock generator circuit on the sheet, make it that clock accurately can be provided, wherein, the accuracy of calibration accuracy is mainly by comparator precision and the decision of calibration control word bit wide.
In order to improve calibration accuracy further, outside precisely resistance and outside precisely electric capacity are preferably the degree of precision types of devices, can regulate the value of device by modes such as instruments, satisfy the requirement to precision, and the calibration control word is selected more than the 10bit.
In order to improve the calibration effect of resistance and electric capacity further, can before the calibration of resistance and electric capacity the offset voltage of comparator be calibrated carrying out, specifically can adopt generic calibration mode of the prior art that the offset voltage of comparator is calibrated.
In sum, the embodiment of the invention provides a kind of to go up clock generator circuit, by being used of the outer precision resister of electric capacity calibration circuit and sheet in resistance calibration circuit, the sheet in the sheet, the outer high-accuracy capacitor of sheet, finish the calibration of interior resistance of sheet and electric capacity, realize high-precision internal clock, reduced manufacturing cost; And clock generator circuit can be widely used in the clock generation system in signal sample circuit and the digital system on the sheet that the embodiment of the invention provides.
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the invention described above embodiment sequence number is not represented the quality of embodiment just to description.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. clock generator circuit on the sheet is characterized in that, goes up clock generator circuit for described and is connected in series by n level inverter, the output of n level inverter links to each other with input, the output terminal of clock of first order inverter respectively, n=2k+1, (k=1,2,3 ...); Each grade inverter comprises: not gate, programmable resistance and programmable capacitor, one end of the output of described not gate and described programmable resistance links to each other, the other end of described programmable resistance links to each other with described programmable capacitor, by the resistance calibration circuit resistance value of described programmable resistance is regulated, the capacitance of described programmable capacitor is regulated by the electric capacity calibration circuit.
2. go up clock generator circuit for according to claim 1, it is characterized in that, described resistance calibration circuit comprises: the outer precisely resistance of resistance calibration circuit and sheet in the sheet, any one input pin of described outer precisely resistance and described interior resistance calibration circuit links to each other.
3. go up clock generator circuit, it is characterized in that described interior resistance calibration circuit comprises for according to claim 2: first current source, second current source, programmable resistance, comparator and digital circuit,
Described first current source and described outer precisely resistance are connected on the same input pin; Described second current source links to each other with described programmable resistance; Described outer precisely resistance is connected the positive polarity input of described comparator by input pin, and the negative polarity input of described programmable resistance and described comparator links to each other; The output of described comparator links to each other with described digital circuit, by the control of described digital circuit described programmable resistance is regulated.
4. go up clock generator circuit for according to claim 1, it is characterized in that, described electric capacity calibration circuit comprises: the outer precisely electric capacity of electric capacity calibration circuit and sheet in the sheet, any one input pin of described outer precisely electric capacity and described interior electric capacity calibration circuit links to each other.
5. go up clock generator circuit, it is characterized in that described interior electric capacity calibration circuit comprises for according to claim 4: first current source, second current source, first switch, second switch, programmable capacitor, comparator and digital circuit,
Described first current source is connected on the same input pin by described first switch and described outer precisely electric capacity; Described second current source links to each other with described programmable capacitor by described second switch; Described outer precisely electric capacity is connected the positive polarity input of described comparator by input pin, and the negative polarity input of described programmable capacitor and described comparator links to each other; The output of described comparator links to each other with described digital circuit, by the control of described digital circuit described programmable capacitor is regulated.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010546205 CN102064804A (en) | 2010-11-16 | 2010-11-16 | On-chip clock generator circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010546205 CN102064804A (en) | 2010-11-16 | 2010-11-16 | On-chip clock generator circuit |
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| CN102064804A true CN102064804A (en) | 2011-05-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111064455A (en) * | 2019-12-27 | 2020-04-24 | 江苏集萃微纳自动化系统与装备技术研究所有限公司 | Programmable delay circuit |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10276068A (en) * | 1997-03-28 | 1998-10-13 | Sony Corp | Ring oscillator |
| CN1795605A (en) * | 2003-05-28 | 2006-06-28 | 西门子公司 | Device for setting a frequency |
| US20080007354A1 (en) * | 2006-07-05 | 2008-01-10 | Ishtiaq Ahsan | Determining thermal absorption using ring oscillator |
| CN101263654A (en) * | 2005-12-02 | 2008-09-10 | 松下电器产业株式会社 | Multi-phase oscillator |
| JP4167255B2 (en) * | 2004-10-01 | 2008-10-15 | 松下電器産業株式会社 | Oscillator start-up control circuit |
| JP2009017257A (en) * | 2007-07-05 | 2009-01-22 | Epson Toyocom Corp | Inverter piezoelectric oscillator |
| CN101496278A (en) * | 2006-04-07 | 2009-07-29 | 高通股份有限公司 | Method and apparatus for tuning resistors and capacitors |
| CN101557213A (en) * | 2009-03-27 | 2009-10-14 | 华为技术有限公司 | Delay unit, annular oscillator and PLL circuit |
| CN101615900A (en) * | 2008-06-27 | 2009-12-30 | 阿尔特拉公司 | Digital controlled oscillator |
-
2010
- 2010-11-16 CN CN 201010546205 patent/CN102064804A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10276068A (en) * | 1997-03-28 | 1998-10-13 | Sony Corp | Ring oscillator |
| CN1795605A (en) * | 2003-05-28 | 2006-06-28 | 西门子公司 | Device for setting a frequency |
| JP4167255B2 (en) * | 2004-10-01 | 2008-10-15 | 松下電器産業株式会社 | Oscillator start-up control circuit |
| CN101263654A (en) * | 2005-12-02 | 2008-09-10 | 松下电器产业株式会社 | Multi-phase oscillator |
| CN101496278A (en) * | 2006-04-07 | 2009-07-29 | 高通股份有限公司 | Method and apparatus for tuning resistors and capacitors |
| US20080007354A1 (en) * | 2006-07-05 | 2008-01-10 | Ishtiaq Ahsan | Determining thermal absorption using ring oscillator |
| JP2009017257A (en) * | 2007-07-05 | 2009-01-22 | Epson Toyocom Corp | Inverter piezoelectric oscillator |
| CN101615900A (en) * | 2008-06-27 | 2009-12-30 | 阿尔特拉公司 | Digital controlled oscillator |
| CN101557213A (en) * | 2009-03-27 | 2009-10-14 | 华为技术有限公司 | Delay unit, annular oscillator and PLL circuit |
Non-Patent Citations (1)
| Title |
|---|
| 《沈阳师范大学学报（自然科学版）》 20090930 汪鹏 等 改进型电阻负载环形振荡器 第27卷, 第4期 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111064455A (en) * | 2019-12-27 | 2020-04-24 | 江苏集萃微纳自动化系统与装备技术研究所有限公司 | Programmable delay circuit |
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Application publication date: 20110518 |