CN102064178B - Cell structure of one-time programmable memory (OTP) device and manufacturing method and operating method of cell structure - Google Patents
Cell structure of one-time programmable memory (OTP) device and manufacturing method and operating method of cell structure Download PDFInfo
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Abstract
The invention discloses a cell structure of a one-time programmable memory (OTP) device. The cell structure is characterized in that silicon dioxides (16) are arranged at the two sides of a gate oxide (13); silicon nitride side walls (17) are arranged on the silicon dioxides (16); and a lightly doped region (15) is arranged below only one side of a polysilicon gate (14). By removing the lightly doped region (15) at the other side, the generation probability and quantity of hot electrons are improved and the hot electrons penetrate through the barriers of the silicon dioxides (16) and are captured by the silicon nitride side walls (17), thus implementing programming by using a channel hot electron injection (CHE) mechanism. In the cell structure, the polysilicon gate (14) is used as a word line, an n-type heavily doped region (18a) adjacent to the n-type lightly doped region (15) is used as a bit line; and an n-type heavily doped region (18b) not adjacent to the n-type lightly doped region (15) is used as the programming terminal. The invention also discloses a manufacturing method and an operating method of the cell structure of the OTP device. The cell structure has small area and is applicable to the condition of thinner gate oxide.
Description
Technical field
The present invention relates to a kind of OTP (one-time programmable memory, disposable programmable memory) device, particularly relate to a kind of cellular construction of OTP parts.
Background technology
The cellular construction of OTP parts, at present representative have two classes.
See also Fig. 1 a, Fig. 1 b, the cellular construction of first kind OTP parts is made up of a transistor 1b and a floating boom electric capacity 1a, wherein transistor 1b carries out programing function, floating boom electric capacity 1a carries out the charge storage function, the polysilicon gate of transistor 1b extends to the top of floating boom electric capacity 1a, and floating boom electric capacity 1a is the capacity plate antenna that the silicon of the polysilicon of being come by extension and below thereof constitutes.Chinese invention patent ublic specification of application CN1627525A (open day on June 15th, 2005), Chinese invention patent ublic specification of application CN1627526A all disclose the cellular construction of this OTP parts in (open day on June 15th, 2005).Because the existence of floating boom coupling capacitance 1a, the cellular construction area of this OTP parts is excessive, is unfavorable for the application of high density integrated circuit.
The cellular construction of the second class OTP parts is composed in series by two PMOS, and one of them PMOS is as gate transistor; Another PMOS utilizes its floating boom storage data as memory cell.U.S. Patent Application Publication specification US2004/0109364A1 (open day on June 10th, 2004), U.S. Patent Application Publication specification US2006/0018161A1 all disclose the cellular construction of this OTP parts in (open day on January 26th, 2006).Compared to the cellular construction of first kind OTP parts, the cellular construction of the second class OTP parts has very big dwindling on area.But the cellular construction of the second class OTP parts utilizes the storage organization of floating boom as electronics, and therefore the gate oxide thickness for the floating boom below has certain requirement.(explanation Pages431-434) requires the gate oxide thickness theoretical value to exist for VLSI Design Volume13 (2001), Issue 1-4 according to " Program, Erase and Retent ion Times of Thin-oxide FIash-EEPROMs "
More than, this just defines the application of the cellular construction of this OTP parts.
Summary of the invention
Technical problem to be solved by this invention provides a kind of cellular construction of OTP parts, on the one hand has very little area, go on the other hand gate oxide thin (for example less than
) situation.
For solving the problems of the technologies described above, the cellular construction of OTP parts of the present invention is a NMOS, it on substrate 10 p trap 12, in substrate 10 and/or the p trap 12 isolated area 11 is arranged, gate oxide 13 and oxide layer 16 are arranged on the p trap 12, oxide layer 16 is in the both sides of gate oxide 13, polysilicon gate 14 is arranged on the gate oxide 13, silicon nitride side wall 17 is arranged on the oxide layer 16, silicon nitride side wall 17 is in the both sides of polysilicon gate 14 and contact, the thickness of oxide layer (16) is less than the thickness of gate oxide (13), polysilicon gate 14 only has n type light doping section 15 in the p of side-lower trap 12, n type heavily doped region 18a is arranged in the p trap 12 of silicon nitride side wall 17 outer side-lowers, 18b, n type heavily doped region 18a is adjacent with n type light doping section 15, n type heavily doped region 18b is not adjacent with n type light doping section 15, and silicon chip surface is coated with layer of silicon dioxide 19;
Described n type heavily doped region 18a is as bit line;
Described n type heavily doped region 18b is as the programming end;
Described polysilicon gate 14 is as word line.
The manufacture method of the cellular construction of described OTP parts comprises the steps:
The 1st step formed p trap 12 with extension or ion implantation technology on substrate 10, isolate (LOCOS) or shallow-trench isolation (STI) technology formation isolated area 11 with field oxygen in substrate 10 and/or p trap 12;
The 2nd step, thermal oxide growth layer of silicon dioxide on p trap 12, deposit one deck polysilicon again, the described polysilicon layer of etching also forms polysilicon gate 14 with described silicon dioxide as etching stop layer, the silicon dioxide of polysilicon gate 14 belows is gate oxide 13, removes gate oxide 13 described silicon dioxide layer in addition with wet corrosion technique;
In the 3rd step, in the p trap 12 of the only side-lower of polysilicon gate 14, form n type light doping section 15 with ion implantation technology;
In the 4th step, in silicon chip surface thermal oxide growth layer of silicon dioxide 16, thickness is
In the 5th step, on the oxide layer 16 of polysilicon gate 14 both sides, form silicon nitride side wall 17;
In the 6th step, in the p trap 12 of the outer side-lower of silicon nitride side wall 17, form n type heavily doped region 18a, 18b by ion implantation technology;
The 7th step is in silicon chip surface deposit layer of silicon dioxide 19.
After above-mentioned 7 steps, silicon chip surface is deposit inter-level dielectric (ILD) again.
The method of operation of the cellular construction of above-mentioned OTP parts is:
During programming: bit line (18a) ground connection, programming end (18b) making alive V1, p trap (12) ground connection, word line (14) making alive V2;
V1＞V2-VT, described VT are the threshold voltage of NMOS;
0＜V1＜VBD, described VBD is the PN junction puncture voltage between programming end (18b) and the p trap (12);
When reading: bit line (18a) making alive V3, programming end (18b) ground connection, p trap (12) ground connection, word line (14) making alive V4;
VT＜V3＜V4-VT；
2VT＜V4＜3 volt.
The cellular construction of OTP parts of the present invention only is a NMOS, compares with the cellular construction of existing OTP parts to have minimum area, and this is one of most important technique effect of the present invention.In addition, the cellular construction of OTP parts of the present invention uses the storage medium of silicon nitride side wall as electronics.Silicon nitride is very strong for the capture ability of electronics, and compared to utilizing the multi-crystal silicon floating bar store electrons, the electronics of being caught by silicon nitride needs certain activation energy could break away from the oxide layer potential barrier escape that catching of silicon nitride penetrates silicon nitride side wall below simultaneously.Therefore utilize silicon nitride side wall store electrons not to be strict with for the thickness of the gate oxide of polysilicon gate below, can be applied in gate oxide thin (as less than
) situation, and make the cellular construction of OTP parts obtain more reliable data storage capacities.More contents can with reference to " charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures " (Solid-State Electronics, vol.44, issue6, pages949-958)
The manufacture method of the cellular construction of OTP parts of the present invention, compatible fully with existing C MOS logic process, need not to increase extra masking process.
The method of operation of the cellular construction of OTP parts of the present invention utilizes CHE (channel hot electron injection, channel hot electron injects) mechanism to programme, electronics is stored in the silicon nitride side wall.Again by NMOS raceway groove before and after the programming for to close or conducting (perhaps channel current is big or little), defining the data of being stored is 0 or 1.
Description of drawings
Fig. 1 a is the schematic diagram of the cellular construction of existing a kind of OTP parts;
Fig. 1 b is the circuit layout schematic diagram of Fig. 1 a;
Fig. 2 is the generalized section of the cellular construction of OTP parts of the present invention;
Fig. 3 is the schematic diagram in cellular construction when programming of OTP parts of the present invention;
Fig. 4 is the schematic diagram of the cellular construction of OTP parts of the present invention when reading.
Description of reference numerals among the figure:
1a is a coupling capacitance; 1b is a transistor; 10 is substrate; 11 is isolated area; 12 is the p trap; 13 is gate oxide; 14 is polysilicon gate; 15 is n type light doping section; 16 is oxide layer; 17 is the silicon nitride side wall; 18a, 18b are n type heavily doped region; 19 is silicon dioxide.
Embodiment
See also Fig. 2, the cellular construction of OTP parts of the present invention is a NMOS, is p trap 12 on substrate 10.In substrate 10 and/or the p trap 12 isolated area 11 is arranged, be generally dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride.Gate oxide 13 and silica 16 are arranged on the p trap 12, and silica 16 is in the both sides of gate oxide 13.Polysilicon gate 14 is arranged on the gate oxide 13, silicon nitride side wall 17 is arranged on the silica 16, silicon nitride side wall 17 is in the both sides of polysilicon gate 14.Polysilicon gate 14 only has n type light doping section 15 in the p of side-lower trap 12.N type heavily doped region 18a, 18b are arranged in the p trap 12 of silicon nitride side wall 17 outer side-lowers.Silicon chip surface is coated with layer of silicon dioxide 19.
Width that it should be noted that silicon dioxide layer 16 among Fig. 2 only is signal.For example, the width of silicon dioxide layer 16 flushes with the outside of silicon nitride side wall 17 among Fig. 2, and in fact the width of silicon dioxide layer 16 can exceed outside the silicon nitride side wall 17.
Wherein, the thickness of the oxide layer 16 of silicon nitride side wall 17 belows is
Because with silicon nitride side wall 17 store electrons, silicon nitride has the ability of stronger trapped electrons than polysilicon, so the thickness of the oxide layer 16 of silicon nitride side wall 17 belows can be lower than among the present invention
And the gate oxide 13 of polysilicon gate 14 belows can be thicker than oxide layer 16, and this is owing to do not re-use polysilicon gate 14 store electrons, does not therefore have thickness requirement for gate oxide 13.
In the cellular construction of above-mentioned OTP parts, polysilicon gate 14 is as word line, and the n type heavily doped region 18a adjacent with n type light doping section 15 be as bit line, and not adjacent with n type light doping section 15 n type heavily doped region 18b is as the programming end.
The manufacture method of the cellular construction of described OTP parts comprises the steps:
The 1st step formed p trap 12 with extension or ion implantation technology on substrate 10, isolate or shallow grooved-isolation technique formation isolated area 11 with field oxygen in substrate 10 and/or p trap 12;
The 2nd step, thermal oxide growth or deposit layer of silicon dioxide on p trap 12, deposit one deck polysilicon on described silicon dioxide layer again, the described polysilicon layer of etching (and with described silicon dioxide layer as etching stop layer) forms polysilicon gate 14, silicon dioxide under the polysilicon gate 14 is gate oxide 13, remove the described silicon dioxide layer that is not covered with wet corrosion technique again by polysilicon gate 14, promptly only keep gate oxide 13, and remove the silicon dioxide of silicon chip surface remainder;
In the 3rd step, in the p trap 12 of the only side-lower of polysilicon gate 14, form n type light doping section 15 with ion implantation technology;
In the 4th step, in silicon chip surface thermal oxide growth layer of silicon dioxide 16, thickness is
The zone of silicon chip surface this moment except being covered by polysilicon gate 14 and gate oxide 13, the silica 16 of all having grown is from the both sides of cutaway view silica 16 at gate oxide 13.
The 5th step at whole silicon wafer surface deposition one deck silicon nitride, anti-carved this layer silicon nitride, thereby formed silicon nitride side wall 17 in the both sides of polysilicon gate 14, and silicon nitride side wall 17 is on the silicon dioxide layer 16 of gate oxide 13 both sides;
The 6th step formed n type heavily doped region by ion implantation technology in the p trap 12 of the outer side-lower of silicon nitride side wall 17, wherein with adjacent with n type light doping section 15 be n type heavily doped region 18a, that not adjacent with n type light doping section 15 is n type heavily doped region 18b;
The 7th step is in silicon chip surface deposit layer of silicon dioxide 19.For example can adopt APCVD (normal pressure chemical vapor deposition), LPCV (low-pressure chemical vapor phase deposition) or PECVD (plasma enhanced CVD) technology etc., and with TEOS (tetraethoxysilane) and O
3(ozone) is feedstock production silicon dioxide layer 19, and is aided with technologies such as backflow to form even, fine and close silicon dioxide layer 19.
After above-mentioned 7 steps, silicon chip surface is the deposit inter-level dielectric again, is generally boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).This moment, silicon dioxide layer 19 completely cut off silicon nitride side wall 17 and the inter-level dielectric as the hot electron storage medium, had played the effect of the data of storing in the cellular construction of protection OTP parts.The thickness of silica 19 (the thinnest part, i.e. thickness on polysilicon gate 14) is
See also Fig. 3, the programmed method of the cellular construction of above-mentioned OTP parts is: bit line 18a ground connection, programming end 18b making alive V1, p trap 12 ground connection, word line 14 making alive V2; V1＞V2-VT, described VT are the threshold voltage of NMOS (cellular construction of OTP parts of the present invention is a nmos pass transistor); 0＜V1＜VBD, described VBD is the PN junction puncture voltage between programming end 18b and the p trap 12.During programming, transistor is operated in pinch off region, and to programming end 18b, raceway groove produces hot electron and is injected in the silicon nitride side wall 17 above the programming end 18b at programming end 18b the direction of channel current from bit line 18a.
There are two lightly doped drains to inject (LDD) district among traditional NMOS, its objective is in order to suppress raceway groove to produce too much hot electron.The cellular construction of OTP parts of the present invention is a NMOS, but wherein has only a side that light doping section 15 is arranged.By removing the light doping section 15 of opposite side, realized the raising that hot electron produces probability and quantity, make hot electron penetrate oxide layer 16 potential barriers of silicon nitride side wall 17 belows, caught by silicon nitride side wall 17, thereby realized programming with CHE mechanism.
See also Fig. 4, the read method of the cellular construction of above-mentioned OTP parts is: bit line 18a making alive V3, programming end 18b ground connection, p trap 12 ground connection, word line 14 making alive V4; VT＜V3＜V4-VT; 2VT＜V4＜3V (volt).。When reading, the direction of channel current, makes the channel region of silicon nitride side wall 17 belows form the hole accumulation, thereby cuts off raceway groove to bit line 18a from programming end 18b.
The data that the cellular construction of OTP parts of the present invention is stored are 0 or 1, its differentiation mode is: before the programming, NMOS produces transoid in gate voltage longitudinal electric field lower channel, shows as under the situation of bit line 18a bias voltage, form big channel current, for example represent 1 this moment.And after the programming, because side wall 17 store electrons, electronics can attract the hole to accumulate in channel surface, channel current is diminished even raceway groove cuts off and do not have electric current, and for example represent 0 this moment.By comparing having or not or size of channel current, realize when reading for the cellular construction storage data 0 of OTP parts and 1 differentiation.For example define channel current and represent 1, represent 0 less than a certain reference value greater than a certain reference value.
In sum, the cellular construction of OTP parts of the present invention has very little area, and is applicable to thin and thicker gate oxide, thereby has expanded range of application greatly.The manufacture method of the cellular construction of described OTP parts is compatible fully with existing CMOS logic process.The method of operation of the cellular construction of described OTP parts is practical and simple and easy.
Claims (7)
1. the cellular construction of an OTP parts, it is characterized in that, the cellular construction of described OTP parts is a NMOS, on the substrate (10) p trap (12), in substrate (10) and/or the p trap (12) isolated area (11) is arranged, gate oxide (13) and oxide layer (16) are arranged on the p trap (12), oxide layer (16) is in the both sides of gate oxide (13), polysilicon gate (14) is arranged on the gate oxide (13), silicon nitride side wall (17) is arranged on the oxide layer (16), silicon nitride side wall (17) is in the both sides of polysilicon gate (14) and contact, the thickness of oxide layer (16) is less than the thickness of gate oxide (13), polysilicon gate (14) only has n type light doping section (15) in the p of side-lower trap (12), the one n type heavily doped region (18a) is arranged in the p trap (12) of the outer side-lower of silicon nitride side wall (17), the 2nd n type heavily doped region (18b), the one n type heavily doped region (18a) is adjacent with n type light doping section (15), the 2nd n type heavily doped region (18b) is not adjacent with n type light doping section (15), and silicon chip surface is coated with layer of silicon dioxide (19);
A described n type heavily doped region (18a) is as bit line;
Described the 2nd n type heavily doped region (18b) is as the programming end;
Described polysilicon gate (14) is as word line.
2. the cellular construction of OTP parts according to claim 1 is characterized in that, the thickness of described oxide layer (16) is
3. the cellular construction of OTP parts according to claim 1 is characterized in that, the thickness of the silicon dioxide (19) of described polysilicon gate (14) top is
4. the manufacture method of the cellular construction of OTP parts as claimed in claim 1 is characterized in that, comprises the steps:
The 1st step formed p trap (12) with extension or ion implantation technology on substrate (10), isolate or shallow grooved-isolation technique formation isolated area (11) with field oxygen in substrate (10) and/or p trap (12);
The 2nd step, thermal oxide growth layer of silicon dioxide on p trap (12), deposit one deck polysilicon again, the described polysilicon layer of etching, with described silicon dioxide layer is etching stop layer, form polysilicon gate (14), the silicon dioxide of polysilicon gate (14) below is gate oxide (13), removes gate oxide (13) described silicon dioxide layer in addition with wet corrosion technique;
In the 3rd step, in the p trap (12) of the only side-lower of polysilicon gate (14), form n type light doping section (15) with ion implantation technology;
In the 4th step, in silicon chip surface thermal oxide growth layer of silicon dioxide (16), THICKNESS CONTROL exists
In the 5th step, on the silicon dioxide layer (16) of polysilicon gate (14) both sides, form silicon nitride side wall (17);
In the 6th step, in the p trap (12) of the outer side-lower of silicon nitride side wall (17), form a n type heavily doped region (18a), the 2nd n type heavily doped region (18b) by ion implantation technology;
The 7th step is in silicon chip surface deposit layer of silicon dioxide (19).
5. the manufacture method of the cellular construction of OTP parts according to claim 4 is characterized in that, described method is feedstock production silicon dioxide layer (19) with tetraethoxysilane and ozone in the 7th step.
6. the method for operation of the cellular construction of OTP parts as claimed in claim 1 is characterized in that, during programming: bit line (18a) ground connection, programming end (18b) making alive V1, p trap (12) ground connection, word line (14) making alive V2;
V1＞V2-VT, described VT are the threshold voltage of NMOS;
0＜V1＜VBD, described VBD is the PN junction puncture voltage between programming end (18b) and the p trap (12);
When reading: bit line (18a) making alive V3, programming end (18b) ground connection, p trap (12) ground connection, word line (14) making alive V4;
VT＜V3＜V4-VT；
2VT＜V4＜3 volt.
7. the method for operation of the cellular construction of OTP parts according to claim 6 is characterized in that, by comparing having or not or size of channel current, realizes for the cellular construction storage data 0 of OTP parts and 1 differentiation.
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| US10127993B2 (en) | 2015-07-29 | 2018-11-13 | National Chiao Tung University | Dielectric fuse memory circuit and operation method thereof |
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| CN104576648B (en) * | 2014-08-19 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | OTP partses and its manufacture method |
| CN106409832B (en) * | 2016-09-30 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Memory unit component and its manufacturing method |
| CN112259545B (en) * | 2020-10-20 | 2021-09-10 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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| TWI311796B (en) * | 2005-11-17 | 2009-07-01 | Ememory Technology Inc | Semiconductor device and manufacturing method thereof |
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