CN102064117A - Method for encapsulating small-size chip - Google Patents

Method for encapsulating small-size chip Download PDF

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Publication number
CN102064117A
CN102064117A CN2010105512690A CN201010551269A CN102064117A CN 102064117 A CN102064117 A CN 102064117A CN 2010105512690 A CN2010105512690 A CN 2010105512690A CN 201010551269 A CN201010551269 A CN 201010551269A CN 102064117 A CN102064117 A CN 102064117A
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Prior art keywords
chip
wafer
chips
solder layer
accompanying
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CN2010105512690A
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CN102064117B (en
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张江元
张元发
蒋慜佶
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Shanghai Kaihong Electronic Co Ltd
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Shanghai Kaihong Electronic Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/0105—Tin [Sn]
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

The invention provides a method encapsulating a small-size chip. The method comprises the following steps: providing a wafer, wherein a plurality of chips are arranged on the front side of the wafer; forming a continuous soldering layer on the back of the wafer; cutting the wafer into a plurality of separate chips, wherein a soldering layer is arranged on the back of each chip; providing a lead wire frame, and adhered the chips to the lead wire frame through the soldering layers on the backs; and bonding lead wires. The method has the advantages that the soldering layers on the backs of the chips and the chips are formed through a cutting step, and the edges of the soldering layers and the chips are aligned, so the chips cannot be immersed in the flexible soldering layers, the chips can be effectively prevented from inclining, and the stability of the subsequent lead wire bonding process is improved.

Description

The method for packing of small size chip
Technical field
The present invention relates to the semiconductor packages field tests, relate in particular to a kind of method for packing of small size chip.
Background technology
Chip (Die) encapsulation needs chip to fit (Die Bond) and lead-in wire bonding (Wire Bond) technology.Traditional method is that these two steps are all implemented on lead frame.But along with the trend of chip miniaturization constantly develops, the size of chip becomes more and more littler, and the power of chip is also more and more higher, so need to adopt have high conductivity and thermal conductivity soft solder with chip attach on lead frame.And the coating area of slicken solder of the prior art on lead frame is very big, thickness is also very thick, with undersized chip mount on slicken solder the time, chip can partly be immersed in the scolder and cause chip to produce, this just brings difficulty for follow-up lead key closing process, and especially the levelness to chip requires good Au/Cu bonding technology etc.
Be the implementation step schematic diagram of the method for packing of a kind of chip in the prior art shown in the accompanying drawing 1, comprise the steps: step S10, a lead frame is provided; Step S11 is at the lead frame surface solder-coating; Step S12 is with the surface of chip attach at scolder; Step S13, the lead-in wire bonding.
Accompanying drawing 2A is to shown in the accompanying drawing 2D being the process chart of said method.
Shown in the accompanying drawing 2A, refer step S10 provides a lead frame 20.The surface of described lead frame 20 should have a chip sticking part 21 and a plurality of terminal pins, and this sentences pin 29 expressions.
Shown in the accompanying drawing 2B, refer step S11 is at lead frame 20 surface applied slicken solders 22.Contain among Sn, Pb, Ag, Bi, Sb and the Cu one or more in the material of the material of this scolder 22, and make glue by organic solvent.Because scolder 22 quality are soft also to have a certain fluidity, therefore the zone of coating is difficult to be controlled at chip size identical substantially, and thickness also is difficult to be controlled in the very thin scope.So scolder 22 will occupy most of zone of chip sticking part 21 and have certain thickness.
Shown in the accompanying drawing 2C, refer step S12 sticks on chip 23 on the surface of scolder 22.In this step, because scolder 22 has certain viscosity, so chip 23 can partly be immersed among the scolder 22.And since chip 23 held up by scolder 22 and near " floating " on scolder 22, in case suffered " buoyancy " of chip 23 is inhomogeneous, just be easy to produce the phenomenon of inclination.What accompanying drawing 2C promptly represented is the phenomenon of said chip 23 run-off the straights.Accompanying drawing 2C exaggerates actual conditions in order to clearly illustrate that the tilt phenomenon of chip 23.In actual process, the inclined degree of chip 23 may not have so big shown in the accompanying drawing 2C, but for follow-up lead key closing process, even the small generation of a bit tilting also might cause situations such as rosin joint.And stick in the process on the scolder 22 and can cause extruding at chip 23, cause scolder 22 to two side flow, even trickle, cause the electricity syndeton disorder of chip, reduce the yield of product to the side of lead frame 20 to scolder 22.
Shown in the accompanying drawing 2D, refer step S13, lead-in wire bonding.This step with pin 29 and chip 23 surfaces corresponding the connection of pad electricity.This step can adopt any one common lead-in wire bonding step, and for example Au/Cu is hybrid bonded or Al metal tape (Al Ribbon) bonding.Because there is inclination on the surface of the chip 23 among the accompanying drawing 2C, the Optical devices that are used for the identification chip surface in the bonding apparatus of causing going between can't be aligned in the focal plane surface of chip 23 exactly, therefore be easy to produce the phenomenon of rosin joint, shown in chip 23 surfaces of accompanying drawing 2D.
To sum up, the shortcoming of prior art is, because scolder 22 quality softnesses cause sticking on the surperficial run-off the straight of its surperficial chip 23, and scolder 22 is squeezed easily and overflows to both sides, thereby had influence on the stability of follow-up lead key closing process, directly caused the yield of packaging body to descend.
Summary of the invention
Technical problem to be solved by this invention is, a kind of method for packing of small size chip is provided, can avoid in the prior art since the surface tilt of chip to the influence of follow-up lead key closing process.
In order to address the above problem, the invention provides a kind of method for packing of small size chip, comprise the steps: to provide a wafer, the front of described wafer has a plurality of chips; Form a continuous solder layer at the back side of wafer; Wafer is cut into a plurality of discrete chips, and the back side of each chip all has solder layer; Lead frame is provided, and the solder layer of chip by the back side sticked on the lead frame; The lead-in wire bonding.
The invention has the advantages that: the solder layer of chip back forms by step of cutting simultaneously with chip, both edges align, therefore chip is not immersed in the flexible solder layer, can effectively avoid the chip run-off the straight, and the thickness homogeneous and controllable of solder layer, avoid the generation spillover, thereby improved the stability of follow-up lead key closing process.
Description of drawings
Accompanying drawing 1 is the implementation step schematic diagram of a kind of chip packaging method of the prior art.
Accompanying drawing 2A is the process chart of the chip packaging method shown in the accompanying drawing 1 to accompanying drawing 2D.
Accompanying drawing 3 is implementation step schematic diagrames of the described method of this embodiment.
Accompanying drawing 4A to 4E is the process chart of the described method of this embodiment.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to the method for packing of a kind of small size chip provided by the invention.
Be the implementation step schematic diagram of the described method of this embodiment shown in the accompanying drawing 3, comprise: step S30, a wafer is provided, the front of described wafer has a plurality of chips; Step S31 forms a continuous solder layer at the back side of wafer; Step S32 cuts into a plurality of discrete chips with wafer, and the back side of each chip all has solder layer; Step S33 provides lead frame, and the solder layer of chip by the back side sticked on the lead frame; Step S34, the lead-in wire bonding.
Accompanying drawing 4A is to shown in the accompanying drawing 4E being the process chart of said method.
Shown in the accompanying drawing 4A, refer step S30 provides a wafer 40, and the front of described wafer 40 has a plurality of chips, and present embodiment is with chip 411,412 and 413 examples.The material of described wafer 40 can be any one material that comprises monocrystalline silicon.Described chip 411～413 can be any one common semiconductor chip, comprises memory, logical circuit or independent MOS transistor etc., even also can be photoelectric devices such as light-emitting diode.Before carrying out subsequent step, can also implement preparation process such as grinding back surface as required to wafer.
Shown in the accompanying drawing 4B, refer step S31 forms a continuous solder layer 42 at the back side of wafer 40.In this step, the method that forms solder layer 42 be selected from coating and paste in a kind of.So-called coating is meant that will have flexibility forms continuous solder layer 42 with the back side that mobile scolder is coated in wafer 40 equably, can also further make solder layer 42 flattening surfaces by methods such as rotations.The so-called continuous solder layer that is meant preparing separately by other technologies of pasting shifts the back side that sticks on wafer 40.Contain among Sn, Pb, Ag, Bi, Sb and the Cu one or more in the material of solder layer 42, and make glue by organic solvent.Owing to adopted the method at wafer 40 back side solder-coating layers 42, therefore than the technology that forms solder layer in the prior art on lead frame, present embodiment can obtain to have the more solder layer 42 of minimal thickness.In the present embodiment, the thickness range of solder layer 42 is 10 μ m～60 μ m.
Shown in the accompanying drawing 4C, refer step S32 cuts into a plurality of discrete chips 411,412 and 413 with wafer 40, and the back side of each chip all has solder layer, corresponds to solder layer 421,422 and 423.This step can at first be pasted blue film on the surface of solder layer 42, and then carry out laser or machine cuts, the solder layer 42 at the wafer 40 and the back side is cut off simultaneously, form a plurality of discrete chips 411,412 and 413, and in follow-up paster technique, discrete chip is taken off from blue film as required one by one.Because solder layer 42 is one deck continuous films, therefore the back side of each chip after the cutting can both remain with solder layer.
Following steps will be that example describes with chip 411.The follow-up encapsulation process of other chip 412,413 and other each chips is all with reference to following steps.
Shown in the accompanying drawing 4D, refer step S33 provides lead frame 20, and the solder layer 421 of chip 411 by the back side sticked on the lead frame 20.The surface of lead frame 20 should have a chip sticking part 21 and a plurality of terminal pins, and this sentences pin 21 expressions.Because the solder layer 421 at the back side forms by cutting in step S32 simultaneously with chip 411, both edges align, therefore chip 421 is not immersed in the flexible solder layer 421, therefore can effectively avoid chip 411 run-off the straight in this step.And the thickness that can control solder layer 42 in step S31 at an easy rate should not be too thick, avoids it to receive extruding in this step and be spilled over to the side of lead frame 20.Practice shows that the thickness range of solder layer 42 can avoid this phenomenon to take place between 10 μ m～60 μ m.
Shown in the accompanying drawing 4E, refer step S34, lead-in wire bonding.This step can adopt any one common lead-in wire bonding step, and for example Au/Cu is hybrid bonded or Al metal tape (Al Ribbon) bonding.Because the surface of the chip 411 among the accompanying drawing 4D is levels, the Optical devices that are used for the identification chip surface in the lead-in wire bonding apparatus can be aligned in the focal plane surface of chip 411 exactly, therefore can not have influence on the stability of follow-up lead key closing process, can improve the yield of packaging body.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (4)

1. the method for packing of a small size chip is characterized in that, comprises the steps:
One wafer is provided, and the front of described wafer has a plurality of chips;
Form a continuous solder layer at the back side of wafer;
Wafer is cut into a plurality of discrete chips, and the back side of each chip all has solder layer;
Lead frame is provided, and the solder layer of chip by the back side sticked on the lead frame;
The lead-in wire bonding.
2. the method for packing of small size chip according to claim 1 is characterized in that, the described method that forms solder layer at wafer rear be selected from coating and paste in a kind of.
3. the method for packing of small size chip according to claim 1 is characterized in that, contains among Sn, Pb, Ag, Bi, Sb and the Cu one or more in the material of described solder layer.
4. the method for packing of small size chip according to claim 1 is characterized in that, the thickness range of described solder layer is 10 μ m～60 μ m.
CN2010105512690A 2010-11-19 2010-11-19 Method for encapsulating small-size chip Active CN102064117B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103500724A (en) * 2013-09-02 2014-01-08 扬州虹扬科技发展有限公司 Prewelding method for Schottky grains
CN116313940A (en) * 2023-05-18 2023-06-23 上海聚跃检测技术有限公司 Cutting method and auxiliary cutting device for wire bonding structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1181619A (en) * 1996-10-31 1998-05-13 国际商业机器公司 Flip chip attach on flexible circuit carrier using chip with metallic cap on solder
US20010015493A1 (en) * 1998-09-03 2001-08-23 Hembree David R. Chip on board with heat sink attachment
CN101533783A (en) * 2008-03-13 2009-09-16 上海凯虹电子有限公司 Thin quad flat no-lead package method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1181619A (en) * 1996-10-31 1998-05-13 国际商业机器公司 Flip chip attach on flexible circuit carrier using chip with metallic cap on solder
US20010015493A1 (en) * 1998-09-03 2001-08-23 Hembree David R. Chip on board with heat sink attachment
CN101533783A (en) * 2008-03-13 2009-09-16 上海凯虹电子有限公司 Thin quad flat no-lead package method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103500724A (en) * 2013-09-02 2014-01-08 扬州虹扬科技发展有限公司 Prewelding method for Schottky grains
CN116313940A (en) * 2023-05-18 2023-06-23 上海聚跃检测技术有限公司 Cutting method and auxiliary cutting device for wire bonding structure
CN116313940B (en) * 2023-05-18 2023-08-11 上海聚跃检测技术有限公司 Cutting method and auxiliary cutting device for wire bonding structure

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