JP2014116561A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises: stacking a plurality of semiconductor wafers 50 each including a plurality of chip formation regions 50a and dicing regions 50b each arranged between the plurality of adjacent chip formation regions 50a, with an insulating encapsulation material layer 6 between each two semiconductor wafers 50; preliminarily removing the encapsulation material layers 6 arranged in regions which overlap the dicing regions 50b; and running dicing blades 44 along the dicing regions 50b here the encapsulation material layers 6 are removed thereby to obtain a plurality of chip laminates MCS.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device in which a plurality of semiconductor chips are stacked.

  Japanese Patent Laying-Open No. 2011-71441 (Patent Document 1) describes a method for manufacturing a semiconductor device in which a plurality of semiconductor wafers are stacked with an underfill interposed therebetween and then diced.

JP 2011-71441 A

  The inventor of the present application is examining a technique for improving the performance of a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board. As part of this, a semiconductor device in which a plurality of semiconductor chips are stacked was examined.

  As a method of laminating a plurality of semiconductor chips, a plurality of semiconductor chips are laminated by preparing a plurality of semiconductor wafers, laminating each with an insulating sealing material interposed therebetween, and then dicing the wafer laminate. There is a stacking method for obtaining a plurality of chip stacks. In such a lamination method, different members (for example, a semiconductor substrate made of silicon (Si) and an insulating sealing material) are alternately laminated also in the dicing region.

  However, the inventor of the present application has found that there is a problem in terms of reliability of the obtained semiconductor device when a dicing blade is run and cut in a dicing region where different members are stacked.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A method of manufacturing a semiconductor device according to an embodiment includes: a plurality of semiconductor wafers each having a plurality of chip forming regions and dicing regions provided between adjacent chip forming regions; And a step of laminating. Moreover, the sealing material layer arrange | positioned in the area | region which overlaps with the said dicing area | region is removed previously. In addition, a plurality of chip stacks are obtained by running a dicing blade along the dicing region from which the sealing material layer has been removed.

  According to the one embodiment, the reliability of the semiconductor device can be improved.

It is a perspective view of the semiconductor device which is one embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 2 is a perspective plan view showing an internal structure of a semiconductor device on a wiring board in a state where a sealing body shown in FIG. 1 is removed. It is sectional drawing along the AA line of FIG. FIG. 5 is an explanatory diagram schematically illustrating a circuit configuration example of the semiconductor device illustrated in FIGS. 1 to 4. It is an expanded sectional view of the A section shown in FIG. FIG. 5 is a plan view illustrating a layout example on the surface side of the logic chip illustrated in FIG. 4. It is a top view which shows an example of the back surface side of the logic chip shown in FIG. FIG. 5 is a plan view illustrating a layout example on the front surface side of the memory chip illustrated in FIG. 4. FIG. 10 is a plan view illustrating an example of a back surface side of the memory chip illustrated in FIG. 9. It is explanatory drawing which shows the outline | summary of the manufacturing process of the semiconductor device demonstrated using FIGS. It is a perspective view of the chip laminated body prepared in the chip laminated body preparing step shown in FIG. It is explanatory drawing which shows the detailed process flow of the chip laminated body preparation process shown in FIG. It is explanatory drawing which shows the process flow which is an examination example with respect to FIG. FIG. 15 is a cross-sectional view schematically showing a state in which a wafer stack is singulated in the singulation process shown in FIG. 14. It is a top view of the semiconductor wafer prepared in each of the 1st, 2nd, 3rd, and 4th wafer preparation process shown in FIG. It is an expanded sectional view along the AA line of FIG. It is explanatory drawing which shows the detailed process contained in the 1st, 2nd, 3rd, and 4th wafer preparation process shown in FIG. 13, and a 1st, 2nd, 3rd, and 4th groove | channel formation process. It is an expanded sectional view which shows the semiconductor substrate prepared in the semiconductor substrate preparation process shown in FIG. FIG. 20 is an enlarged cross-sectional view showing a state where a plurality of holes are formed in the semiconductor substrate shown in FIG. 19. FIG. 21 is an enlarged cross-sectional view illustrating a state in which a metal material is embedded in a plurality of holes illustrated in FIG. 20. FIG. 22 is an enlarged cross-sectional view showing a state in which a chip wiring layer is formed on the main surface of the semiconductor substrate shown in FIG. 21. FIG. 23 is an enlarged cross-sectional view illustrating a state in which a sealing material layer is stacked on the surface of the semiconductor wafer illustrated in FIG. 22. FIG. 24 is an enlarged cross-sectional view showing a state where a plurality of through holes are formed in the sealing material layer shown in FIG. 23. FIG. 25 is an enlarged cross-sectional view illustrating a state in which a conductive pillar is formed by embedding a metal material in the plurality of through holes illustrated in FIG. 24. It is sectional drawing which shows the state which formed the groove | channel in the semiconductor wafer shown in FIG. It is an expanded sectional view which expands and shows one of the dicing area | regions shown in FIG. It is sectional drawing which shows the state which laminated | stacked the semiconductor wafer in the 2nd wafer mounting process shown in FIG. It is an expanded sectional view which expands and shows one of the dicing area | regions shown in FIG. FIG. 29 is an enlarged cross-sectional view showing the periphery of a region where a plurality of surface electrodes are formed in the chip formation region shown in FIG. 28; It is sectional drawing which shows the state which grinded the back surface of the upper stage semiconductor wafer in the 2nd wafer back surface grinding process shown in FIG. FIG. 32 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG. 31 in an enlarged manner. FIG. 32 is an enlarged cross-sectional view showing an enlargement of the periphery of a region where a plurality of surface electrodes are formed in the chip formation region shown in FIG. 31. It is sectional drawing which shows the state which laminated | stacked the semiconductor wafer in the 3rd wafer mounting process shown in FIG. It is an expanded sectional view which expands and shows one of the dicing area | regions shown in FIG. FIG. 35 is an enlarged cross-sectional view showing the periphery of a region where a plurality of surface electrodes are formed in the chip formation region shown in FIG. 34; It is sectional drawing which shows the state which ground the back surface of the semiconductor wafer of the upper stage in the 3rd wafer back surface grinding process shown in FIG. It is sectional drawing which shows the state which laminated | stacked the semiconductor wafer in the 4th wafer mounting process shown in FIG. It is sectional drawing which shows the state which ground the back surface of the upper stage semiconductor wafer in the 4th wafer back surface grinding process shown in FIG. FIG. 14 is a cross-sectional view showing a state in which a plurality of protruding electrodes are formed on the back surface of the uppermost semiconductor wafer in the electrode forming step shown in FIG. 13. FIG. 41 is an enlarged cross-sectional view showing a periphery of a region where a plurality of protruding electrodes are formed in the chip formation region shown in FIG. 40. It is sectional drawing which shows the state which ground the semiconductor wafer in the 1st wafer back surface grinding process shown in FIG. It is sectional drawing which shows the individualization process shown in FIG. FIG. 44 is an enlarged cross-sectional view showing the periphery of the dicing area shown in FIG. 43 in an enlarged manner. It is a top view which shows the whole structure of the wiring board prepared by the board | substrate preparation process shown in FIG. FIG. 46 is an enlarged plan view of one device region shown in FIG. 45. It is an expanded sectional view along the AA line of FIG. It is an enlarged plan view which shows the state which has arrange | positioned the adhesive material in the chip | tip mounting area | region shown in FIG. It is an expanded sectional view along the AA line of FIG. It is explanatory drawing which shows typically the outline | summary of the manufacturing process of the semiconductor chip provided with the penetration electrode shown in FIG. FIG. 51 is an explanatory diagram schematically showing an overview of the manufacturing process of the semiconductor chip following FIG. 50; FIG. 49 is an enlarged plan view showing a state in which a logic chip is mounted on a chip mounting region of the wiring board shown in FIG. 48. It is an expanded sectional view along the AA line of FIG. FIG. 53 is an enlarged plan view showing a state in which an adhesive is arranged on the back surface and the periphery of the semiconductor chip shown in FIG. 52; It is an expanded sectional view along the AA line of FIG. FIG. 55 is an enlarged plan view showing a state in which a stacked body of memory chips is mounted on the back surface of the logic chip shown in FIG. 54. It is an expanded sectional view along the AA line of FIG. FIG. 58 is an enlarged cross-sectional view showing a state where a sealing body is formed on the wiring substrate shown in FIG. 57 and a plurality of stacked semiconductor chips are sealed. It is a top view which shows the whole structure of the sealing body shown in FIG. FIG. 59 is an enlarged cross-sectional view showing a state in which solder balls are bonded onto a plurality of lands of the wiring board shown in FIG. 58. FIG. 61 is a cross-sectional view showing a state in which the multi-cavity wiring board shown in FIG. 60 is separated. FIG. 43 is an enlarged cross-sectional view showing a modified example with respect to FIG. 42. In the modification with respect to FIG. 40, it is an expanded sectional view which expands and shows the periphery of a dicing area | region. FIG. 64 is an enlarged cross-sectional view showing a further modification to FIG. 63. It is sectional drawing which shows the modification with respect to FIG. It is explanatory drawing which shows the process flow which is a modification with respect to FIG. 13 which forms the chip | tip laminated body shown in FIG. FIG. 69 is a cross-sectional view showing a modified example of FIG. 28 and showing a state after the second wafer mounting step shown in FIG. 66. FIG. 67 is a cross-sectional view showing a state in which grooves are formed along the dicing region of the semiconductor wafer in the second groove forming step shown in FIG. 66. FIG. 69 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG. 68 in an enlarged manner. FIG. 67 is an enlarged cross-sectional view showing the periphery of a dicing region after the fourth groove forming step shown in FIG. 66. FIG. 71 is an enlarged cross-sectional view showing a state in which the wafer laminated body shown in FIG. 70 has been cut. It is a perspective view which shows the modification with respect to the chip laminated body shown in FIG. FIG. 75 is an explanatory diagram showing a process flow which is a modification example of FIG. 13 for forming the chip stack shown in FIG. 72; FIG. 74 is a cross-sectional view showing the support member prepared in the support member preparation step shown in FIG. 73 and the semiconductor wafer prepared in the second wafer preparation step. FIG. 74 is a cross-sectional view showing a state in which a semiconductor wafer is stacked on a support member in the second wafer mounting step shown in FIG. 73. FIG. 74 is an enlarged cross-sectional view showing an enlarged periphery of a dicing region at the time when the fourth wafer back surface grinding step shown in FIG. 73 is completed.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component” or the like. For example, the term “silicon member” is not limited to pure silicon, but a member containing a silicon-germanium (SiGe) alloy, other multi-component alloys containing silicon as a main component, or other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In this application, the terms “upper surface” or “lower surface” may be used. However, since there are various modes for mounting a semiconductor package, for example, the upper surface is disposed below the lower surface after mounting the semiconductor package. Sometimes it is done. In the present application, the plane on the element forming surface side of the semiconductor chip is described as the front surface, and the surface opposite to the front surface is described as the back surface. Further, a plane on the chip mounting surface side of the wiring board is described as an upper surface or a surface, and a surface positioned on the opposite side of the upper surface is described as a lower surface.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

  In the embodiment described below, as an example of a semiconductor device in which a plurality of semiconductor chips are stacked, the operation of the stacked body in which a plurality of semiconductor chips in which a memory circuit is formed is stacked in one package and the operation of the memory circuit is controlled. A semiconductor chip on which a semiconductor chip on which a control circuit is formed is mounted will be described.

(Embodiment 1)
FIG. 1 is a perspective view of the semiconductor device of the present embodiment, and FIG. 2 is a bottom view of the semiconductor device shown in FIG. FIG. 3 is a perspective plan view showing the internal structure of the semiconductor device on the wiring board with the sealing body shown in FIG. 1 removed. 4 is a cross-sectional view taken along the line AA in FIG. FIG. 5 is an explanatory view schematically showing a circuit configuration example of the semiconductor device shown in FIGS. 1 to 4, the number of terminals is reduced for the sake of clarity, but the number of terminals (for example, bonding leads 2f, lands 2g, solder balls 5) is shown in FIGS. It is not limited to the aspect shown in. In FIG. 3, the outline of the logic chip LC is indicated by a dotted line in order to make it easy to see the positional relationship and the planar size difference between the logic chip LC and the memory chip MC4 in plan view.

<Semiconductor device>
First, a schematic configuration of the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. The semiconductor device 1 according to the present embodiment includes a wiring board 2, a plurality of semiconductor chips 3 (see FIG. 4) mounted on the wiring board 2, and a sealing body 4 that is a resin body that seals the plurality of semiconductor chips 3. Is provided.

  As shown in FIG. 4, the wiring board 2 includes an upper surface (also referred to as a surface, main surface, or chip mounting surface) 2a on which a plurality of semiconductor chips 3 are mounted, and a lower surface (surface, main surface) opposite to the upper surface 2a. 2b), and a side surface 2c disposed between the upper surface 2a and the lower surface 2b. Further, the wiring board 2 has a quadrangular outer shape in plan view as shown in FIGS. In the example shown in FIGS. 2 and 3, the planar size of the wiring board 2 (that is, the dimension in plan view, the dimension of the upper surface 2a and the lower surface 2b, also referred to as the outer size) is, for example, a square having a side length of about 14 mm. Make it. Further, the thickness (in other words, the height) of the wiring board 2, that is, the distance from the upper surface 2a to the lower surface 2b shown in FIG. 4 is, for example, about 0.3 mm to 0.5 mm.

  The wiring substrate 2 is an interposer for electrically connecting the semiconductor chip 3 mounted on the upper surface 2a side and a mounting substrate (not shown), and a plurality of wiring layers electrically connecting the upper surface 2a side and the lower surface 2b side. (4 layers in the example shown in FIG. 4). In each wiring layer, a plurality of wirings 2d and an insulating layer 2e that insulates between the plurality of wirings 2d and between adjacent wiring layers are formed. Here, the wiring substrate 2 of the present embodiment has three insulating layers 2e, and the middle insulating layer 2e is a core layer, but does not have the insulating layer 2e serving as a core, so-called A coreless substrate may be used. The wiring 2d includes a wiring 2d1 formed on the upper surface or the lower surface of the insulating layer 2e, and a via wiring 2d2 that is an interlayer conductive path formed so as to penetrate the insulating layer 2e in the thickness direction.

  A plurality of bonding leads (also referred to as terminals, chip mounting surface side terminals, or electrodes) 2 f that are terminals electrically connected to the semiconductor chip 3 are formed on the upper surface 2 a of the wiring board 2. On the other hand, on the lower surface 2b of the wiring board 2, a plurality of lands 2g, to which a plurality of solder balls 5 which are terminals for electrical connection to a mounting board (not shown), that is, external connection terminals of the semiconductor device 1, are joined. Is formed. The plurality of bonding leads 2f and the plurality of lands 2g are electrically connected to each other via a plurality of wirings 2d. Since the wiring 2d connected to the bonding lead 2f and the land 2g is formed integrally with the bonding lead 2f and the land 2g, in FIG. 4, the bonding lead 2f and the land 2g are shown as a part of the wiring 2d. Yes.

  Further, the upper surface 2a and the lower surface 2b of the wiring board 2 are covered with insulating films (specifically, solder resist films) 2h and 2k. The wiring 2d formed on the upper surface 2a of the wiring board 2 is covered with an insulating film 2h. An opening is formed in the insulating film 2h, and at least a part of the plurality of bonding leads 2f (for example, a bonding portion with the semiconductor chip 3) is exposed from the insulating film 2h in the opening. Further, the wiring 2d formed on the lower surface 2b of the wiring board 2 is covered with an insulating film 2k. An opening is formed in the insulating film 2k, and at least a part of the plurality of lands 2g (for example, a joint with the solder ball 5) is exposed from the insulating film 2k in the opening.

  As shown in FIG. 4, a plurality of solder balls (external terminals, electrodes, external electrodes) 5 bonded to a plurality of lands 2g on the lower surface 2b of the wiring board 2 are arranged in a matrix (array) as shown in FIG. Arranged in a matrix or matrix). Although not shown in FIG. 2, a plurality of lands 2g (see FIG. 4) to which a plurality of solder balls 5 are joined are also arranged in a matrix. A semiconductor device in which a plurality of external terminals (for example, solder balls 5 and lands 2g) are arranged in a matrix on the mounting surface side of the wiring board 2 is called an area array type semiconductor device. Since the area array type semiconductor device 1 can effectively utilize the lower surface 2b side, which is the mounting surface of the wiring board 2, as an external terminal arrangement space, the mounting area of the semiconductor device can be increased even if the number of external terminals increases. It is preferable at the point which can suppress an increase. That is, a semiconductor device in which the number of external terminals increases with higher functionality and higher integration can be mounted in a space-saving manner.

  The semiconductor device 1 includes a plurality of semiconductor chips 3 mounted on the wiring board 2. The plurality of semiconductor chips 3 are stacked on the upper surface 2 a of the wiring board 2. Each of the plurality of semiconductor chips 3 includes a front surface (also referred to as a main surface or an upper surface) 3a, a back surface (also referred to as a main surface or a lower surface) 3b opposite to the front surface 3a, and a space between the front surface 3a and the back surface 3b. And has a rectangular outer shape in plan view as shown in FIG. As described above, by stacking a plurality of semiconductor chips, the mounting area can be reduced even when the function of the semiconductor device 1 is enhanced.

  In the example shown in FIG. 4, the semiconductor chip 3 mounted at the lowest stage (in other words, the position closest to the wiring board 2) is a logic chip (semiconductor chip) LC on which an arithmetic processing circuit PU (see FIG. 5) is formed. It is. On the other hand, the semiconductor chip 3 mounted on the upper side of the logic chip LC is a memory chip (semiconductor chip) in which a main memory circuit MM (see FIG. 5) for storing data communicated with the logic chip LC is formed. MC1, MC2, MC3, and MC4. In the example shown in FIG. 4, the plurality of memory chips MC1, MC2, MC3, and MC4 are stacked via an insulating sealing material layer 6 (also referred to as a chip stacked body sealing body or chip stacked body resin body). In addition, a chip stack (also referred to as a semiconductor chip stack or a memory chip stack) MCS that is bonded and fixed is configured.

  Between the plurality of memory chips MC1, MC2, MC3, and MC4, a sealing material layer 6 different from the sealing body 4 is disposed, and the electrical connection portions of the memory chips MC1, MC2, MC3, and MC4 are sealed. Sealed by the material layer 6. The sealing material layer 6 is embedded so as to be in close contact with the front surface 3a and the back surface 3b of the plurality of memory chips MC1, MC2, MC3, and MC4. The chip stack MCS of the memory chips MC1, MC2, MC3, and MC4 includes each semiconductor The joint portion between the chips 3 and the sealing material layer 6 are integrated. The sealing material layer 6 is made of an insulating (non-conductive) material (for example, a resin material). However, as shown in FIG. 4, the surface 3a of the memory chip MC1 mounted in the lowest stage (in other words, the position closest to the logic chip LC) among the chip stacks MCS of the memory chips MC1, MC2, MC3, and MC4 is , Exposed from the sealing material layer 6. Of the chip stack MCS of the memory chips MC1, MC2, MC3, and MC4, the back surface 3b of the memory chip MC4 arranged at the uppermost stage is exposed from the sealing material layer 6.

  Further, as shown in FIG. 4, an adhesive material NCL that is an insulating adhesive material is disposed between the plurality of semiconductor chips 3. The adhesive material NCL is disposed so as to block a space between the front surface 3a of the upper semiconductor chip 3 and the back surface 3b of the lower semiconductor chip 3 (or the upper surface 2a of the wiring board 2). Specifically, the adhesive material NCL is an adhesive material NCL1 for bonding and fixing the logic chip LC on the wiring substrate 2, and an adhesive material NCL2 for bonding and fixing the chip stack MCS of the memory chips MC1, MC2, MC3, and MC4 on the logic chip. including. The adhesives NCL1 and NCL2 are each made of an insulating (in other words, non-conductive) material (for example, a resin material), and are a junction between the logic chip LC and the wiring board 2, and the logic chip LC and the chip stack MCS. By disposing the adhesive material NCL at the joints, a plurality of electrodes provided at the joints can be electrically insulated.

  The semiconductor device 1 also includes a sealing body 4 that seals the plurality of semiconductor chips 3. The sealing body 4 is positioned between an upper surface (also referred to as a surface or a front surface) 4a, a lower surface (also referred to as a surface or a back surface) 4b (see FIG. 4) located on the opposite side of the upper surface 4a, and between the upper surface 4a and the lower surface 4b. And has a rectangular outer shape in plan view. In the example shown in FIG. 1, the planar size of the sealing body 4 (that is, the dimension when viewed in plan from the upper surface 4 a side, also referred to as the outer size of the upper surface 4 a) is the same as the planar size of the wiring board 2. The side surface 4 c of the stationary body 4 is continuous with the side surface 2 c of the wiring board 2. Moreover, in the example shown in FIG. 1, the planar size of the sealing body 4 forms a square whose length of one side is about 14 mm, for example.

The sealing body 4 is a resin body that protects the plurality of semiconductor chips 3 and is thin by forming the sealing body 4 in close contact with the semiconductor chips 3 and between the semiconductor chip 3 and the wiring substrate 2. Damage to the semiconductor chip 3 can be suppressed. Moreover, the sealing body 4 is comprised with the following materials from a viewpoint of improving the function as a protection member, for example. Since the sealing body 4 is easily adhered to a plurality of semiconductor chips 3 and between the semiconductor chips 3 and the wiring substrate 2 and has a certain degree of hardness after sealing, for example, an epoxy resin or the like is required. It is preferable that a thermosetting resin is included. Moreover, in order to improve the function of the sealing body 4 after hardening, for example, filler particles such as silica (silicon dioxide; SiO ₂ ) particles are preferably mixed in the resin material. For example, from the viewpoint of suppressing damage to the semiconductor chip 3 due to thermal deformation after the sealing body 4 is formed, the mixing ratio of the filler particles is adjusted to bring the linear expansion coefficients of the semiconductor chip 3 and the sealing body 4 closer. It is preferable.

<Circuit configuration of semiconductor device>
Next, a circuit configuration example of the semiconductor device 1 will be described. As shown in FIG. 5, the logic chip LC is formed with a control circuit CU for controlling the operation of the main memory circuit MM of the memory chips MC1, MC2, MC3, and MC4 in addition to the arithmetic processing circuit PU described above. The logic chip LC is formed with an auxiliary memory circuit SM having a smaller storage capacity than the main memory circuit MM, such as a cache memory for temporarily storing data. In FIG. 5, as an example, the arithmetic processing circuit PU, the control circuit CU, and the auxiliary memory circuit SM are collectively shown as a core circuit (or main circuit) CR1. However, the circuit included in the core circuit CR1 may include circuits other than those described above.

  Further, the logic chip LC is formed with an external interface circuit (or external input / output circuit) GIF for inputting / outputting signals to / from an external device (not shown). A signal line SG for transmitting a signal between the logic chip LC and an external device (not shown) is connected to the external interface circuit GIF. The external interface circuit GIF is also electrically connected to the core circuit CR1, and the core circuit CR1 can transmit signals to external devices via the external interface circuit GIF.

  In addition, the logic chip LC is formed with an internal interface circuit (or internal input / output circuit) NIF for inputting / outputting signals to / from internal devices (for example, memory chips MC1, MC2, MC3, MC4). . The internal interface circuit NIF is connected to a data line DS that is a signal line that transmits a data signal, an address line AS that is a signal line that transmits an address signal, and a signal line OS that transmits other signals. The data line DS, address line AS, and signal line OS are connected to the internal interface circuits NIF of the memory chips MC1, MC2, MC3, and MC4, respectively. In FIG. 5, a circuit for inputting / outputting signals to / from electronic components other than the logic chip LC, such as the external interface circuit GIF and the internal interface circuit NIF, is shown as an input / output circuit NS1.

  The logic chip LC includes a power supply circuit DR that supplies a potential for driving the core circuit CR1 and the input / output circuit NS1. The power supply circuit DR is supplied with a power supply circuit (or input / output power supply circuit) DR1 for supplying a voltage for driving the input / output circuit NS1 of the logic chip LC and a voltage for driving the core circuit CR1 of the logic chip LC. A power supply circuit (or core power supply circuit) DR2 is included. For example, a plurality of different potentials (for example, a first power supply potential and a second power supply potential) are supplied to the power supply circuit DR, and a voltage applied to the core circuit CR1 and the input / output circuit NS1 is defined by the potential difference.

  A circuit in which circuits necessary for the operation of a certain device or system are formed on a single semiconductor chip 3 like a logic chip LC is called SoC (System on a Chip). By the way, if the main memory circuit MM shown in FIG. 5 is formed in the logic chip LC, the system can be configured by one logic chip LC. However, the required capacity of the main memory circuit MM (see FIG. 5) varies depending on the device or system to be operated. Therefore, the versatility of the logic chip LC can be improved by forming the main memory circuit MM in the semiconductor chip 3 different from the logic chip LC.

  Further, by connecting a plurality of memory chips MC1, MC2, MC3, and MC4 according to the required storage capacity of the main memory circuit MM, the degree of freedom in designing the capacity of the memory circuit included in the system is improved. . In the example shown in FIG. 5, the main memory circuit MM is formed in each of the memory chips MC1, MC2, MC3, and MC4. In FIG. 5, the main memory circuit MM is shown as the core circuit CR2 of the memory chips MC1, MC2, MC3, MC4. However, the circuit included in the core circuit CR2 may include a circuit other than the main memory circuit MM.

  The memory chips MC1, MC2, MC3, and MC4 are each formed with an internal interface circuit NIF that inputs and outputs signals to and from an internal device (for example, a logic chip LC). In FIG. 5, an internal interface circuit NIF that performs input / output of signals to / from electronic components other than the memory chips MC1, MC2, MC3, and MC4 is shown as an input / output circuit NS2.

  In addition, the memory chips MC1, MC2, MC3, and MC4 include a power supply circuit (in other words, a drive circuit) DR that supplies a potential for driving the core circuit CR2 and the input / output circuit NS2. The power supply circuit DR supplies a voltage for driving the input / output circuit NS2 of the memory chips MC1, MC2, MC3, and MC4. The power supply circuit (or input / output power supply circuit) DR3 and the memory chips MC1, MC2, MC3, A power supply circuit (or core power supply circuit) DR4 that supplies a voltage for driving the core circuit CR2 of MC4 is included. For example, a plurality of different potentials (for example, a first power supply potential and a second power supply potential) are supplied to the power supply circuit DR, and a voltage applied to the core circuit CR2 and the input / output circuit NS2 is defined by the potential difference.

  In the example shown in FIG. 5, the power supply circuit DR1 of the logic chip LC and the power supply circuit DR3 of the memory chips MC1, MC2, MC3, and MC4 are combined. In other words, the input / output circuit NS1 of the logic chip LC and the input / output circuit NS2 of the memory chips MC1, MC2, MC3, and MC4 are driven by applying the same voltage supplied from the power supply line V2. In this way, by sharing part or all of the power supply circuit DR, the number of power supply lines V1, V2, and V3 that supply a potential (in other words, drive voltage) to the power supply circuit can be reduced. Further, if the number of power supply lines V1, V2, and V3 is reduced, the number of electrodes formed on the logic chip LC can be reduced.

  The internal interface circuit NIF of the logic chip LC and the input / output circuits NS2 of the memory chips MC1, MC2, MC3, and MC4 are electrically connected to each other. A semiconductor device 1 in which circuits necessary for the operation of a certain device or system are collectively formed in one semiconductor device 1 is called a SiP (System in Package). 4 shows an example in which four memory chips MC1, MC2, MC3, and MC4 are stacked on one logic chip LC. However, as described above, the number of stacked semiconductor chips 3 can be variously modified. There is an example. Although illustration is omitted, for example, the minimum configuration can be applied to a modification in which one memory chip MC1 is mounted on one logic chip LC.

  In addition, from the viewpoint of improving the versatility of the logic chip LC and the memory chips MC1, MC2, MC3, and MC4, the planar size of the logic chip LC and the memory chips MC1, MC2, MC3, and MC4 (that is, dimensions and surfaces in plan view). 3a and back surface 3b) are preferably minimized within a range in which the function of each semiconductor chip 3 can be achieved. The logic chip LC can reduce the planar size by improving the integration degree of circuit elements. On the other hand, the capacity of the main memory circuit MM and the transmission speed (for example, the data transfer amount depending on the width of the data bus) change according to the plane size. There is a case.

  For this reason, in the example shown in FIG. 4, the planar size of the memory chip MC4 is larger than the planar size of the logic chip LC. For example, the planar size of the memory chip MC4 is a quadrangle whose side is about 8 mm to 10 mm, whereas the planar size of the logic chip LC is a quadrangle whose side is about 5 mm to 6 mm. Although not shown, the planar size of the memory chips MC1, MC2, and MC3 shown in FIG. 4 is the same as the planar size of the memory chip MC4.

  Further, as described above, the logic chip LC is formed with the external interface circuit GIF for inputting / outputting signals to / from an external device (not shown). From the viewpoint of shortening the transmission distance from the external device, a plurality of logic chips LC are provided. The stacking order of the semiconductor chips 3 is preferably such that the logic chip LC is mounted at the lowest stage, that is, at a position closest to the wiring board 2. That is, it is preferable to stack the semiconductor chip 3 (for example, memory chips MC1, MC2, MC3, and MC4) having a large planar size on the semiconductor chip 3 (logic chip LC) having a small planar size as in the semiconductor device 1.

<Details of electrical connection method of stacked semiconductor chips>
Next, details of the logic chip LC and the memory chips MC1, MC2, MC3, and MC4 shown in FIG. 4 and an electrical connection method of each semiconductor chip 3 will be described. 6 is an enlarged cross-sectional view of a portion A shown in FIG. 7 is a plan view showing the front side of the logic chip shown in FIG. 4, and FIG. 8 is a plan view showing an example of the back side of the logic chip shown in FIG. 9 is a plan view showing the front side of the memory chip shown in FIG. 4, and FIG. 10 is a plan view showing an example of the back side of the memory chip shown in FIG. 6 to 10, the number of electrodes is reduced for ease of viewing, but the number of electrodes (for example, the front surface electrode 3 ap, the back surface electrode 3 bp, and the through electrode 3 tsv) is illustrated in FIGS. The embodiment shown in FIG. 10 shows the back surfaces of the memory chips MC1, MC2, and MC3, the structure of the back surface of the memory chip MC4 (see FIG. 4) in which the through electrode 3tsv is not formed on the back surface 3b is shown in FIG. The illustration is omitted.

  The inventor of the present application is examining a technique for improving the performance of the SiP type semiconductor device. As part of this, the signal transmission speed between a plurality of semiconductor chips mounted on the SiP is set to, for example, 12 Gbps (12 gigabits per second). The technology to be improved was examined. As a method of improving the transmission speed between a plurality of semiconductor chips mounted on a SiP, there is a method of increasing the amount of data transmitted at one time by increasing the width of the data bus of the internal interface (hereinafter referred to as bus width expansion). ). As another method, there is a method of increasing the number of transmissions per unit time (hereinafter referred to as high clock). In addition, there is a method in which the above-described bus width expansion method and the clock number increase method are applied in combination. The semiconductor device 1 described with reference to FIGS. 1 to 5 is a semiconductor device in which the transmission speed of the internal interface is improved to 12 Gbps or more by applying a combination of bus width expansion and clock increase.

  For example, the memory chips MC1, MC2, MC3, and MC4 shown in FIG. 4 are so-called wide I / O memories each having a 512-bit data bus width. Specifically, each of the memory chips MC1, MC2, MC3, and MC4 includes four channels each having a data bus width of 128 bits, and the total bus width of these four channels is 512 bits. In addition, the number of transmissions per unit time of each channel is increased to, for example, 3 Gbps or more.

  As described above, when applying a combination of high clock and widening the bus width, it is necessary to operate many data lines at high speed, so the data transmission distance is shortened from the viewpoint of reducing the influence of noise. It is preferable to do. Therefore, as shown in FIG. 4, the logic chip LC and the memory chip MC1 are electrically connected via a conductive member disposed between the logic chip LC and the memory chip MC1. In addition, the plurality of memory chips MC1, MC2, MC3, and MC4 are electrically connected to each other through conductive members disposed between the plurality of memory chips MC1, MC2, MC3, and MC4. In other words, in the semiconductor device 1, the transmission path between the logic chip LC and the memory chip MC1 does not include the wiring board 2 or a wire (not shown). Further, in the semiconductor device 1, the transmission path between the plurality of memory chips MC1, MC2, MC3, and MC4 does not include the wiring board 2 or wires (not shown) (bonding wires). Further, when bonding wires are not interposed in the transmission paths of a plurality of stacked semiconductor chips, the space for wire bonding can be saved, so that the planar size of the entire package can be reduced.

  In the present embodiment, as a method of connecting a plurality of semiconductor chips 3 without wires, through electrodes (internal electrodes) 3tsv penetrating the semiconductor chip 3 in the thickness direction are formed as shown in FIG. A technique for connecting the stacked semiconductor chips 3 through the through electrodes 3tsv is applied.

  For example, the logic chip LC has a plurality of front surface electrodes (also referred to as electrodes or pads) 3ap formed on the front surface 3a and a plurality of back surface electrodes (also referred to as electrodes or pads) 3bp formed on the back surface 3b. . The logic chip LC is formed so as to penetrate from one of the front surface 3a and the back surface 3b toward the other, and a plurality of through electrodes that electrically connect the plurality of front surface electrodes 3ap and the plurality of back surface electrodes 3bp. It has an electrode 3tsv.

  As shown in FIG. 7, some of the plurality of surface electrodes 3ap included in the logic chip LC (for example, the plurality of surface electrodes 3ap1) are arranged in the center portion on the surface 3a. In addition, a part (for example, the plurality of surface electrodes 3ap2) of the plurality of surface electrodes 3ap included in the logic chip LC is arranged along the side of the surface 3a (in other words, the side surface 3c) at the peripheral portion of the surface 3a. ing. Further, as shown in FIG. 8, the plurality of back surface electrodes 3bp included in the logic chip LC are arranged in the center of the back surface 3b.

  Among the plurality of surface electrodes 3ap shown in FIG. 7, the plurality of surface electrodes 3ap1 arranged at the center portion of the surface 3a are the same as the plurality of back surface electrodes 3bp arranged at the center portion of the back surface 3b shown in FIG. Are electrically connected through a plurality of through electrodes 3tsv.

  In the example shown in FIG. 7, among the plurality of surface electrodes 3ap, the plurality of surface electrodes 3ap2 arranged at the peripheral portion of the surface 3a are not joined with the through electrodes 3tsv, and the through electrodes 3tsv shown in FIG. 6 are joined. What is to be mixed. In other words, in the example shown in FIG. 7, the plurality of surface electrodes 3ap2 are a mixture of internal interface electrodes and external interface electrodes. On the other hand, among the plurality of surface electrodes 3ap shown in FIG. 7, most of the plurality of surface electrodes 3ap2 arranged at the periphery of the surface 3a are electrically connected to an external device (not shown) via the wiring board 2 shown in FIG. It is connected to the. Specifically, as shown in FIG. 6, the surface electrode 3ap of the logic chip LC and the bonding lead 2f of the wiring board 2 are electrically connected via the protruding electrode 7b and the solder material 7s.

  Further, for example, each of the plurality of memory chips MC1, MC2, and MC3 is formed so as to penetrate from one of the plurality of surface electrodes 3ap formed on the front surface 3a and the front surface 3a and the back surface 3b toward the other. And a plurality of through electrodes 3tsv that electrically connect the plurality of front surface electrodes 3ap and the plurality of back surface electrodes 3bp. Each of the plurality of through electrodes 3tsv is formed to extend along the thickness direction of the semiconductor chip 3 (from the front surface 3a side to the back surface 3b side).

  Of the plurality of memory chips MC1, MC2, MC3, and MC4, the memory chip MC4 mounted at the top has a plurality of surface electrodes 3ap formed on the surface 3a, and a plurality of through electrodes 3tsv are present. Not done.

  As shown in FIG. 9, the plurality of surface electrodes 3ap included in the memory chips MC1, MC2, MC3, and MC4 are arranged at the center of the surface 3a. As shown in FIG. 10, the plurality of through electrodes 3tsv included in the memory chips MC1, MC2, and MC3 are exposed from the semiconductor substrate at the center of the back surface 3b. Further, as shown in FIG. 6, the plurality of surface electrodes 3ap of the memory chips MC1, MC2, MC3, and MC4 and the plurality of through electrodes 3tsv of the memory chips MC1, MC2, and MC3 are arranged at positions that overlap each other in the thickness direction. Has been.

  Further, as shown in FIG. 9, a plurality of memory regions (in other words, memory circuit element array regions) are provided on the surface 3a side (specifically, on the main surface of the semiconductor substrate) of the memory chips MC1, MC2, MC3, and MC4. MR is provided. In the example shown in FIG. 9, four memory regions MR corresponding to the above four channels are formed. In each memory region MR, a plurality of memory cells (in other words, memory circuit elements) are arranged in an array. The main memory circuit MM described with reference to FIG. 5 is formed in each of the plurality of memory regions MR shown in FIG.

  In the present embodiment, as shown in FIG. 4, the logic chip LC and the memory chips MC1, MC2, MC3, and MC4 are stacked so that the center portions of the surfaces 3a overlap each other. For this reason, as shown in FIG. 9, by arranging the plurality of surface electrodes 3ap of the memory chips MC1, MC2, MC3, and MC4 in the center of the surface 3a, each semiconductor chip 3 having a different planar size is electrically connected. The transmission path distance to be connected can be shortened.

  Each circuit included in the semiconductor chip 3 is formed on the surface 3a side of the semiconductor chip 3. Specifically, the semiconductor chip 3 includes a semiconductor substrate (not shown) made of, for example, silicon (Si), and a plurality of semiconductor elements (not shown) such as transistors are formed on a main surface that is an element forming surface of the semiconductor substrate. Is formed. A wiring layer (not shown) including a plurality of wirings and an insulating film that insulates between the plurality of wirings is stacked on the main surface of the semiconductor substrate (that is, on the surface 3a side). A plurality of wirings in the wiring layer are electrically connected to a plurality of semiconductor elements, respectively, to constitute a circuit. A plurality of surface electrodes 3ap formed on the surface 3a (see FIG. 4) of the semiconductor chip 3 are electrically connected to a semiconductor element through a wiring layer provided between the semiconductor substrate and the surface 3a, and Part of it.

  Therefore, as shown in FIG. 6, by forming the through electrode 3tsv penetrating the semiconductor chip 3 in the thickness direction and electrically connecting the surface electrode 3ap and the through electrode 3tsv, the surface 3a side of the semiconductor chip 3 And a back surface 3b can be electrically connected to each other. Therefore, for example, like the connection structure of the memory chip MC1 and the memory chip MC2 shown in FIG. 6, the through electrode 3tsv of the memory chip MC2 and the surface electrode 3ap of the memory chip MC1 are electrically connected via the connection material 7. If connected, the circuit of the memory chip MC1 and the circuit of the memory chip MC2 can be electrically connected.

  Further, for example, like the connection structure of the logic chip LC and the memory chip MC1 shown in FIG. 6, the back surface electrode 3bp of the logic chip LC and the through electrode 3tsv of the memory chip MC1 are electrically connected via the connection material 7. Then, the circuit of the memory chip MC1 and the circuit of the logic chip LC can be electrically connected.

  Further, for example, like the connection structure of the memory chip MC3 and the memory chip MC4 shown in FIG. 6, the surface electrode 3ap of the memory chip MC4 and the surface electrode 3ap of the memory chip MC3 are electrically connected via the connecting material 7. Then, the circuit of the memory chip MC4 and the circuit of the memory chip MC3 can be electrically connected.

  As described above, according to the present embodiment, since a plurality of semiconductor chips 3 can be electrically connected without using wires, the data transmission distance can be shortened. As a result, the speed of each of the plurality of transmission paths can be increased.

  In the example shown in FIG. 6, a plurality of stacked semiconductor chips 3 are mounted by a so-called face-down mounting method in which the front surface 3a is opposed to the upper surface 2a of the wiring board 2, and the back surface 3b is a wiring. A device mounted in a so-called face-up mounting system that faces the upper surface 2a of the substrate 2 is mixed. For example, the logic chip LC and the memory chip MC4 are each mounted by a face-down mounting method (also called a flip chip connection method). On the other hand, each of the memory chips MC1, MC2, and MC3 is mounted by a face-up mounting method. The reason for the laminated structure as shown in FIG. 6 will be described later.

  Further, the connecting material 7 that electrically connects the plurality of semiconductor chips 3 includes conductive members such as protruding electrodes (also referred to as bump electrodes) 7b, solder materials 7s, and conductor columns 7p. The protruding electrode 7b is a metal member formed by, for example, a plating method. In the example shown in FIG. 6, the protruding electrode 7b is a metal member in which nickel (Ni) and gold (Au) are sequentially laminated by an electroless plating method. Note that the gold (Au) component of the gold (Au) film covering the surface of the nickel member may be dispersed in the solder material 7s when it is joined to the solder material 7s.

  In the example shown in FIG. 6, the plurality of protruding electrodes 7b formed on the back surface 3b of the memory chip MC1 have a dome shape (also referred to as a hemispherical shape). On the other hand, the plurality of protruding electrodes 7b formed on the surface 3a of the logic chip LC has a columnar shape (for example, a cylinder). The shape of these protruding electrodes 7b varies depending on the manufacturing method when forming the protruding electrodes 7b, but is not limited to the embodiment shown in FIG.

  Further, for example, the solder material 7s is made of so-called lead-free solder that does not substantially contain lead (Pb). The solder material 7s is, for example, only tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), or the like. Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHS (Restriction of Hazardous Substances) directive. Hereinafter, in the present embodiment, when a solder material or a solder component is described, it indicates lead-free solder unless otherwise specified.

  The conductor pillar 7p is a metal member formed by forming a through hole in an insulating member (a sealing material layer 6 or a resist film not shown) and embedding a metal film in the through hole by, for example, a plating method. is there. In the example shown in FIG. 6, the conductor pillar 7p is made of, for example, copper (Cu) formed in a columnar shape. Note that the plurality of protruding electrodes 7b formed on the surface 3a of the logic chip LC shown in FIG. 6 have the same shape as the conductor pillar 7p and are formed of the same metal material. Therefore, the plurality of protruding electrodes 7b formed on the surface 3a of the logic chip LC can also be called conductor pillars.

  Further, like the logic chip LC and the memory chips MC1, MC2, and MC3 shown in FIG. 6, the semiconductor chip 3 including the through electrode 3tsv has a small thickness, that is, a separation distance between the front surface 3a and the back surface 3b (in other words, Preferably). If the thickness of the semiconductor chip 3 is reduced, the transmission distance of the through electrode 3tsv is shortened, which is preferable in that the impedance component can be reduced. Further, when an opening (including a through hole and a hole that does not penetrate) is formed in the thickness direction of the semiconductor substrate, the processing accuracy decreases as the depth of the hole increases. In other words, if the thickness of the semiconductor chip 3 is reduced, the processing accuracy of the opening for forming the through electrode 3tsv can be improved. For this reason, since the diameters of the plurality of through electrodes 3tsv (that is, the length in the direction orthogonal to the thickness direction of the semiconductor chip 3) can be made uniform, the impedance components of the plurality of transmission paths can be easily controlled.

  For this reason, the thickness of the logic chip LC and the memory chips MC1, MC2, and MC3 is thinner than the thickness of the memory chip MC4 mounted on the uppermost layer, for example, thinner than 100 μm. In the example shown in FIG. 6, the thickness of the logic chip LC is, for example, about 50 μm, and the thicknesses of the memory chips MC1, MC2, and MC3 are each about 30 to 40 μm.

  As described above, when the semiconductor chip 3 is thinned, there is a concern that the semiconductor chip 3 may be damaged when the semiconductor chip 3 is exposed. Therefore, in the present embodiment, as shown in FIG. 6, the sealing material layer 6 or the adhesive material NCL is interposed between the stacked semiconductor chips 3. Thereby, the connection part which electrically connects semiconductor chips 3 and each semiconductor chip 3 can be protected. Further, in the example shown in FIG. 4, the sealing body 4 is brought into close contact with the plurality of semiconductor chips 3 and sealed. In this case, the sealing body 4 functions as a protective member for the semiconductor chip 3 and can suppress damage to the semiconductor chip 3. That is, according to the present embodiment, the reliability (durability) of the semiconductor device 1 can be improved by sealing the plurality of semiconductor chips 3 with resin.

<Method for Manufacturing Semiconductor Device>
Next, the manufacturing process of the semiconductor device 1 described with reference to FIGS. 1 to 10 will be described. FIG. 11 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device described with reference to FIGS. FIG. 12 is a perspective view of the chip laminate prepared in the chip laminate preparation step shown in FIG.

  In the present embodiment, in the chip laminated body preparation step shown in FIG. 11, for example, as shown in FIG. 12, a chip laminated body in which a plurality of memory chips MC1, MC2, MC3, MC4 are laminated (laminated body, memory chip laminated). MCS) is also prepared. In this section, a manufacturing method of the chip stack MCS shown in FIG. 12 will be described before the outline of the manufacturing process is described along the process flow shown in FIG.

<Details of chip stack preparation process>
FIG. 13 is an explanatory diagram showing a detailed process flow of the chip stack preparation process shown in FIG. 11. As shown in FIG. 12, in the chip stacked body MCS, a plurality of semiconductor chips 3 are stacked via a sealing material layer 6. In addition, as described with reference to FIG. 6, each of the plurality of semiconductor chips 3 is electrically connected to each other via the conductor pillar 7p and the through electrode 3tsv. In addition, a plurality of protruding electrodes 7b serving as external terminals of the chip stack MCS are formed on the mounting surface of the chip stack MCS. In the example shown in FIG. 4, the back surface 3b of the memory chip MC1 is a mounting surface that is disposed opposite to the back surface 3b of the logic chip LC. Therefore, as shown in FIG. 12, a plurality of protruding electrodes 7b are formed on the back surface 3b of the memory chip MC1. Is formed.

  As described above, the chip stacked body MCS in which the plurality of semiconductor chips 3 are electrically connected to each other and has the plurality of protruding electrodes 7b serving as external terminals can also be defined as a semiconductor device.

  The chip stack MCS shown in FIG. 12 can also be formed by sequentially stacking the memory chips MC1, MC2, MC3, MC4 via the sealing material layer 6 on the logic chip LC shown in FIG. However, from the viewpoint of simplifying the assembly process shown in FIG. 11 and improving the manufacturing efficiency as a whole, it is preferable to assemble the chip stack MCS first and mount it in the chip stack mounting process shown in FIG. . When forming the chip stack MCS in which the memory chips MC1, MC2, MC3, and MC4 are stacked, for example, the chip stack preparation process shown in FIG. 11 can be performed independently at a place different from other processes. it can. For example, the chip stack MCS can be assembled independently at an establishment different from the establishment where the assembly steps shown in FIG. 11 are performed.

  In particular, as in the present embodiment, the planar sizes of the memory chips MC1, MC2, MC3, and MC4, that is, the planar dimensions of the front surface 3a shown in FIG. 9 and the planar dimensions of the back surface 3b shown in FIG. In some cases, as will be described below, a manufacturing method in which the semiconductor wafer is stacked in the state of a semiconductor wafer and then cut is more efficient. Therefore, in the present embodiment, after stacking semiconductor wafers on which a plurality of chip formation regions corresponding to the memory chips MC1, MC2, MC3, and MC4 are formed, the wafer stack is cut to obtain a plurality of chip stacks. A manufacturing method for obtaining a body will be described.

  First, a study example examined by the inventors of the present application will be described with respect to a manufacturing method for obtaining a plurality of laminated bodies by cutting a wafer laminated body after laminating semiconductor wafers. FIG. 14 is an explanatory diagram showing a process flow, which is an example for studying FIG. FIG. 15 is a cross-sectional view schematically showing a state in which the wafer stack is separated into pieces in the singulation process shown in FIG. The process flow shown in FIG. 13 and the process flow shown in FIG. 14 differ in the presence or absence of the first, second, third, and fourth groove forming steps, but are the same in other respects. In FIG. 15, in order to make it easy to understand the correspondence with the memory chips MC1, MC2, MC3, and MC4 shown in FIG. 6, the semiconductor wafers WH4, WH3, WH2, and WH1 are stacked in order from the side closer to the dicing tape 40. The structure is shown.

  That is, a plurality of semiconductor elements corresponding to the memory chip MC4 shown in FIG. 6 are formed in each of the plurality of chip formation regions 50a included in the semiconductor wafer WH4. Similarly, a plurality of semiconductor elements corresponding to the memory chips MC3, MC2, and MC1 shown in FIG. 6 are formed in each of the plurality of chip formation regions 50a included in the semiconductor wafers WH3, WH2, and WH1. In the following, repeated description of the correspondence between the memory chips MC1, MC2, MC3, and MC4 shown in FIG. 6 and the semiconductor wafers WH1, WH2, WH3, and WH4 is omitted, but the above correspondence is also applied to other drawings. Will be described.

  In the embodiment shown in FIGS. 14 and 15, each of the semiconductor wafers WH4, WH3, WH2, and WH1 is laminated via the sealing material layer 6 to form a wafer laminated body WHS. As shown in FIG. 15, each of the semiconductor wafers WH4, WH3, WH2, and WH1 includes a plurality of chip formation regions (also referred to as chip formation portions) 50a and dicing regions disposed between adjacent chip formation regions 50a. 50b (also referred to as a cutting region, a cutting region, or a cutting portion) is provided. Then, after the wafer stack WHS is formed, the wafer stack WHS is divided into a plurality of chip stacks MCS by running the dicing blade 41 along the dicing area 50b. That is, in this manufacturing method, after stacking a plurality of semiconductor wafers 50, the wafer stack WHS is cut to obtain a plurality of chip stacks MCS.

  As described above, in the case of a manufacturing method in which a plurality of semiconductor wafers 50 are stacked and then the wafer stack WHS is cut, a step of aligning the plurality of chip formation regions 50a, a sealing material layer 6 and a semiconductor The process of bonding and fixing the wafer 50 can be performed in batches for each wafer. For this reason, manufacturing efficiency can be improved compared with the method of laminating | stacking each semiconductor chip 3 sequentially.

  Further, in the example shown in FIG. 14, after the second, third, and fourth wafer mounting steps for mounting the semiconductor wafer, a step of grinding the back surface 3b of the semiconductor wafer 50 shown in FIG. 15 is performed. That is, since the thickness of the semiconductor wafer 50 is reduced after the semiconductor wafer 50 is mounted, the process of mounting the semiconductor wafer 50 is performed with the semiconductor wafer 50 being thick. For example, in the case of a standard semiconductor wafer having a diameter of 300 mm, the second, third, and fourth wafer mounting steps shown in FIG. 14 can be performed with a thickness of about 775 μm. For this reason, it is possible to prevent or suppress damage to the semiconductor wafer 50 during the mounting process.

  However, according to the study by the inventors of the present application, it has been found that in the manufacturing method shown in FIGS. 14 and 15, a part of the semiconductor chip 3 may be damaged in the singulation process. As shown in FIG. 15, in the case of a system in which each of the plurality of semiconductor wafers 50 is stacked via the sealing material layer 6, the sealing material layer 6 also exists in the dicing region 50b. Although details will be described later, the sealing material layer 6 is required to have a function as an adhesive for bonding and fixing the semiconductor wafers 50 to be stacked, and has different physical properties from the semiconductor material (for example, silicon) constituting the semiconductor wafer 50. It is comprised with the insulating material which has these. That is, as shown in FIG. 15, when the cutting process is performed by the dicing blade 41, when the semiconductor wafer 50 is cut, and when the sealing material layer 6 is cut, the rotational speed of the dicing blade 41 and the grinding The optimum values of cutting conditions such as the average grain size and pressing pressure are greatly different.

  For this reason, when the semiconductor wafer 50 and the sealing material layer 6 are collectively cut by the dicing blade 41 as shown in FIG. 15, an excessive load is applied in the vicinity of the dicing region 50b of the semiconductor wafer 50. There is. For example, when the semiconductor wafer 50 is cut under conditions that allow the sealing material layer 6 to be cut, a chipping phenomenon may occur in which the peripheral portion of the chip formation region 50a of the semiconductor wafer 50 is cracked or chipped.

  Moreover, when the cutting waste of the sealing material layer 6 adheres to the cutting surface of the dicing blade 41 and becomes clogged, the occurrence frequency of the chipping phenomenon increases. Moreover, the frequency of occurrence of the chipping phenomenon increases as the thickness of the semiconductor wafer 50 decreases. Further, as the cutting width becomes narrower, stress is more likely to be concentrated locally, so that the frequency of occurrence of the chipping phenomenon increases. When a chipping phenomenon occurs in the uppermost semiconductor wafer 50, the chipping location can be detected visually or by an optical inspection method. However, when the chipping phenomenon occurs in the lower semiconductor wafer 50, it is difficult to detect the chipping location. Further, the above chipping phenomenon causes a decrease in reliability of the chip stack MCS or the semiconductor device 1 (see FIG. 4) on which the chip stack MCS is mounted.

  Therefore, the inventor of the present application has found an embodiment described below from the viewpoint of improving the reliability of the chip stack MCS or the semiconductor device 1 (see FIG. 4) on which the chip stack MCS is mounted.

  If the outline | summary of this aspect demonstrated below is demonstrated previously, the several semiconductor wafer 50 will be laminated | stacked in the state which removed previously the sealing material layer 6 arrange | positioned in the area | region which overlaps with the dicing area | region 50b. A plurality of chip stacks MCS are obtained by running the dicing blade 41 along the dicing region 50b from which the sealing material layer 6 has been removed. This eliminates the need to cut the sealing material layer 6 with the dicing blade 41 in the singulation process shown in FIG.

  Further, if it is not necessary to cut the sealing material layer 6 with the dicing blade 41, the cutting conditions can be optimized for the semiconductor wafer 50. For this reason, generation | occurrence | production of the above-mentioned chipping phenomenon can be prevented or suppressed. Further, if the occurrence of a chipping phenomenon is prevented or suppressed in the singulation process shown in FIG. 13, the reliability of the chip stack MCS or the semiconductor device 1 (see FIG. 4) on which the chip stack MCS is mounted is improved. Can be made.

  Hereinafter, the details of the process flow shown in FIG. 13 will be described in order. Each of the first, second, third, and fourth wafer preparation steps shown in FIG. 13 has a common process flow, and will be described collectively as a wafer preparation step below.

<Wafer preparation process>
First, in the first, second, third, and fourth wafer preparation steps shown in FIG. 13, semiconductor wafers WH1, WH2, WH3, and WH4 are respectively prepared as shown in FIGS. FIG. 16 is a plan view of a semiconductor wafer prepared in each of the first, second, third and fourth wafer preparation steps shown in FIG. FIG. 17 is an enlarged cross-sectional view along the line AA in FIG. 18 shows detailed steps included in the first, second, third, and fourth wafer preparation steps shown in FIG. 13, and the first, second, third, and fourth groove forming steps. It is explanatory drawing.

  Since the semiconductor wafers WH1, WH2, WH3, and WH4 (see FIG. 17) manufactured in the wafer preparation process of FIG. 18 have the same structure in plan view, FIG. 16 representatively shows one semiconductor wafer 50. ing. On the other hand, the semiconductor wafers WH1, WH2, WH3 and the semiconductor wafer WH4 have different cross-sectional structures. For this reason, in FIG. 17, the semiconductor wafers WH1, WH2, and WH3 having the same cross-sectional structure are shown in the upper stage, and the semiconductor wafer WH4 having a different cross-sectional structure is shown in the lower stage. In the following description, when a configuration common to the semiconductor wafers WH1, WH2, WH3, and WH4 is described, the description of the semiconductor wafer 50 is used as a general term for the semiconductor wafers WH1, WH2, WH3, and WH4. On the other hand, configurations that are present in the semiconductor wafers WH1, WH2, and WH3 but not in the semiconductor wafer WH4 will be described as semiconductor wafers WH1, WH2, and WH3. A configuration that is present in the semiconductor wafer WH4 but not in the semiconductor wafers WH1, WH2, and WH3 will be described as the semiconductor wafer WH4.

  In FIGS. 16 and 17, the number of chip formation regions 50a is reduced (for example, 16 in the example shown in FIG. 16) for ease of viewing. However, the number of chip formation regions 50a is not limited to the aspect shown in FIG. 16, and can be increased from 16. Further, in FIG. 16, in order to show the boundary between the chip formation region 50a and the dicing region 50b, the outlines of the chip formation region 50a and the dicing region 50b are indicated by two-dot chain lines. However, since the chip formation region 50a and the dicing region 50b are regions that are divided in the singulation process shown in FIG. 13 and regions that are to be cut, it is not necessary to have a boundary line that is actually visible.

  As shown in FIG. 17, the semiconductor wafer 50 prepared in the wafer preparation process has a front surface 3a and a back surface 3b2. In addition, the semiconductor wafer 50 is provided with a plurality of chip formation regions 50a that define the surface 3a. Further, as shown in FIGS. 16 and 17, the semiconductor wafer 50 is subjected to cutting in the singulation process shown in FIG. 13 between the chip formation regions 50a adjacent to each other among the plurality of chip formation regions 50a. A dicing area (also referred to as a cutting area or a cutting area) 50b, which is a planned area, is provided.

  Each of the plurality of chip formation regions 50a corresponds to the memory chips MC1, MC2, MC3, and MC4 shown in FIG. When the semiconductor wafer 50 having the plurality of chip formation regions 50a is used as described above, when the circuit elements are formed on the element formation surface of the semiconductor substrate (not shown), the plurality of chip formation regions 50a are collectively processed. Can be applied. For this reason, the manufacturing efficiency of the semiconductor chip can be improved.

  As shown in FIG. 17, a plurality of surface electrodes 3 ap are formed on the surface 3 a in each of the plurality of chip formation regions 50 a of the semiconductor wafer 50. A plurality of conductor columns 7p are connected to the plurality of surface electrodes 3ap, respectively. The plurality of surface electrodes 3ap are the same members as the plurality of surface electrodes 3ap shown in FIG. Further, the plurality of conductor columns 7p shown in FIG. 17 are the same members as the plurality of conductor columns 7p that electrically connect the semiconductor chips 3 shown in FIG.

  As shown in FIG. 17, a plurality of internal electrodes 3iv are formed between the front surface 3a and the back surface 3b2 on each of the semiconductor wafers WH1, WH2, and WH3. The plurality of internal electrodes 3iv are metal members corresponding to the plurality of through electrodes 3tsv shown in FIG. 6, and are formed to extend in the thickness direction of the semiconductor wafer. The plurality of internal electrodes 3iv are connected to the surface electrode 3ap on the surface 3a. In other words, the plurality of internal electrodes 3iv are electrically connected to the plurality of conductor pillars 7p via the plurality of surface electrodes 3ap.

  On the other hand, as shown in the lower part of FIG. 17, the plurality of internal electrodes 3iv are not formed on the semiconductor wafer WH4. As shown in FIG. 6, the semiconductor wafer WH4 is a semiconductor wafer corresponding to the memory chip MC4 mounted on the uppermost stage when mounted on the wiring board 2, so that it is not necessary to form the through electrode 3tsv. For this reason, the plurality of internal electrodes 3iv are not formed on the semiconductor wafer WH4.

  A sealing material layer 6 is formed on the surface 3 a of the semiconductor wafer 50. As shown in FIG. 12, the sealing material layer 6 is a resin material that functions as an adhesive that bonds and fixes each of the plurality of semiconductor chips 3. Further, as shown in FIG. 6, the sealing material layer 6 includes a connection portion (in FIG. 6, a conductor column that connects the surface electrode 3ap and the through electrode 3tsv) that electrically connects the semiconductor chips 3 adjacent in the thickness direction. 7p).

  In the present embodiment, as shown in FIG. 18, after forming the sealing material layer 6 (see FIG. 17), through holes are formed in the sealing material layer 6, and a metal is embedded in the through holes. 7p (see FIG. 6) is formed. Therefore, the sealing material layer 6 is required to have physical properties necessary for forming the conductor pillar 7p.

  For example, in order to form a plurality of through holes by applying a photolithography technique, the sealing material layer 6 (see FIG. 17) needs to be a photosensitive resin. Further, for example, when a polishing technique such as CMP (Chemical Mechanical Polishing) is applied when removing excess metal after embedding a metal in the through hole, the encapsulant layer 6 is applied. Is required to be strong enough not to be crushed by pressing the polishing member. For this reason, it is preferable to form the sealing material layer 6 using the resin material which hardens | cures by providing energy, such as a heat | fever and light, for example. Further, for example, as shown in FIG. 13, in this embodiment, the semiconductor wafers 50 (see FIG. 17) on which the sealing material layer 6 (see FIG. 17) is formed are sequentially stacked and bonded and fixed. For this reason, the encapsulant layer 6 is made of a resin material that improves the adhesiveness of the exposed surface by applying energy such as heat or light to the exposed surface of the encapsulated layer 6 once cured. Is preferably formed. Further, as shown in FIG. 6, in order to seal a plurality of connection portions that electrically connect the semiconductor chip 3, it is necessary to be an insulating material.

  In the present embodiment, for example, PBO (polybenzoxazole) is used as the material as described above to form the sealing material layer 6. However, various modified examples can be applied as long as the resin material has the above characteristics. For example, a photosensitive polymer such as polyimide or BCB (benzocyclobutene) can be applied.

  Moreover, PBO which comprises the sealing material layer 6 is a liquid at normal temperature (for example, 25 degreeC). For this reason, in the step of forming the sealing material layer 6 on the semiconductor wafer 50, liquid PBO is applied onto the upper surface 3a of the semiconductor wafer 50 by using a coating technique such as spin coating, and then cured. . Accordingly, as shown in FIG. 17, the sealing material layer 6 is not selectively disposed on the chip formation region 50a, but is uniformly formed on the surface 3a including the chip formation region 50a and the dicing region 50b. Has been.

  Further, as shown in FIG. 17, each of the plurality of conductor columns 7p is covered with the sealing material layer 6, and each of the plurality of conductor columns 7p (the tip portion in FIG. 17) is the sealing material. Exposed from layer 6. Thus, by exposing a part of the conductor pillar 7p from the sealing material layer 6, it becomes possible to electrically connect a plurality of semiconductor wafers 50 via the conductor pillar 7p.

  Next, a method of manufacturing the semiconductor wafer 50 shown in FIGS. 16 and 17 will be described along the process flow shown in FIG. When the semiconductor wafer WH4 shown in FIG. 17 is manufactured, the hole forming step and the conductor column forming step shown in FIG. 18 can be omitted, but the other steps are common. Therefore, a method for manufacturing the semiconductor wafers WH1, WH2, and WH3 shown in FIG. 17 will be described below. FIG. 19 is an enlarged sectional view showing a semiconductor substrate prepared in the semiconductor substrate preparation step shown in FIG. FIG. 20 is an enlarged cross-sectional view showing a state in which a plurality of holes are formed in the semiconductor substrate shown in FIG. FIG. 21 is an enlarged cross-sectional view showing a state in which a metal material is embedded in the plurality of holes shown in FIG. FIG. 22 is an enlarged cross-sectional view showing a state in which a chip wiring layer is formed on the main surface of the semiconductor substrate shown in FIG. FIG. 23 is an enlarged cross-sectional view showing a state where a sealing material layer is laminated on the surface of the semiconductor wafer shown in FIG. FIG. 24 is an enlarged cross-sectional view showing a state where a plurality of through holes are formed in the sealing material layer shown in FIG. FIG. 25 is an enlarged cross-sectional view showing a state in which a conductive pillar is formed by embedding a metal material in the plurality of through holes shown in FIG.

  First, as a semiconductor substrate preparation step shown in FIG. 18, a semiconductor substrate SS shown in FIG. 19 is prepared. The semiconductor substrate SS is made of, for example, silicon (Si) and has a circular shape in plan view. The planar shape of the semiconductor substrate SS is the same as the planar shape of the semiconductor wafer 50 shown in FIG.

  The semiconductor substrate SS has a main surface (also referred to as a front surface or an upper surface) SSf that is a semiconductor element formation surface and a back surface (also referred to as a main surface or a lower surface) SSb opposite to the main surface SSf. The main surface SSf is a surface on which a semiconductor element is formed. Strictly speaking, the main surface SSf is disposed between the front surface 3a and the back surface 3b2 shown in FIG. 17 and at a position about 1 μm to several μm from the front surface 3a. On the other hand, the back surface SSb is the same surface as the back surface 3b2 shown in FIG. The thickness of the semiconductor substrate SS is thicker than the memory chips MC1, MC2, MC3, and MC4 shown in FIG. 4, and is about 700 to 800 μm (strictly, for example, 775 μm).

  Next, as a hole forming step shown in FIG. 18, a hole (hole, opening) 3tsh for forming the internal electrode 3iv (see FIG. 17) is formed as shown in FIG. In the example shown in FIG. 20, the mask 25 is disposed on the main surface SSf of the semiconductor substrate SS, and the hole 3tsh is formed by performing an etching process. The depth of the hole 3tsh may be larger than the thickness of the semiconductor wafer after the second, third and fourth wafer back surface grinding steps shown in FIG. That is, the thickness may be larger than the thickness of the memory chips MC1, MC2, and MC3 shown in FIG. For example, if the thickness of the hole 3tsh formed in this step is about 30 μm to 50 μm after grinding, a thickness of several μm (one digit) is added to the thickness of this wafer. Depth (for example, about 31 μm to 51 μm).

  However, from the viewpoint of improving the electrical connection reliability at the connection portion between the through electrode 3tsv and the conductor pillar 7p shown in FIG. 6, it is preferable to increase the exposed area of the through electrode 3tsv to some extent. Therefore, it is preferable to determine the depth of the hole 3tsh considering that the bottom surface of the hole 3tsh is curved by the etching process. For example, if the thickness of the semiconductor wafer after grinding is about 30 μm to 50 μm, the depth of the hole 3tsh formed in this step is a thickness of several tens μm (two digits) added to the thickness of the wafer. The depth is preferably about 40 μm to 60 μm.

  Next, as an internal electrode forming step, a plurality of internal electrodes 3iv are formed by embedding a metal material in the plurality of holes 3tsh as shown in FIG. An example of the metal material embedded in this step is copper (Cu). Moreover, the method of embedding a metal material can illustrate a plating method, for example.

  Although not shown, in the wafer preparation step, a step of forming a plurality of semiconductor elements configured by combining a plurality of semiconductor regions having different impurity concentrations and an insulating layer on the main surface SSf of the semiconductor substrate SS. (That is, a semiconductor element forming step). This semiconductor element forming step can be performed, for example, between the internal electrode forming step shown in FIG. 18 and the wiring layer forming step. Alternatively, a semiconductor element can be formed in advance on the main surface SSf of the semiconductor substrate SS prepared in the semiconductor substrate preparation step.

  Next, as a wiring layer forming step, as shown in FIG. 22, a wiring layer (specifically, a wiring layer for a semiconductor chip) having conductor patterns insulated from each other by an insulating layer on the main surface SSf of the semiconductor substrate SS. 3d is formed. The upper surface of the wiring layer 3d constitutes the surface 3a of the semiconductor wafer 50 (semiconductor wafers WH1, WH2, and WH3 in the example of FIG. 22). The semiconductor wafer WH4 shown in FIG. 17 is the same as the semiconductor wafers WH1, WH2, and WH3 except that the plurality of internal electrodes 3iv shown in FIG. 22 are not formed. In this step, the surface electrode 3ap is formed on the uppermost layer of the wiring layer 3d, and the plurality of internal electrodes 3iv and the plurality of surface electrodes 3ap are electrically connected to each other. In this step, the plurality of semiconductor elements formed on the main surface SSf of the semiconductor substrate SS and the plurality of surface electrodes 3ap are electrically connected.

  Next, in the sealing material layer forming step, the sealing material layer 6 is formed on the surface 3a of the semiconductor wafer 50 as shown in FIG. As described above, the sealing material layer 6 is made of a resin that is liquid at room temperature, such as PBO. Therefore, in this step, for example, a spin coating method can be applied in which a liquid resin is dropped on the surface 3a and the semiconductor wafer 50 is rotated to form the sealing material layer 6 on the surface 3a. . The encapsulant layer 6 contains, for example, a thermosetting resin component, and the encapsulant layer 6 is heated by heating the semiconductor wafer 50 whose surface 3 a is covered with the encapsulant layer 6. It can be cured.

  Next, as a through-hole forming step, as shown in FIG. 24, a plurality of through-holes 6th penetrating the sealing body layer 6 in the thickness direction are formed. The plurality of through holes 6th are formed at positions that overlap the plurality of surface electrodes 3ap in the thickness direction. That is, in this step, a plurality of through holes 6th are formed in the sealing material layer 6 so that the plurality of surface electrodes 3ap formed in the semiconductor wafer 50 are exposed from the sealing material layer 6. As described above, the sealing material layer 6 is made of a photosensitive resin such as PBO, and a plurality of through holes 6th can be formed by a photolithography technique.

  Next, as a conductor column forming step, as shown in FIG. 25, a metal material is embedded in each of the plurality of through holes 6th to form a plurality of conductor columns 7p that are electrically connected to the plurality of surface electrodes 3ap. . In this step, the conductor pillar 7p can be formed by, for example, a plating method. In addition, when a metal material (for example, copper) is embedded in the through hole 6th, the metal material may be formed also on the upper surface 6a of the sealing material layer 6. In this case, each of the plurality of conductor pillars 7p can be electrically separated by polishing the upper surface 6a of the sealing material layer 6 by a polishing technique such as CMP.

  Through the above steps, the semiconductor wafer 50 shown in FIGS. 16 and 17 can be manufactured. In addition, when forming the semiconductor wafer WH4, a hole formation process and an internal electrode formation process are omissible among the above-mentioned processes.

<Groove formation process>
Next, in the first, second, third, and fourth groove forming steps shown in FIG. 13, a groove 50tr is formed along the dicing region 50b on the surface 3a side of the semiconductor wafer 50, as shown in FIG. Then, the sealing material layer 6 on the dicing region 50b is removed. FIG. 26 is a cross-sectional view showing a state where grooves are formed in the semiconductor wafer shown in FIG. FIG. 27 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG.

  As shown in FIG. 26, in the groove forming step, the sealing material layer 6 on the dicing region 50b is selectively removed. In this step, it is sufficient that at least the sealing material layer 6 in the dicing region 50b can be removed. For example, in addition to a method of removing the sealing material layer 6 by cutting, various methods such as a method of removing by laser irradiation are used. Variations can be applied. In the present embodiment, as an example, an embodiment in which the sealing material layer 6 is removed by cutting using a dicing blade 42 as shown in FIG. 27 will be described. When removing the sealing material layer 6 by cutting using the dicing blade 42, it is preferable in that a special manufacturing apparatus for removing the sealing material layer 6 is not required.

  As shown in FIG. 27, in this embodiment, the dicing blade 42 is run to cut the dicing area 50b, and the dicing area 50b is formed so as to cover the surface 3a of the semiconductor wafer 50. The sealing material layer 6 is removed. In the example shown in FIGS. 26 and 27, a part of the dicing area 50b of the semiconductor wafer 50 is also removed by running the dicing blade 42 (see FIG. 27). Thus, by removing a part of the semiconductor wafer 50 together with the sealing material layer 6 in the dicing region 50b, the sealing material layer 6 can be reliably removed.

  A dicing blade 42 shown in FIG. 27 is a cutting jig in which abrasive grains such as diamond are fixed to the outer periphery of a thin plate having a circular or ring-shaped outer shape. In addition, the dicing blade 42 is a rotary blade in which abrasive grains fixed to the outer periphery cut the object to be cut by rotating around the center of a circular or ring-shaped plane. When the dicing blade 42 is caused to travel along the direction in which the dicing region 50b extends (see, for example, FIG. 16), a groove 50tr is formed in the semiconductor wafer 50 along the dicing region 50b. The groove 50 tr has a bottom surface 50 trb positioned between the front surface 3 a and the back surface 3 b 2 of the semiconductor wafer 50 along the thickness direction of the semiconductor wafer 50.

  The width (namely, cutting width) WT1 of the groove 50tr is defined by the width WB1 of the dicing blade 42, and is, for example, about 40 μm to 60 μm in the present embodiment. The depth DT1 of the groove 50tr is defined by cutting conditions such as the pressing pressure of the dicing blade 42, the rotational speed, or the traveling speed along the dicing area 50b. From the viewpoint of removing 6, there is no particular limitation. However, in order to transport the semiconductor wafer 50 after forming the groove 50tr, it is necessary to connect a plurality of chip formation regions 50a. Therefore, the depth DT1 of the groove 50tr is larger than the thickness T1 of the semiconductor wafer 50. Is also small. Further, from the viewpoint of preventing damage to the semiconductor wafer 50 during the transfer of the semiconductor wafer, the depth DT1 of the groove 50tr is preferably less than or equal to half the thickness T1 of the semiconductor wafer 50. In addition, in the singulation process shown in FIG. 13, from the viewpoint of reducing the portion to be cut, the semiconductor wafers WH1, WH2, WH3 (after the first, second, and third wafer back grinding processes shown in FIG. It is preferable that the thickness be larger than the thickness shown in FIG. For example, in the present embodiment, the thicknesses of the semiconductor wafers WH1, WH2, and WH3 are set to about 30 μm to 50 μm in the first, second, and third wafer back surface grinding steps shown in FIG. It is about 80 μm.

  By the way, in the groove forming process of the present embodiment, both the sealing material layer 6 and the semiconductor wafer 50 are collectively cut by the dicing blade 42. For this reason, as described above, a plurality of members having different optimum values of the cutting processing conditions such as the rotational speed, the average particle diameter of the abrasive grains, and the pressing pressure are collectively cut.

  However, in the present embodiment, the semiconductor wafer 50 is not completely cut, but only a part on the surface 3a side of the semiconductor wafer 50 is cut. The thickness T1 of the semiconductor wafer 50 at the time of cutting has a thickness of about 775 μm, for example. Therefore, even if the cutting conditions such as the rotational speed of the dicing blade 42, the average grain size of the abrasive grains, and the pressing pressure are deviated from the optimum values for cutting the semiconductor wafer 50, the above-described chipping phenomenon occurs. hard.

  Further, the dicing blade 42 used in the groove forming process of the present embodiment has a cutting width, that is, a width WT1 shown in FIG. 27, than the dicing blade (details will be described later) used in the singulation process shown in FIG. large. For this reason, since it becomes difficult to concentrate stress locally at the time of cutting, generation | occurrence | production of a chipping phenomenon can be prevented or suppressed.

  As described above, in this step, the trench 50tr is formed along the dicing region 50b for each of the semiconductor wafers WH1, WH2, WH3, and WH4. Thereby, the sealing material layer 6 on the dicing area 50b is removed. In other words, each of the semiconductor wafers WH1, WH2, WH3, and WH4 after the completion of this process is covered with the sealing material layer 6 on the chip formation region 50a and the sealing material layer 6 on the dicing region 50b. Not placed.

<Second wafer mounting process>
Next, in the second wafer mounting step shown in FIG. 13, as shown in FIG. 28, the semiconductor wafer WH3, with the surface 3a of the semiconductor wafer WH4 and the surface 3a of the semiconductor wafer WH3 facing each other, WH4 is bonded and fixed through the sealing material layer 6. FIG. 28 is a cross-sectional view showing a state in which semiconductor wafers are stacked in the second wafer mounting step shown in FIG. FIG. 29 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG. 28 in an enlarged manner. FIG. 30 is an enlarged cross-sectional view showing the periphery of a region where a plurality of surface electrodes are formed in the chip formation region shown in FIG. In the example shown in FIG. 13, the semiconductor wafer WH4 shown in FIGS. 28 to 30 corresponds to the first wafer shown in FIG. 13, and the semiconductor wafer WH3 shown in FIGS. 28 to 30 corresponds to the second wafer shown in FIG. Equivalent to.

  As shown in FIG. 28, in the second wafer mounting step, the semiconductor wafer WH3 is mounted on the surface 3a of the semiconductor wafer WH4. Specifically, for example, the semiconductor wafer WH3 shown in FIG. 26 is turned upside down, and the semiconductor wafers WH3 and WH4 are sealed with the surface 3a of the semiconductor wafer WH4 and the surface 3a of the semiconductor wafer WH3 facing each other. The material layer 6 is bonded together. In other words, the surface 3a side of the semiconductor wafer WH4 and the surface 3a side of the semiconductor wafer WH3 are bonded together with the sealing material layer 6 interposed therebetween.

  In this step, each of the plurality of chip formation regions 50a of the semiconductor wafer WH4 and each of the plurality of chip formation regions 50a of the semiconductor wafer WH3 are electrically connected. Specifically, the plurality of conductor columns 7p formed in each of the plurality of chip formation regions 50a of the semiconductor wafer WH4 and the plurality of conductor columns 7p formed in each of the plurality of chip formation regions 50a of the semiconductor wafer WH3 are opposed to each other. Contact and make electrical connection. Therefore, in this step, the plurality of chip formation regions 50a of the semiconductor wafer WH4 and the plurality of chip formation regions 50a of the semiconductor wafer WH3 overlap each other, and the surface 3a of the semiconductor wafer WH4 is the surface 3a of the semiconductor wafer WH3. It arranges so that it may face.

  The resin constituting the encapsulant layer 6 of the present embodiment has the property that when exposed to heat even after being cured, the exposed surface becomes sticky. Further, in the step of forming the encapsulant layer 6 as described above, the adhesiveness can be further improved in this step if it is kept in a so-called temporary curing state in which all of the thermosetting resin is not cured. . In this step, as shown in FIG. 29, the upper surface 6a of the sealing material layer 6 formed on the surface 3a of the semiconductor wafer WH4 and the sealing material layer 6 formed on the surface 3a of the semiconductor wafer WH3. The upper surface 6a is brought into close contact with heating, and a load is applied to the close contact surface. Thereby, the contact | adherence surface of the sealing material layer 6, ie, the upper surface 6a of the sealing material layer 6, is joined.

  In addition, as shown in FIG. 30, the plurality of conductor pillars 7p formed on the surface 3a of the semiconductor wafer WH4 and the plurality of conductor pillars 7p formed on the surface 3a of the semiconductor wafer WH3 are in opposing contact with each other. In the state, the surrounding sealing material layer 6 is joined. For this reason, the plurality of conductive pillars 7p facing each other are electrically connected.

  As described above, in this step, the sealing material layer 6 is bonded in a state where the plurality of conductor columns 7p are opposed to each other. In this state, by re-curing the sealing material layer 6, the semiconductor wafer WH3 can be bonded and fixed on the semiconductor wafer WH4. In FIGS. 29 and 30, the position of the upper surface 6 a is clearly shown with a two-dot chain line in order to clearly show the position of the bonding interface of the sealing material layer 6. It is possible to integrate the interface to such an extent that it becomes difficult to visually recognize. From the viewpoint of improving the bonding strength of the sealing material layer 6, it is preferable that the bonding interface of the sealing material layer 6 be integrated to such an extent that it becomes difficult to visually recognize.

<Second wafer back grinding process>
Next, in the second wafer back surface grinding step shown in FIG. 13, as shown in FIG. 31, the back surface 3b2 of the semiconductor wafer WH3 is ground to expose each of the plurality of internal electrodes 3iv. FIG. 31 is a cross-sectional view showing a state where the back surface of the upper semiconductor wafer is ground in the second wafer back surface grinding step shown in FIG. 13. FIG. 32 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG. FIG. 33 is an enlarged cross-sectional view showing the periphery of a region where a plurality of surface electrodes are formed in the chip formation region shown in FIG.

  31 to 33, the outline of the semiconductor wafer WH3 before grinding is indicated by a two-dot chain line in order to clearly indicate the position of the back surface 3b2 before performing the grinding process. 32 and 33 show a state after the semiconductor substrate SS is ground and then an insulating film is formed on the exposed surface and then ground again.

  As shown in FIG. 31, in this step, the back surface 3b2 side of the semiconductor wafer WH3 is ground to reduce the thickness of the semiconductor wafer WH3. For example, in the present embodiment, since the thickness of the memory chip MC3 shown in FIG. 6 is about 30 μm to 50 μm, the grinding process is performed until the height from the surface 3a of the semiconductor wafer WH3 becomes about 30 μm to 50 μm. Apply. The grinding method can be performed by, for example, a CMP method.

  As shown in detail in FIG. 33, in this step, first, the semiconductor substrate SS constituting the semiconductor wafer WH3 is ground by the CMP method, and a part (specifically, the tip part) of the plurality of internal electrodes 3iv is exposed. At this time, the tip portion of the internal electrode 3iv protrudes from the semiconductor substrate SS according to the etching rate selection ratio with respect to the semiconductor substrate SS and the internal electrode 3iv.

  As shown in FIG. 32, in the present embodiment, the depth of the groove 50tr formed in the semiconductor wafer WH3 is formed to be larger than the thickness of the semiconductor wafer WH3 after the grinding process. For this reason, in this process, the semiconductor wafer WH3 is divided for each chip formation region. In other words, in this step, as shown in FIG. 32, the grinding process is performed until the bottom surface 50trb of the groove 50tr formed in the dicing region 50b of the semiconductor wafer WH3 is removed. Furthermore, in other words, in the present embodiment, the semiconductor wafer WH3 is divided into a plurality of memory chips MC3 by performing a grinding process from the back surface 3b2. For this reason, in the individualization process shown in FIG. 13, it is not necessary to cut the semiconductor wafer WH3. That is, it is possible to reduce the portion to be cut in the singulation process.

Next, an insulating film 3ps is formed so as to cover the back surface of the semiconductor substrate SS and the plurality of internal electrodes 3iv in a state where a part of the internal electrode 3iv protrudes from the semiconductor substrate SS. The insulating film 3ps is made of, for example, silicon oxide (SiO ₂ ), and can be deposited by, for example, a CVD (Chemical Vapor Deposition) method. By covering the back surface side of the semiconductor substrate SS with an insulating film, the plurality of internal electrodes 3iv can be reliably insulated from each other, so that electrical characteristics can be improved. At this time, as shown in FIG. 32, the insulating film 3ps is also formed inside the trench 50tr. However, since the insulating film 3ps is thin, for example, 1 μm or less, the inside of the trench 50tr is not filled with the insulating film 3ps.

  Next, as shown in FIG. 33, a grinding process is performed by a CMP method so that the tip surface of the internal electrode 3iv is exposed. Since the insulating film 3ps is very thin as described above, the processing is completed in a short time compared to the time for grinding the semiconductor substrate SS. For this reason, as shown in FIG. 33, the back surface of the insulating film 3ps after the grinding treatment and the front end surfaces of the plurality of internal electrodes 3iv are arranged at substantially the same positions as the back surface 3b.

  Through the above steps, the plurality of internal electrodes 3iv are exposed on the back surface 3b of the semiconductor wafer WH3. Moreover, as described above, the plurality of internal electrodes 3iv are electrically connected to the plurality of surface electrodes 3ap. That is, when this step is completed, the plurality of internal electrodes 3iv become the plurality of through-electrodes 3tsv formed so as to penetrate from one to the other of the front surface 3a and the back surface 3b of the semiconductor wafer WH3.

<Third wafer mounting process>
Next, in the third wafer mounting process shown in FIG. 13, as shown in FIG. 34, the semiconductor wafer WH2, the semiconductor wafer WH2, and the back surface 3b of the semiconductor wafer WH3 are arranged so as to face each other. WH3 is bonded and fixed through the sealing material layer 6. FIG. 34 is a cross-sectional view showing a state in which semiconductor wafers are stacked in the third wafer mounting step shown in FIG. FIG. 35 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG. 34 in an enlarged manner. FIG. 36 is an enlarged cross-sectional view showing the periphery of a region where a plurality of surface electrodes are formed in the chip formation region shown in FIG. In the example shown in FIG. 13, the semiconductor wafer WH2 shown in FIGS. 34 to 36 corresponds to the third wafer shown in FIG.

  As shown in FIG. 34, in the third wafer mounting step, the semiconductor wafer WH2 is mounted on the back surface 3b of the semiconductor wafer WH3. Specifically, for example, the semiconductor wafer WH2 shown in FIG. 26 is turned upside down, and the sealing material layer of the semiconductor wafer WH2 is disposed so that the back surface 3b of the semiconductor wafer WH3 and the front surface 3a of the semiconductor wafer WH2 face each other. 6 and the back surface 3b of WH3 are bonded together. In other words, the back surface 3b side of the semiconductor wafer WH3 and the front surface 3a side of the semiconductor wafer WH2 are bonded together via the sealing material layer 6.

  In this step, each of the plurality of chip formation regions 50a of the semiconductor wafer WH3 and each of the plurality of chip formation regions 50a of the semiconductor wafer WH2 are electrically connected. Specifically, the plurality of conductor pillars 7p formed in each of the plurality of chip formation regions 50a of the semiconductor wafer WH2 and the plurality of internal electrodes 3iv exposed on the back surfaces 3b of the plurality of chip formation regions 50a of the semiconductor wafer WH3 (that is, The through electrodes 3tsv) are brought into contact with each other and electrically connected. Therefore, in this step, the plurality of chip formation regions 50a of the semiconductor wafer WH3 and the plurality of chip formation regions 50a of the semiconductor wafer WH2 overlap each other, and the front surface 3a of the semiconductor wafer WH2 is the back surface 3b of the semiconductor wafer WH3. It arranges so that it may face.

  In the above-described second wafer mounting step, the upper surfaces 6a of the sealing material layers 6 are bonded to each other. However, in this step, the upper surface 6a of the sealing material layer 6 and the back surface 3b of the semiconductor wafer WH3 are bonded and fixed. However, as described above, the resin constituting the encapsulant layer 6 of the present embodiment has the property that when exposed even after being cured, the exposed surface becomes sticky. Further, in the step of forming the encapsulant layer 6 as described above, the adhesiveness can be further improved in this step if it is kept in a so-called temporary curing state in which all of the thermosetting resin is not cured. .

  Therefore, in this step, as shown in FIG. 35, the upper surface 6a of the sealing material layer 6 formed on the front surface 3a of the semiconductor wafer WH2 and the rear surface 3b of the semiconductor wafer WH3 are brought into close contact with each other while being heated. A load is applied to. Thereby, the bonding interface between the sealing material layer 6 and the semiconductor wafer WH3, that is, the upper surface 6a of the sealing material layer 6 and the back surface 3b of the semiconductor wafer WH3 are bonded.

  As shown in FIG. 36, on the back surface 3b of the semiconductor wafer WH3, the exposed plurality of internal electrodes 3iv and the plurality of conductor columns 7p formed on the front surface 3a of the semiconductor wafer WH2 are in a state of facing each other. The surrounding sealing material layer 6 is adhered. For this reason, the plurality of internal electrodes 3iv and the plurality of conductor columns 7p that face each other are electrically connected to each other.

  As described above, in this step, the sealing material layer 6 is bonded in a state where the plurality of internal electrodes 3iv and the plurality of conductor pillars 7p are opposed to each other. In this state, by re-curing the sealing material layer 6, the semiconductor wafer WH3 can be bonded and fixed on the semiconductor wafer WH4.

<Third wafer back grinding process>
Next, in the third wafer back surface grinding step shown in FIG. 13, as shown in FIG. 37, the back surface 3b2 of the semiconductor wafer WH2 is ground to expose each of the plurality of internal electrodes 3iv. FIG. 37 is a cross-sectional view showing a state where the back surface of the upper semiconductor wafer is ground in the third wafer back surface grinding step shown in FIG.

  As shown in FIG. 37, in this process, the back surface 3b2 side of the semiconductor wafer WH2 is ground to reduce the thickness of the semiconductor wafer WH2. For example, in the present embodiment, since the thickness of the memory chip MC2 shown in FIG. 6 is about 30 μm to 50 μm, the grinding process is performed until the height from the surface 3a of the semiconductor wafer WH2 is about 30 μm to 50 μm. Apply. The grinding method can be performed by, for example, a CMP method.

  This step is the same as the above-described second wafer back surface grinding step except that the object to be ground is the semiconductor wafer WH2. Therefore, details of this step can be applied by replacing the description of the semiconductor wafer WH3 with the semiconductor wafer WH2 in the detailed description of the second wafer back surface grinding step. For this reason, the overlapping description is omitted.

<Fourth wafer mounting process>
Next, in the fourth wafer mounting step shown in FIG. 13, as shown in FIG. 38, the semiconductor wafer WH 1, with the front surface 3 a of the semiconductor wafer WH 1 and the back surface 3 b of the semiconductor wafer WH 2 facing each other, WH2 is bonded and fixed through the sealing material layer 6. FIG. 38 is a cross-sectional view showing a state in which semiconductor wafers are stacked in the fourth wafer mounting step shown in FIG. In the example shown in FIG. 13, the semiconductor wafer WH1 shown in FIG. 38 corresponds to the fourth wafer shown in FIG.

  As shown in FIG. 38, in the fourth wafer mounting process, the semiconductor wafer WH1 is mounted on the back surface 3b of the semiconductor wafer WH2. This step is the same as the third wafer mounting step described above except that the mounting target is the semiconductor wafer WH1 and the mounting target is the semiconductor wafer WH2. Therefore, details of this process can be applied by replacing the description of the semiconductor wafer WH2 with the semiconductor wafer WH1 and replacing the description of the semiconductor wafer WH3 with the semiconductor wafer WH2 in the detailed description of the third wafer mounting process described above. . For this reason, the overlapping description is omitted.

<4th wafer back grinding process>
Next, in the fourth wafer back surface grinding step shown in FIG. 13, as shown in FIG. 39, the back surface 3b2 of the semiconductor wafer WH1 is ground to expose each of the plurality of internal electrodes 3iv. FIG. 39 is a cross-sectional view showing a state where the back surface of the upper semiconductor wafer is ground in the fourth wafer back surface grinding step shown in FIG. 13.

  As shown in FIG. 39, in this step, the back surface 3b2 side of the semiconductor wafer WH1 is ground to reduce the thickness of the semiconductor wafer WH1. For example, in this embodiment, since the thickness of the memory chip MC1 shown in FIG. 6 is about 30 μm to 50 μm, the grinding process is performed until the height from the surface 3a of the semiconductor wafer WH1 becomes about 30 μm to 50 μm. Apply. The grinding method can be performed by, for example, a CMP method.

  This step is the same as the above-described second wafer back surface grinding step except that the object to be ground is the semiconductor wafer WH1. Therefore, details of this step can be applied by replacing the description of the semiconductor wafer WH3 with the semiconductor wafer WH1 in the detailed description of the second wafer back surface grinding step described above. For this reason, the overlapping description is omitted.

<Electrode formation process>
Next, in the electrode forming step shown in FIG. 13, as shown in FIGS. 40 and 41, a plurality of protruding electrodes 7b as external terminals are formed on the back surface 3b of the semiconductor wafer WH1. 40 is a cross-sectional view showing a state in which a plurality of protruding electrodes are formed on the back surface of the uppermost semiconductor wafer in the electrode forming step shown in FIG. FIG. 41 is an enlarged cross-sectional view showing the periphery of a region where a plurality of protruding electrodes are formed in the chip formation region shown in FIG.

  As shown in FIGS. 40 and 41, in the present embodiment, a plurality of through electrodes 3tsv are formed on the back surface 3b of the semiconductor wafer WH1 mounted on the uppermost stage of the wafer stack WHS in which the plurality of semiconductor wafers 50 are stacked. The tip surface is exposed. Therefore, in this step, the plurality of protruding electrodes 7b are formed on the exposed surfaces of the plurality of through electrodes 3tsv, respectively. As a method for forming the protruding electrode 7b, for example, a plating method can be applied.

  Here, in the present embodiment, the grinding process is performed until the groove 50tr formed in the semiconductor wafers WH3, WH2, and WH1 is reached in the second, third, and fourth wafer back surface grinding steps. Therefore, as shown in FIG. 40, the grooves 50tr of the semiconductor wafers WH4, WH3, WH2, and WH1 are in communication with each other. In other words, an opening that communicates from the back surface 3b of the semiconductor wafer WH1 to the bottom surface 50trb of the groove 50tr of the semiconductor wafer WH4 is formed on the dicing region 50b of the wafer stack WHS.

  For this reason, from the viewpoint of preventing the resist liquid from being embedded in the opening provided in the dicing region 50b of the wafer laminate WHS, in this step, a method that does not involve formation of a resist mask, for example, an electroless plating method is used. It is preferable to form the protruding electrode 7b.

  When the protruding electrode 7b made of a metal material such as nickel (Ni) or copper (Cu) is formed by electroless plating, as shown in FIG. 41, it is isotropic with the exposed surface of the through electrode 3tsv as the center. A plating film grows. Therefore, the protruding electrode 7b has a dome shape as shown in FIG.

  Although not shown in FIG. 41, in this step, the present invention is not limited to an embodiment in which a single metal film is formed, and a multilayer metal film made of a plurality of types of metal materials can be formed. For example, a metal film made of gold (Au) can be laminated on the surface of a metal film such as nickel (Ni) or copper (Cu). In this case, since the wettability of the protruding electrode 7b with respect to the solder material can be improved in the chip stacked body mounting step shown in FIG. 11, the connection strength with the solder material 7s shown in FIG. 6 can be improved. As a further modification, a solder material 7s can be formed on the exposed surface of the protruding electrode 7b in this step.

<First wafer back grinding process>
Next, in the first wafer back surface grinding step shown in FIG. 13, as shown in FIG. 42, the back surface 3b2 of the semiconductor wafer WH4 is ground and thinned to the thickness of the memory chip MC4 shown in FIG. FIG. 42 is a cross-sectional view showing a state in which the semiconductor wafer is ground in the first wafer back surface grinding step shown in FIG. In FIG. 42, the outline of the semiconductor wafer WH4 before grinding is indicated by a two-dot chain line in order to clearly indicate the position of the back surface 3b2 before performing the grinding process.

  As shown in FIG. 42, in this step, the wafer stack WHS is moved up and down with a support member 43 made of, for example, a tape material or a resin cured after application applied to the back surface 3b side of the semiconductor wafer WH1. Invert. Then, a grinding process is performed on the back surface 3b2 side of the semiconductor wafer WH4 to reduce the thickness of the semiconductor wafer WH4. For example, in the present embodiment, since the thickness of the memory chip MC4 shown in FIG. 6 is about 100 μm to 200 μm, the grinding process is performed until the height from the surface 3a of the semiconductor wafer WH4 becomes about 100 μm to 200 μm. Apply. The grinding method can be performed by, for example, a CMP method.

  In the present embodiment, in the first wafer back surface grinding step, the wafer stack WHS is not divided into individual pieces, but is divided into chip forming regions 50a in the individualization step described below. Therefore, at the stage where the first wafer back surface grinding step is completed, the bottom surface 50trb remains in the groove 50tr of the semiconductor wafer WH4.

  From the viewpoint of suppressing damage to the semiconductor wafer WH4 in each step from the first wafer preparation step to the electrode formation step shown in FIG. 13, the depth of the groove 50tr formed in the semiconductor wafer WH4 is reduced, and the semiconductor It is preferable to improve the strength of the wafer WH4. Therefore, from this viewpoint, it is preferable to separately perform the first wafer back surface grinding step and the singulation step as in the present embodiment.

<Individualization process>
Next, in the individualization step shown in FIG. 13, as shown in FIG. 43, the wafer stack WHS is divided into a plurality of chip stacks MCS by running the dicing blade 44 along the dicing area 50b. FIG. 43 is a cross-sectional view showing the singulation process shown in FIG. FIG. 44 is an enlarged cross-sectional view showing the periphery of the dicing region shown in FIG.

  As shown in FIG. 43, in this step, for example, the dicing blade 44 is caused to travel along the groove 50tr in a state where the dicing tape 40 as a support member is attached to the back surface 3b of the semiconductor wafer WH4.

  The dicing blade 44 shown in FIG. 43 and FIG. 44 is similar to the dicing blade 42 shown in FIG. 27. The cutting process is such that abrasive grains such as diamond are fixed to the outer periphery of a thin plate having a circular or ring-shaped outer shape. It is a jig. In addition, the dicing blade 44 is a rotary blade in which abrasive grains fixed to the outer periphery cut the object to be cut by rotating around the center of a circular or ring-shaped plane as a rotation axis. When the dicing blade 44 is caused to travel along the direction in which the dicing area 50b extends (see, for example, FIG. 16), the wafer stack WHS is cut along the dicing area 50b. Thereby, the wafer stacked body WHS is divided into a plurality of chip stacked bodies MCS.

  In this embodiment, as described above, an opening that communicates from the back surface 3b of the semiconductor wafer WH1 to the bottom surface 50trb of the groove 50tr of the semiconductor wafer WH4 is formed on the dicing region 50b of the wafer stack WHS. Has been. For this reason, in this process, the part to be cut, which is cut by the dicing blade 44, is a part from the bottom surface 50trb of the groove 50tr of the semiconductor wafer WH4 to the back surface 3b of the semiconductor wafer WH4.

  As shown in FIG. 44, this part to be cut is constituted by, for example, a semiconductor substrate SS made of silicon, an insulating film 3ps made of silicon oxide, and a part on the bonding surface side of the dicing tape 40. Further, most of the portion to be cut is constituted by the semiconductor substrate SS. For this reason, the cutting conditions such as the rotational speed of the dicing blade 44, the average grain size of the abrasive grains, and the pressing pressure can be optimized in accordance with the semiconductor substrate SS.

  Since the silicon oxide constituting the insulating film 3ps and the silicon constituting the semiconductor substrate SS have similar physical property values, the optimum values of the cutting conditions by the dicing blade 44 are also similar. In addition, the dicing tape 40 can select a material according to the cutting conditions of the semiconductor substrate SS. Therefore, according to the present embodiment, it is possible to prevent a chipping phenomenon in which the peripheral portion of the chip forming region 50a of the semiconductor wafer 50 is cracked or chipped at the time of cutting by the dicing blade 44 or Can be suppressed. Further, if the occurrence of a chipping phenomenon is prevented or suppressed in the singulation process shown in FIG. 13, the reliability of the chip stack MCS or the semiconductor device 1 (see FIG. 4) on which the chip stack MCS is mounted is improved. Can be made.

  In the example shown in FIGS. 43 and 44, the dicing blade 44 is inserted along the groove 50tr. Therefore, from the viewpoint of preventing or suppressing the dicing blade 44 from coming into contact with the side surface of the groove 50tr, as shown in FIG. 44, the width WB2 of the dicing blade 44 is equal to the width of the groove 50tr (ie, the cutting width) WT1. Narrower than that. In other words, the width WB2 of the dicing blade 44 is preferably narrower than the width WB1 of the dicing blade 42 shown in FIG. For example, in this embodiment, it is about 35 μm to 50 μm.

  Through the above steps, the chip stack MCS shown in FIG. 12 is obtained. As described above, for example, the chip stack preparation step shown in FIG. 11 can be performed independently at a place different from other steps. For example, the chip stack MCS can be assembled at a business establishment different from the business establishment that performs the assembly flow shown in FIG. In this case, the chip stack MCS includes a semiconductor device in which a plurality of semiconductor chips 3 are stacked via a sealing material layer 6 and a plurality of protruding electrodes 7b as external terminals are formed on the back surface 3b of the memory chip MC1. Can be seen. In this case, after obtaining the chip stack MCS, necessary inspections and tests such as an appearance inspection and an electrical test are performed and shipped.

<Assembly process for semiconductor devices>
Next, the manufacturing process of the semiconductor device 1 described with reference to FIGS. 1 to 10 will be described along the process flow shown in FIG.

<Board preparation process>
First, in the board preparation step shown in FIG. 11, the wiring board 20 shown in FIGS. 45 to 48 is prepared. 45 is a plan view showing the entire structure of the wiring board prepared in the board preparation step shown in FIG. 11, and FIG. 46 is an enlarged plan view for one device region shown in FIG. 47 is an enlarged cross-sectional view along the line AA in FIG. 45 to 47, the number of terminals is reduced for the sake of clarity. However, the number of terminals (bonding leads 2f, lands 2g) is limited to the mode shown in FIGS. Not.

  As shown in FIG. 45, the wiring board 20 prepared in this step includes a plurality of device regions 20a inside a frame portion (outer frame) 20b. Specifically, a plurality (27 in FIG. 45) of device regions 20a are arranged in a matrix. Each of the plurality of device regions 20a corresponds to the wiring board 2 shown in FIGS. The wiring substrate 20 is a so-called multi-piece substrate having a plurality of device regions 20a and a dicing line (dicing region) 20c between the device regions 20a. Thus, manufacturing efficiency can be improved by using a multi-piece substrate provided with a plurality of device regions 20a.

  As shown in FIGS. 46 and 47, each device region 20a is formed with the constituent members of the wiring board 2 described with reference to FIG. The wiring board 20 has an upper surface 2a, a lower surface 2b opposite to the upper surface 2a, and a plurality of wiring layers (four layers in the example shown in FIG. 4) that electrically connect the upper surface 2a side and the lower surface 2b side. In each wiring layer, an insulating layer (core layer) 2e that insulates between the plurality of wirings 2d and the plurality of wirings 2d and between adjacent wiring layers is formed. The wiring 2d includes a wiring 2d1 formed on the upper surface or the lower surface of the insulating layer 2e, and a via wiring 2d2 that is an interlayer conductive path formed so as to penetrate the insulating layer 2e in the thickness direction.

  As shown in FIG. 46, the upper surface 2a of the wiring board 20 is a chip mounting area (chip mounting portion) that is a planned area for mounting the logic chip LC shown in FIG. 10 in the first chip mounting process shown in FIG. 2p1 is included. The chip mounting area 2p1 is present at the center of the device area 20a on the upper surface 2a. In FIG. 46, the outline of the chip mounting area is indicated by a two-dot chain line in order to show the position of the chip mounting area 2p1, but since the chip mounting area 2p1 is a planned area for mounting the logic chip LC as described above, it is actually visually recognized. There need not be possible borders.

  A plurality of bonding leads (terminals, chip mounting surface side terminals, electrodes) 2f are formed on the upper surface 2a of the wiring board 20. The bonding lead 2f is a terminal electrically connected to the plurality of surface electrodes 3ap formed on the surface 3a of the logic chip LC shown in FIG. 10 in the first chip mounting step shown in FIG. In the present embodiment, since the logic chip LC is mounted by a so-called face-down mounting method in which the surface 3a side of the logic chip LC is opposed to the upper surface 2a of the wiring board 20, the bonding portions of the plurality of bonding leads 2f are connected to the chip. It is formed inside the mounting region 2p1.

  The upper surface 2a of the wiring board 20 is covered with an insulating film (solder resist film) 2h. An opening 2hw is formed in the insulating film 2h, and at least a part of the plurality of bonding leads 2f (bonding portion with semiconductor chip, bonding region) is exposed from the insulating film 2h in the opening 2hw. Further, as shown in FIG. 47, a plurality of lands 2g are formed on the lower surface 2b of the wiring board 20. The lower surface 2b of the wiring board 20 is covered with an insulating film (solder resist film) 2k. An opening 2kw is formed in the insulating film 2k, and at least a part of the plurality of lands 2g (joined portions with the solder balls 5 shown in FIG. 4) is exposed from the insulating film 2k in the opening 2kw.

  As shown in FIG. 47, the plurality of bonding leads 2f and the plurality of lands 2g are electrically connected to each other through a plurality of wirings 2d. The conductor patterns such as the plurality of wirings 2d, the plurality of bonding leads 2f, and the plurality of lands 2g are formed of a metal material containing copper (Cu) as a main component, for example. The plurality of wirings 2d, the plurality of bonding leads 2f, and the plurality of lands 2g can be formed by, for example, an electrolytic plating method. As shown in FIG. 47, the wiring board 20 having four or more wiring layers (four layers in FIG. 47) can be formed by, for example, a build-up method.

<First adhesive placement step>
Next, in the first adhesive material arranging step shown in FIG. 11, the adhesive material NCL1 is arranged on the chip mounting region 2p1 on the upper surface 2a of the wiring board 20, as shown in FIGS. 48 is an enlarged plan view showing a state in which an adhesive is disposed in the chip mounting region shown in FIG. 46, and FIG. 49 is an enlarged cross-sectional view taken along the line AA in FIG. 48 shows the positions of the chip mounting area 2p1 and the chip mounting area 2p2, and the outlines of the chip mounting areas 2p1 and 2p2 are indicated by two-dot chain lines. The chip mounting areas 2p1 and 2p2 are logic chips as described above. Since the LC is a planned area to be mounted, it is not necessary to have a boundary line that is actually visible. Hereinafter, in the case where the chip mounting areas 2p1 and 2p2 are illustrated, it is not necessary to have a boundary line that can be actually visually recognized.

  When mounting a semiconductor chip on a wiring board by a face-down mounting method (flip chip connection method), for example, a method of sealing the connection portion with a resin after electrically connecting the semiconductor chip and the wiring substrate (post-injection method) ) Is performed. In this case, the resin is supplied from a nozzle disposed in the vicinity of the gap between the semiconductor chip and the wiring board, and the resin is embedded in the gap using a capillary phenomenon.

  In the example described in the present embodiment, before the logic chip LC (see FIG. 4) is mounted on the wiring substrate 20 in the first chip mounting step described later, the adhesive NCL1 is disposed in the chip mounting region 2p1 and bonded. The logic chip LC is mounted by a method (first coating method) in which the logic chip LC is pressed from the material NCL1 and electrically connected to the wiring substrate 20.

  In the case of the pre-coating method, when the tip of the logic chip LC (for example, the solder material 7s formed at the tip of the conductor pillar 7p shown in FIG. 6) and the bonding portion of the bonding lead 2f contact each other, the wiring board 20 and the logic are already connected. An adhesive NCL1 is embedded between the chips LC. Therefore, it is preferable in that the processing time for one device region 20a can be shortened and the manufacturing efficiency can be improved as compared with the above-described post-injection method.

  However, as a modification to the present embodiment, the post-injection method can be applied by changing the order of the first chip mounting step and the first adhesive material arranging step shown in FIG. For example, when the number of product formation regions formed in a lump is small, the difference in processing time is small, so that a decrease in manufacturing efficiency can be suppressed even when the post-injection method is used.

  Further, as described above, the adhesive NCL1 used in the pre-coating method is made of an insulating (non-conductive) material (for example, a resin material), and is a joint between the logic chip LC (see FIG. 6) and the wiring board 20. By disposing the adhesive material NCL1 on the plurality of conductive members (the connecting material 7 and the bonding lead 2f shown in FIG. 6) provided in the joint portion can be electrically insulated.

  The adhesive NCL1 is made of a resin material whose hardness (hardness) is increased (increased) by applying energy, and in the present embodiment, for example, includes a thermosetting resin. Further, the adhesive NCL1 before curing is softer than the connecting material 7 shown in FIG. 6, and is deformed by pressing the logic chip LC.

  Further, the adhesive NCL1 before curing is roughly classified into the following two types due to differences in handling methods. One is made of a paste-like resin (insulating material paste) called NCP (Non-Conductive Paste) and applied to the chip mounting region 2p1 from a nozzle (not shown). The other is a method called NCF (Non-Conductive Film), which is made of a resin (insulating material film) previously formed into a film shape, and is transported to the chip mounting region 2p1 in the film state and pasted. When the insulating material paste (NCP) is used, the step of attaching as in the case of the insulating material film (NCF) is not required, so that the stress applied to the semiconductor chip or the like can be reduced as compared with the case where the insulating material film is used. On the other hand, when the insulating film (NCF) is used, the shape retaining property is higher than that of the insulating material paste (NCP), so that the range and thickness in which the adhesive material NCL1 is disposed can be easily controlled.

  In the example shown in FIGS. 48 and 49, an adhesive material NCL1 that is an insulating film (NCF) is disposed on the chip mounting region 2p1 and pasted so as to be in close contact with the upper surface 2a of the wiring board 20. Yes. However, although illustration is omitted, as a modification, insulating material paste (NCP) can also be used.

<First chip preparation process>
In the first chip preparation step shown in FIG. 11, the logic chip LC shown in FIGS. 10 and 48 is prepared. FIG. 50 is an explanatory view schematically showing the outline of the manufacturing process of the semiconductor chip provided with the through electrode shown in FIG. FIG. 51 is an explanatory view schematically showing the outline of the semiconductor chip manufacturing process following FIG. 50 and 51, the description will focus on the through electrode 3tsv and the manufacturing method of the back electrode 3bp electrically connected to the through electrode 3tsv, and the steps of forming various circuits other than the through electrode 3tsv are shown and described. Is omitted.

  First, as a semiconductor substrate preparation step, a semiconductor substrate SS shown in FIG. 50 is prepared. The semiconductor substrate SS is made of, for example, silicon (Si) and has a circular shape in plan view. The semiconductor substrate SS has a main surface (also referred to as a front surface or an upper surface) SSf that is a semiconductor element formation surface and a back surface (also referred to as a main surface or a lower surface) SSb opposite to the main surface SSf. Further, the thickness of the semiconductor substrate SS is thicker than the thickness of the logic chip LC and the memory chips MC1, MC2, MC3, and MC4 shown in FIG. 4, for example, about 700 to 800 μm.

  Next, as a hole forming step, a hole (hole, opening) 3tsh for forming the through electrode 3tsv shown in FIG. 6 is formed. In the example shown in FIG. 50, the hole 3tsh is formed by disposing the mask 25 on the main surface SSf of the semiconductor substrate SS and performing an etching process. The semiconductor element of the logic chip LC shown in FIG. 4 can be formed, for example, after this step and before the next wiring layer forming step.

  Next, a through electrode 3tsv is formed by embedding a metal material such as copper (Cu) in the hole 3tsh by, for example, a plating method. Next, as a wiring layer forming step, a wiring layer (chip wiring layer) 3d is formed on the main surface SSf of the semiconductor substrate SS. In this step, the plurality of surface electrodes 3ap shown in FIG. 6 are formed, and the plurality of through electrodes 3tsv and the plurality of surface electrodes 3ap are electrically connected to each other. Further, in this step, the semiconductor elements of the logic chip LC and the memory chips MC1, MC2, and MC3 shown in FIG. 4 and the plurality of surface electrodes 3ap shown in FIG. 6 are electrically connected through the wiring layer 3d.

  Next, as a protruding electrode forming step, the protruding electrode 7b is formed on the surface electrode 3ap (FIG. 6). FIG. 50 shows an example in which a conductor member formed in a columnar shape as the protruding electrode 7b, that is, a columnar electrode is formed. Also, a solder material 7s is formed at the tip of the protruding electrode 7b formed in a column shape. The solder material 7 s functions as a bonding material when the logic chip LC shown in FIG. 6 is mounted on the wiring board 2.

  Next, as the back surface grinding step shown in FIG. 51, the back surface SSb (see FIG. 50) side of the semiconductor substrate SS is ground (specifically, after grinding processing, polishing processing is performed), and the thickness of the semiconductor substrate SS is reduced. To do. Thereby, the back surface 3b of the semiconductor chip 3 shown in FIG. 6 is exposed. In other words, the through electrode 3tsv penetrates the semiconductor substrate SS in the thickness direction. In addition, the plurality of through electrodes 3tsv are exposed from the semiconductor substrate SS on the back surface 3b of the semiconductor substrate SS. In the example shown in FIG. 51, in the back surface grinding step, polishing is performed using the polishing jig 28 in a state where the semiconductor substrate SS is supported by the supporting base material 26 such as a glass plate and the protective layer 27 protecting the main surface SSf side. .

  Next, in the back electrode forming step, a plurality of back electrodes 3bp are formed on the back surface 3b, and are electrically connected to the plurality of through electrodes 3tsv.

  Next, as a singulation process, the semiconductor substrate SS is divided along dicing lines to obtain a plurality of logic chips LC (semiconductor chips 3). Thereafter, inspection is performed as necessary, and a logic chip LC (semiconductor chip 3) shown in FIG. 4 is obtained.

<First chip mounting process>
Next, in the first chip mounting step shown in FIG. 11, the logic chip LC is mounted on the wiring substrate 2 as shown in FIGS. 52 and 53. FIG. 52 is an enlarged plan view showing a state in which the logic chip LC is mounted on the chip mounting region of the wiring board shown in FIG. FIG. 53 is an enlarged cross-sectional view along the line AA in FIG.

  In this step, the logic chip LC is mounted by a so-called face-down mounting method (flip chip connection method) so that the surface 3a of the logic chip LC faces the upper surface 2a of the wiring substrate 2 as shown in FIG. In addition, the logic chip LC and the wiring board 2 are electrically connected by this process. Specifically, the plurality of surface electrodes 3ap formed on the surface of the logic chip LC and the plurality of bonding leads 2f formed on the upper surface 2a of the wiring board 2 are formed of the protruding electrodes 7b (see FIG. 6) and the solder material 7s (FIG. 6). Electrically connected via a reference).

  In this step, as shown in FIG. 53, the logic chip LC (semiconductor chip 3) is disposed on the chip mounting region 2p1 of the wiring board 20. A connecting material 7 is formed on the surface 3a side of the logic chip LC. On the other hand, a solder layer (not shown) that is a bonding material for electrically connecting to the protruding electrode 7b shown in FIG. 6 is formed at the bonding portion of the bonding lead 2f formed on the upper surface 2a of the wiring board 20. ing.

  Next, a heating jig (not shown) is pressed against the back surface 3 b side of the logic chip LC, and the logic chip LC is pressed toward the wiring board 20. Before the heat treatment, the adhesive material NCL1 is in a soft state. Therefore, when the logic chip LC is pushed in by a heating jig, the tips of the plurality of connecting materials 7 formed on the surface 3a of the logic chip LC are bonded to the bonding leads 2f. In contact with a bonding region (a solder layer not shown in detail).

  Next, in a state where the logic chip LC is pressed against a heating jig (not shown), the logic chip LC and the adhesive NCL1 are heated by the heating jig. At the junction between the logic chip LC and the wiring board 20, the solder material 7s (see FIG. 50) and the solder layer (not shown) on the bonding lead 2f are melted and integrated. Thereby, as shown in FIG. 6, the protruding electrode 7b and the bonding lead 2f are electrically connected via the solder material 7s.

  Further, the adhesive material NCL1 is cured by heating the adhesive material NCL1. As a result, the adhesive NCL1 cured in a state where a part of the logic chip LC is embedded is obtained. Further, the back surface electrode 3bp of the logic chip LC is exposed from the cured adhesive material NCL1.

<Second adhesive placement step>
Next, in the second adhesive material arranging step shown in FIG. 11, as shown in FIG. 54, the adhesive material NCL2 is formed on the back surface 3b of the logic chip LC (semiconductor chip 3) and on the adhesive material NCL1 exposed from the logic chip LC. Place. 54 is an enlarged plan view showing a state in which an adhesive is disposed on the back surface of the semiconductor chip shown in FIG. 52 and its periphery, and FIG.

  As shown in FIG. 6 described above, the semiconductor device 1 according to the present embodiment includes a logic chip LC and a logic chip mounted on the lowermost stage (for example, the first stage) among the plurality of stacked semiconductor chips 3. The chip stack MCS (see FIG. 4) mounted on the LC is electrically connected to the lower layer terminal via the connecting material 7 protruding from the front surface 3a or the back surface 3b of the semiconductor chip 3. For this reason, as described in the first adhesive material arranging step, the post-injection method can be applied as a modification, but the processing time for one device region 20a (see FIGS. 54 and 55) is shortened. And it is preferable to apply the above-mentioned application | coating method at the point which can improve manufacturing efficiency.

  In addition, as the adhesive NCL2 used in this step, any one of the lower NCP (insulating material paste) and NCF (insulating material film) can be used. In the example shown in FIGS. 54 and 55, NCP (insulating material paste) is ejected from the nozzle 30 (see FIG. 55) and bonded onto the back surface 3b of the logic chip LC and onto the adhesive NCL1 exposed from the logic chip LC. The material NCL2 is disposed.

  The insulating material paste (NCP) can be brought into close contact with the object to be applied (the logic chip LC in this step) with a lower load than the insulating material film (NCF). Therefore, the insulating material paste (NCP) is preferable from the viewpoint of reducing the stress on the logic chip LC already mounted in this step. However, although illustration is omitted, as a modification, an insulating material film (NCF) can be used as the adhesive material NCL2.

  In the example shown in FIG. 54, the adhesive material NCL2 is applied in a strip shape on the back surface 3b of the logic chip LC along the diagonal line of the logic chip LC having a square shape in plan view. As described above, a method of applying the paste-like adhesive NCL2 (referred to as a cross-coating method) so as to form two strips intersecting each other in the application region of the adhesive NCL2 is a chip stack mounting described later. In the process, it is preferable in that the adhesive NCL2 is easily spread evenly. However, a coating method different from that shown in FIG. 54 can be used as long as the adhesive material NCL2 can be expanded so as not to cause a gap in the chip stack mounting process described later.

<Chip laminate preparation process>
Further, in the chip laminated body preparation step shown in FIG. 11, as shown in FIG. 12, a chip laminated body in which a plurality of memory chips MC1, MC2, MC3, MC4 are laminated (laminated body, memory chip laminated body, semiconductor chip laminated body). Body, semiconductor device) MCS is prepared. The details of this step have been described in detail in the section <Details of Chip Laminate Preparation Step> described above.

<Chip stack mounting process>
Next, in the chip stacked body mounting step shown in FIG. 11, as shown in FIGS. 56 and 57, the chip stacked body MCS is mounted on the logic chip LC. 56 is an enlarged plan view showing a state in which a stacked body of memory chips is mounted on the back surface of the logic chip shown in FIG. FIG. 57 is an enlarged cross-sectional view along the line AA in FIG.

  In this step, as shown in FIG. 57, the back surface 3b of the chip stack MCS (that is, the back surface 3b of the memory chip MC1) is opposed to the back surface 3b of the logic chip LC (or the top surface 2a of the wiring board 20). The chip stack MCS is mounted. In addition, the chip stack MCS and the logic chip LC are electrically connected by this process. Specifically, as shown in FIG. 6, the plurality of through-electrodes 3tsv exposed on the back surface 3b of the chip stacked body MCS and the plurality of back surface electrodes 3bp formed on the back surface 3b of the logic chip LC include the protruding electrodes 7b and the solder material 7s. It is electrically connected via.

  In this step, the back surface 3b located on the side far from the element formation surface on which a plurality of semiconductor elements (for example, circuit elements constituting the main memory circuit MM shown in FIG. 5) included in the memory chip MC1 are formed is formed on the logic chip. It is made to oppose the mounting surface (back surface 3b) of LC. Strictly speaking, this is a face-up mounting method. However, as shown in FIG. 6, the logic chip LC and the memory chip MC <b> 1 are connected via the protruding electrodes 7 b and the solder material 7 s (not via wires not shown). In this respect, the connection method between the memory chip MC1 and the logic chip LC can be considered similarly to the flip chip connection method. For example, the connection portion can be protected by sealing the periphery of the connection portion that electrically connects the chip stack MCS and the logic chip LC with the adhesive NCL.

  In this step, as shown in FIG. 56, the chip stack MCS is arranged on the chip mounting area (chip mounting portion) 2p2 of the wiring board 20. The chip mounting region 2p2 is a region where the chip stack MCS is to be mounted in this step, and it is not necessary to have an actually visible boundary line as in the chip mounting region 2p1 described in the first chip mounting step. . In this step, the plurality of protruding electrodes 7b (see FIG. 12) formed on the chip stacked body MCS and the plurality of back surface electrodes 3bp (see FIG. 6) of the logic chip LC are arranged to face each other.

  Next, a heating jig (not shown) is pressed against the back surface 3 b side of the chip stack MCS, and the chip stack MCS is pressed toward the wiring board 20. Since the adhesive NCL2 is in a paste state, when the chip stack MCS is pushed in by a heating jig, the adhesive NCL2 shown in FIG. 55 is spread between the logic chip LC and the chip stack MCS. Further, the tips of the plurality of protruding electrodes 7b (see FIG. 6) formed on the back surface 3b of the chip stacked body MCS are in contact with the back surface electrode 3bp (see FIG. 6) of the logic chip LC.

  Next, in a state where a heating jig (not shown) is pressed against the chip stack MCS, the chip stack MCS and the adhesive NCL2 are heated by the heating jig. At the joint between the chip stack MCS and the logic chip LC, the solder material 7s (see FIG. 6) is melted and joined to the protruding electrode 7b and the back electrode 3bp. Thereby, as shown in FIG. 6, the plurality of protruding electrodes 7b of the chip stacked body MCS and the plurality of back surface electrodes 3bp of the logic chip LC are electrically connected via the connecting material 7 (solder material 7s). . In addition, since the plurality of back surface electrodes 3bp of the logic chip LC are electrically connected to the plurality of through electrodes 3tsv of the logic chip LC, respectively, the chip stack MCS is connected to the plurality of through electrodes 3tsv of the logic chip LC by this process. It is electrically connected to the circuit formed on the logic chip LC via (see FIG. 6).

  Further, the adhesive material NCL2 is cured by heating the adhesive material NCL2. Thereby, the chip stack MCS is bonded and fixed on the logic chip LC.

<Sealing process>
Next, in the sealing step shown in FIG. 11, as shown in FIG. 58, the upper surface 2a of the wiring substrate 20, the logic chip LC, and the chip stack MCS of the plurality of memory chips MC1, MC2, MC3, MC4 are made of resin. The sealing body 4 is formed by sealing. 58 is an enlarged sectional view showing a state in which a sealing body is formed on the wiring substrate shown in FIG. 57 and a plurality of stacked semiconductor chips are sealed. FIG. 59 is a plan view showing the entire structure of the sealing body shown in FIG.

  In the present embodiment, as shown in FIG. 59, a sealing body 4 is formed which collectively seals a plurality of semiconductor chips respectively mounted in a plurality of device regions 20a. Such a method of forming the sealing body 4 is called a collective sealing (Block Molding) method, and a semiconductor package manufactured by the collective sealing method is called a MAP (Multi Array Package) type semiconductor device. In the collective sealing method, the interval between the device regions 20a can be reduced, so that the effective area of one wiring board 20 is increased. That is, the number of products that can be obtained from one wiring board 20 increases. Thus, the manufacturing process can be made efficient by increasing the effective area of one wiring board 20.

Further, in the present embodiment, the resin is formed by a so-called transfer mold method in which a heat-softened resin is press-fitted into a molding die (not shown) and then the resin is thermally cured. The sealing body 4 formed by the transfer mold method is more durable than a case where a liquid resin is cured, for example, a sealing material layer 6 for sealing the chip stack MCS shown in FIG. Because of its high properties, it is suitable as a protective member. Further, for example, silica (silicon dioxide; SiO ₂₎ filler particles such as particles by mixing the thermosetting resin, it is possible to improve the function of the sealing body 4 (for example, resistance to warping deformation).

  In the present embodiment, the joint portions (electrical connection portions) of the stacked semiconductor chips 3 are sealed with the adhesive materials NCL1 and NCL2 and the sealing material layer 6. Therefore, it can apply to the embodiment which does not form the sealing body 4 as a modification. In this case, this sealing body process can be omitted.

<Ball mounting process>
Next, in the ball mounting step shown in FIG. 11, as shown in FIG. 60, a plurality of solder balls 5 serving as external terminals are joined to a plurality of lands 2 g formed on the lower surface 2 b of the wiring board 20. 60 is an enlarged cross-sectional view showing a state in which solder balls are bonded onto a plurality of lands of the wiring board shown in FIG.

  In this step, as shown in FIG. 60, after the wiring board 20 is turned upside down, the solder balls 5 are disposed on each of the plurality of lands 2g exposed on the lower surface 2b of the wiring board 20, and then heated. A plurality of solder balls 5 and lands 2g are joined together. By this step, the plurality of solder balls 5 are electrically connected to the plurality of semiconductor chips 3 (logic chip LC and memory chips MC1, MC2, MC3, MC4) via the wiring substrate 20. However, the technique described in the present embodiment is not limited to a so-called BGA (Ball Grid Array) type semiconductor device in which solder balls 5 are joined in an array. For example, as a modification to the present embodiment, the so-called LGA is shipped in which the solder balls 5 are not formed and the lands 2g are exposed, or the lands 2g are coated with a solder paste thinner than the solder balls 5. It can be applied to a (Land Grid Array) type semiconductor device. In the case of an LGA type semiconductor device, the ball mounting process can be omitted.

<Individualization process>
Next, in the singulation process shown in FIG. 11, as shown in FIG. 61, the wiring board 20 is divided for each device region 20a. 61 is a cross-sectional view showing a state in which the multi-piece wiring board shown in FIG. 60 is separated. In this step, as shown in FIG. 61, the wiring substrate 20 and the sealing body 4 are cut along a dicing line (dicing region) 20c to obtain a plurality of separated semiconductor devices 1 (see FIG. 4). To do. The cutting method is not particularly limited, but in the example shown in FIG. 61, the wiring substrate 20 and the sealing body 4 that are bonded and fixed to the tape material (dicing tape) 36 using the dicing blade (rotating blade) 35 are connected to the wiring substrate 20. The embodiment which cuts and cuts from the lower surface 2b side of this is shown. However, the technique described in the present embodiment is not applied only to the case where the wiring substrate 20 that is a multi-piece substrate including a plurality of device regions 20a is used. For example, the present invention can be applied to a semiconductor device in which a plurality of semiconductor chips 3 are stacked on a wiring board 2 (see FIG. 4) corresponding to one semiconductor device. In this case, the singulation process can be omitted.

  Through the above steps, the semiconductor device 1 described with reference to FIGS. 1 to 10 is obtained. Thereafter, necessary inspections and tests such as an appearance inspection and an electrical test are performed and shipped or mounted on a mounting board (not shown).

  Next, a typical modification of this embodiment will be described.

<Modification 1>
In the above <electrode forming step>, the embodiment in which the dome-shaped protruding electrode 7b is formed by the electroless plating method has been described. However, as a modification, as shown in FIG. 62, on the extension line of the through electrode 3tsv. A protruding electrode 7b that extends in a columnar shape can be formed. FIG. 62 is an enlarged cross-sectional view showing a modification to FIG. FIG. 63 is an enlarged cross-sectional view showing the periphery of the dicing region in a modification to FIG. FIG. 64 is an enlarged cross-sectional view showing a further modification to FIG.

  In the example shown in FIG. 62, the protruding electrode 7b formed in a columnar shape has, for example, a cylindrical shape, and the length of the height Tb is larger than the length of the diameter Rb of the column. As described with reference to FIG. 41, when the protruding electrode 7b is formed using the electroless plating method, the metal film grows isotropically. For this reason, if it is going to make small the separation distance of the adjacent projecting electrode 7b, ie, the arrangement pitch of the several projecting electrode 7b, the height of the projecting electrode 7b will become low.

  On the other hand, as shown in FIG. 62, the protruding electrode 7b having a cylindrical shape is formed by using a photolithographic technique in the same manner as the method for forming the conductive pillar 7p (see FIG. 25) described with reference to FIGS. The through hole is formed in the mask, and the conductive film is embedded in the through hole. In this case, since the shape of the protruding electrode 7b is determined by the opening shape of the through-hole formed in the mask, the cylindrical protruding electrode 7b can be formed even when formed by the electroless plating method. Further, when the protruding electrode 7b is formed by the electrolytic plating method, it can be selectively grown on the through electrode 3tsv of the semiconductor wafer WH1, so that the total amount of the plated metal film can be reduced.

  In addition, when distinguishing the protruding electrode 7b formed in the columnar shape described in the present modification from the protruding electrode 7b formed in the dome shape as shown in FIG. 41, the protruding electrode 7b in the present modified example is a columnar electrode, The protruding electrode 7b shown in FIG. 41 can be defined as a dome-shaped electrode.

  Here, when the protruding electrode 7b is formed in a columnar shape (for example, a cylindrical shape), a mask for forming a through hole is required. Further, it is necessary to deposit a resist film used when forming a through hole in the mask. However, as shown in FIG. 40, on the dicing region 50b of the wafer stacked body WHS, an opening that communicates from the back surface 3b of the semiconductor wafer WH1 to the bottom surface 50trb of the groove 50tr of the semiconductor wafer WH4 is formed. Therefore, when a liquid resin is dropped as a mask for forming the plurality of protruding electrodes 7b shown in FIG. 62, the resin is embedded in the opening.

  Therefore, in this modified example, in the fourth wafer back surface grinding step shown in FIG. 13, as shown in FIG. 63, the grinding process is performed so that a part of the semiconductor substrate SS constituting the semiconductor wafer WH1 remains in the dicing region 50b. Apply. In other words, in the fourth wafer back surface grinding step, the grinding process is performed so as to leave the bottom surface 50trb of the groove 50tr formed in the semiconductor wafer WH1. In other words, in the fourth wafer back surface grinding step, a grinding process is performed so that the plurality of chip formation regions 50a are not divided (or maintained in a connected state).

  If the polishing process is performed as described above, the back surface 3b of the semiconductor wafer WH1 after the fourth wafer back surface grinding step is not divided into a plurality of chip formation regions 50a. In addition, the back surface 3b of the semiconductor wafer WH1 after the fourth wafer back surface grinding step is not formed with an opening communicating with the bottom surface 50trb of the groove 50tr formed in the semiconductor wafer WH1. Therefore, in the electrode forming step shown in FIG. 13, even if liquid resin is dropped as a mask for forming the plurality of protruding electrodes 7b shown in FIG. 62, a hollow space is maintained in the groove 50tr shown in FIG. The

  As described above, according to this modification, in the step of grinding the back surface of the semiconductor wafer WH1 on which the protruding electrodes 7b are formed, the grinding process is performed so as to leave the bottom surface 50trb of the groove 50tr formed in the semiconductor wafer WH1. The protruding electrode 7b can have a columnar shape.

  As shown in FIG. 62, if the plurality of protruding electrodes 7b are formed in a columnar shape, the length Tb can be made longer than the diameter Rb. For this reason, the arrangement pitch of the plurality of protruding electrodes 7b can be reduced. In this modification, as a difference between the dome-shaped electrode and the columnar electrode, it has been described that the length Tb can be easily made longer than the length of the diameter Rb in the case of the columnar electrode. However, the relationship between the height of the protruding electrode 7b and the diameter Rb can be determined by the electrical characteristics required for the protruding electrode 7b and the thickness requirements of the semiconductor device. For example, even when the protruding electrode 7b is formed in a columnar shape, the length Tb can be shorter than the length Rb. In this case, the amount of metal used when forming the protruding electrode 7b can be reduced.

  As shown in FIG. 62, if the plurality of protruding electrodes 7b are formed in a columnar shape, for example, when the solder material 7s is formed at the tip of the protruding electrode 7b, the solder material 7s is affected by the surface tension of the solder component. It is easy to selectively form the tip surface of the protruding electrode 7b. That is, it is difficult for the solder material 7s to adhere to the side surface of the columnar protruding electrode 7b. Therefore, even when the arrangement pitch of the plurality of protruding electrodes 7b is narrowed, the solder material 7s can be formed in advance on the tip surface of the protruding electrode 7b.

  As shown in FIG. 63, in the step of grinding the back surface of the semiconductor wafer WH1 on which the protruding electrodes 7b are formed, as a method of performing a grinding process so as to leave the bottom surface 50trb of the groove 50tr formed in the semiconductor wafer WH1, for example The following two methods are conceivable.

  As a first method, a method is conceivable in which the thickness of the semiconductor wafer WH1 after the polishing process is made larger than the thickness of the semiconductor wafers WH2 and WH3 after the polishing process. In this case, since the trenches 50tr formed in the semiconductor wafers WH1, WH2, and WH3 can have the same depth, the semiconductor wafers WH1, WH2, and WH3 are collectively manufactured in the wafer preparation process shown in FIG. can do.

  As a second method, in the wafer preparation step shown in FIG. 18, the depth of the groove 50tr formed in the semiconductor wafer WH1 is shallower than the depth of the groove 50tr formed in the semiconductor wafers WH2, WH3, and WH4. A method is conceivable. In this case, the thickness of the memory chip MC1 of the finally obtained chip stack MCS can be made equal to the thickness of the memory chips MC2 and MC3.

  As a further modification to FIG. 63, as shown in FIG. 64, a grinding process is performed so that a part of each of the semiconductor substrates SS constituting the semiconductor wafers WH1, WH2, and WH3 remains in the dicing region 50b. Can be considered. In this case, in the wafer preparation process shown in FIG. 18, the semiconductor wafers WH1, WH2, and WH3 can be manufactured together. In addition, the thickness of the memory chip MC1 of the finally obtained chip stack MCS can be made equal to the thickness of the memory chips MC2 and MC3.

  In the case of the modification shown in FIG. 63, in the singulation process of dividing the wafer stack WHS for each chip formation region 50a, a part of the semiconductor substrate SS constituting the semiconductor wafer WH1 is included in the cutting target portion. Become. In the case of the modification shown in FIG. 64, in the singulation process of dividing the wafer stack WHS for each chip formation region 50a, a part of each of the semiconductor substrates SS constituting the semiconductor wafers WH1, WH2, and WH3 is cut. It will be included in the part to be processed. However, as described above, according to the present embodiment, the cutting process conditions such as the number of rotations of the dicing blade 44 (see FIG. 44), the average grain size of the abrasive grains, and the pressing pressure are optimized in accordance with the semiconductor substrate SS. Can be Therefore, even in the modification examples shown in FIGS. 63 and 64, the occurrence of the above-described chipping phenomenon can be suppressed.

<Modification 2>
In the section of <First Wafer Back Surface Grinding Step> described above, in this first wafer back surface grinding step, the wafer stack WHS is not divided into individual pieces. Explained how to divide. In this case, at the stage where the first wafer back surface grinding step is completed, the bottom surface 50trb remains in the groove 50tr of the semiconductor wafer WH4.

  However, as a modified example, as shown in FIG. 65, an embodiment is conceivable in which in the first wafer back surface grinding step, the wafer stack WHS is ground to a thickness that is divided for each chip formation region 50a. FIG. 65 is a cross-sectional view showing a modification to FIG. In the case of the modification shown in FIG. 65, the singulation process shown in FIG. 13 can be omitted. That is, the cutting process by the dicing blade in the state where the thickness of the semiconductor wafer WH4 is reduced can be omitted. For this reason, generation | occurrence | production of the chipping phenomenon resulting from the cutting process using a dicing blade can be prevented.

  In the case of this modification shown in FIG. 65, in the groove forming step shown in FIG. 18, the depth of the groove 50tr formed in the semiconductor wafer WH4 is preferably made larger than the depth of the semiconductor wafers WH1, WH2, and WH3. Thereby, the wafer laminated body WHS can be easily divided in the first wafer back surface grinding step shown in FIG.

  Further, as another modification to the above-described first wafer back grinding process, when the semiconductor wafer WH4 does not need to be thin in relation to the thickness of the memory chip MC4 shown in FIG. 6, the first wafer back grinding process. Can be omitted. As yet another modification, the electrode forming step can be performed after the first wafer back surface grinding step.

(Embodiment 2)
In the first embodiment, the sealing material layer 6 formed in the dicing region 50b of the wafer stack WHS in which the plurality of semiconductor wafers 50 are stacked is removed in advance and then divided into the chip formation regions 50a. The embodiment has been described. In this case, when the singulation process shown in FIG. 13 is performed, cutting conditions such as the number of revolutions of the dicing blade 44 (see FIG. 44), the average grain size of the abrasive grains, and the pressing pressure are applied to the semiconductor substrate SS. By optimizing together, the occurrence of the chipping phenomenon can be prevented or suppressed.

  In the present embodiment, the chipping phenomenon is achieved by optimizing the cutting process conditions such as the rotational speed of the dicing blade 44, the average grain diameter of the abrasive grains, and the pressing pressure in accordance with the sealing material layer 6 in the individualization process. An embodiment for preventing or suppressing the occurrence of the above will be described.

  The present embodiment is different from the first embodiment in the assembly flow of the chip stack MCS shown in FIG. 12 described in the first embodiment, but the other points are the same as those in the first embodiment. . Therefore, in the present embodiment, the description will focus on the differences from the technology described in the first embodiment, and a duplicate description will be omitted.

  FIG. 66 is an explanatory diagram showing a process flow which is a modified example of FIG. 13 for forming the chip stack shown in FIG. FIG. 67 is a cross-sectional view showing a modification to FIG. 28, and is a cross-sectional view showing a state after the second wafer mounting step shown in FIG. FIG. 68 is a sectional view showing a state in which grooves are formed along the dicing region of the semiconductor wafer in the second groove forming step shown in FIG. FIG. 69 is an enlarged cross-sectional view showing one of the dicing regions shown in FIG. 68 in an enlarged manner. FIG. 70 is an enlarged sectional view showing the periphery of the dicing region after the fourth groove forming step shown in FIG. 71 is an enlarged cross-sectional view showing a state where the wafer laminated body shown in FIG. 70 is cut.

  As shown in FIG. 66, the present embodiment is different from the first embodiment in that the first groove forming step shown in FIG. 13 is not performed. Further, the present embodiment is different from the first embodiment in that the second, third, and fourth groove forming steps are performed after the second, third, and fourth wafer mounting steps, respectively. In other words, in this embodiment, when the second, third, and fourth wafer mounting steps are performed, the sealing material layer 6 remains in the dicing region 50b as illustrated in FIG.

  For example, as shown in FIG. 67, in the present embodiment, the second wafer mounting process shown in FIG. 66 is performed in a state where the groove 50tr (see FIG. 28) is not formed. At this time, in the state where the surface 3a of the semiconductor wafer WH4 and the surface 3a of the semiconductor wafer WH3 are arranged to face each other, the sealing material layers 6 of the semiconductor wafers WH3 and WH4 are bonded together as in the above embodiment. It is. Further, the point that the plurality of chip formation regions 50a of the semiconductor wafer WH4 and the plurality of chip formation regions 50a of the semiconductor wafer WH3 are bonded so as to overlap is the same as in the above embodiment. Further, the point that bonding is performed so that the dicing region 50b of the semiconductor wafer WH4 and the dicing region 50b of the semiconductor wafer WH3 overlap each other is the same as in the above embodiment.

  However, as shown in FIG. 67, in this embodiment, the sealing material layer 6 in the dicing region 50b is not removed in advance. For this reason, when the sealing material layers 6 of the semiconductor wafers WH3 and WH4 are bonded together in a state where the surface 3a of the semiconductor wafer WH4 and the surface 3a of the semiconductor wafer WH3 are opposed to each other, the sealing material layer 6 is formed. The semiconductor wafers WH3 and WH4 are in close contact with each other on the opposing surfaces.

  In the example shown in FIG. 66, the second groove forming step is performed after the second wafer back surface grinding step. In the second groove forming step of the present embodiment, for example, as shown in FIGS. 68 and 69, the dicing blade 42 is caused to travel from the back surface 3b side of the semiconductor wafer WH3 having a reduced thickness, and the dicing area 50b is cut. Apply processing.

  Here, when the thin semiconductor wafer WH3 and the sealing material layer 6 are collectively cut by the dicing blade 42, as described with reference to FIGS. 14 and 15 in the first embodiment. In addition, a plurality of members having greatly different optimum values of the cutting process conditions are collectively cut. In the example shown in FIG. 69, the semiconductor wafer WH3 and the sealing material layer 6 are cut in a single layer state. For this reason, as described with reference to FIGS. 14 and 15, when compared with a case where a plurality of semiconductor wafers 50 and a plurality of sealing material layers 6 are laminated together and subjected to cutting in a lump, The occurrence of the chipping phenomenon can be suppressed. However, if an excessive load is applied from the dicing blade 42 at the bonding interface between the surface 3a of the semiconductor wafer WH3 and the sealing material layer 6, the above-described chipping phenomenon occurs.

  Therefore, in the present embodiment, in the second groove forming step, the semiconductor wafer WH3 disposed in the dicing region 50b is removed, and cutting is performed so that a part of the sealing material layer 6 on the semiconductor wafer WH4 side remains. Apply processing. In other words, in the present embodiment, in the second groove forming step, the constituent members of the semiconductor wafer WH3 (that is, the semiconductor substrate SS and the insulating film 3ps shown in FIG. 69) are selectively removed. In other words, in the present embodiment, after the second groove forming step is completed, the semiconductor wafer WH3 is divided for each chip formation region 50a and disposed between the semiconductor wafer WH3 and the semiconductor wafer WH4. The sealing material layer 6 is in a state where a plurality of chip formation regions 50a are connected.

  Although overlapping description is omitted, in the present embodiment, each of the third groove forming process and the fourth groove forming process shown in FIG. 66 is performed in the dicing region 50b in the same procedure as the above-described second groove forming process. The constituent material of the semiconductor wafer 50 is selectively removed. Therefore, in the wafer stack WHS after the completion of the fourth groove forming step shown in FIG. 66, the semiconductor substrate SS and the insulating film 3ps on the dicing region 50b of the semiconductor wafer WH4 are removed as shown in FIG. . In the wafer stacked body WHS, a plurality of sealing material layers 6 are disposed on the dicing region 50b of the semiconductor wafer WH4 so as to be spaced apart from each other through a groove 50tr.

  In the present embodiment, in the individualization step shown in FIG. 66, cutting is performed using a dicing blade 44 as shown in FIG. At this time, as described above, since the plurality of sealing material layers 6 are spaced apart from each other via the groove 50tr (see FIG. 70) on the dicing region 50b of the semiconductor wafer WH4, the cutting process is performed. The object is mainly the sealing material layer 6. Therefore, the chipping phenomenon can be prevented or suppressed by optimizing the cutting conditions such as the rotational speed of the dicing blade 44, the average grain size of the abrasive grains, and the pressing pressure according to the sealing material layer 6. . Further, in the individualization process of the present embodiment, the dicing blade 44 collectively cuts the plurality of sealing material layers 6 and the semiconductor substrate SS of the semiconductor wafer WH4. However, since the semiconductor wafer WH4 is thicker than the other semiconductor wafers WH1, WH2, and WH3, even if the cutting conditions by the dicing blade 44 are not optimum values for the semiconductor substrate SS, The above-mentioned chipping phenomenon hardly occurs.

  As described above, according to the present embodiment, each time the semiconductor wafers WH3, WH2, and WH1 are stacked on the semiconductor wafer WH4, the groove 50tr (see FIG. 70) is formed to configure the semiconductor wafers WH3, WH2, and WH1. Remove the member. As a result, in the singulation process, if the cutting process conditions such as the rotational speed of the dicing blade 44, the average grain size of the abrasive grains, and the pressing pressure are optimized according to the sealing material layer 6, the occurrence of chipping phenomenon can be prevented. Can be prevented or suppressed.

  In the second, third, and fourth groove forming steps shown in FIG. 66, cutting is performed so as to leave a part of the sealing material layer 6 as described above. The following embodiments are preferred. That is, if most of the semiconductor substrate SS shown in FIG. 69 is removed, the occurrence of the chipping phenomenon in the singulation process can be suppressed. However, when a part of the semiconductor substrate SS remains in the dicing region 50b, there is a possibility that the residue is lost and becomes a foreign substance. Therefore, it is preferable to reliably remove the semiconductor substrate SS from the viewpoint of reliably suppressing the generation of foreign substances made of a semiconductor material. That is, it is preferable to cut the sealing material layer 6 so that the contact surface with the semiconductor substrate SS is at least removed.

  On the other hand, from the viewpoint of reducing the load at the time of cutting the semiconductor wafer WH3 having a reduced thickness, the amount of the sealing material layer 6 that is cut in the second, third, and fourth groove forming steps is small. Is preferred. Therefore, in the second, third, and fourth groove forming steps, it is particularly preferable to perform cutting so that more than half of the sealing material layer 6 disposed in the dicing region 50b remains.

  In the present embodiment, an example has been described with respect to an embodiment in which the cutting conditions are optimized according to the sealing material layer 6 to prevent or suppress the occurrence of the chipping phenomenon. On the other hand, there are various modifications. For example, FIG. 66 shows an example in which the second, third, and fourth groove forming steps are performed after the second, third, and fourth wafer back grinding steps. The order of can be changed. FIG. 66 shows an embodiment in which the fourth groove forming step is performed before the electrode forming step. If the electrode forming step is after the fourth wafer back surface grinding step, for example, the fourth groove forming step is performed. Can be done before. Further, the present invention can be applied in combination with the first and second modifications described in the first embodiment.

  The manufacturing method of the semiconductor device described in the present embodiment is the same as that of the first embodiment except for the differences described above. Therefore, the overlapping description is omitted.

(Embodiment 3)
In the first embodiment and the second embodiment, the semiconductor wafer WH4 used as a semiconductor chip is used as a base material, and the semiconductor wafers WH3, WH2, and WH1 are stacked on the semiconductor wafer WH4 that is the base material, and the chip stack MCS. The embodiment of forming the has been described. However, a base material that is a support member for stacking the plurality of semiconductor wafers 50 is not limited to the semiconductor wafer 50. In this embodiment, for example, an embodiment in which a chip stack is obtained by stacking a semiconductor wafer on a base material using a support member such as a silicon substrate on which no circuit element is formed or a glass substrate as a base material. To do.

  72 is a perspective view showing a modification of the chip stack shown in FIG. FIG. 73 is an explanatory diagram showing a process flow which is a modified example of FIG. 13 for forming the chip stack shown in FIG. In the present embodiment, the member corresponding to the first wafer shown in FIG. 13 is replaced with a support member. However, in FIG. 73, the second, third, and third members are replaced to facilitate comparison with FIG. The names of four wafers are shown without change.

  If the outline | summary of this Embodiment is demonstrated previously, this Embodiment will replace the semiconductor wafer WH4 demonstrated in the said Embodiment 1 with the support member which can improve support strength rather than the semiconductor wafer WH4. It is the embodiment to assemble. Therefore, as shown in FIG. 73, in the process flow of the present embodiment, the first wafer preparation process and the first groove forming process shown in FIG. 13 described in the first embodiment are replaced with the support member preparation shown in FIG. It is replaced with a process. Further, in the present embodiment, the first wafer back surface grinding step shown in FIG. 13 is not performed, and as shown in FIG. 73, the chip stack MCS shown in FIG. Obtained by peeling from the support member. For this reason, in the said Embodiment 1, when obtaining the chip | tip laminated body MCS, the singulation process which performs a cutting process can be abbreviate | omitted.

  In the supporting member preparation step shown in FIG. 73, a supporting member 51 serving as a base material for stacking the semiconductor wafers 50 is prepared as shown in FIG. 74 is a cross-sectional view showing the support member prepared in the support member preparation step shown in FIG. 73 and the semiconductor wafer prepared in the second wafer preparation step. The support member 51 has a front surface 51a that is a wafer stacking surface on which a plurality of semiconductor wafers 50 are stacked, and a back surface 51b that is located on the opposite side of the front surface 51a. Further, since the support member 51 is a base material for stacking the semiconductor wafers 50 as described above, it is a plate member such as a silicon substrate or a glass substrate on which no circuit element is formed.

  Although illustration is omitted, the planar shape of the support member 51 (that is, the shape of the front surface 51a and the back surface 51b) is not particularly limited as long as it has an area covering the entire surface 3a of the semiconductor wafer 50. For example, when the silicon substrate is used as the support member 51, it can be manufactured in the same manner as the semiconductor wafer 50 by making it circular like the semiconductor wafer 50. Further, when the glass substrate is used as the support member 51, it can be formed into an arbitrary planar shape such as a quadrangle in consideration of ease of processing. However, in consideration of apparatus transportability and recognizability, even when a glass substrate is used for the support member 51, it is preferable to have the same planar shape as the semiconductor wafer 50.

  In the example shown in FIG. 74, the thickness 51T of the support member 51 is larger than the thickness 50T of the semiconductor wafer 50 from the viewpoint of making the strength of the support member 51 stronger than the strength of the semiconductor wafer 50. However, as described in the first embodiment, even when the thickness is the same as the thickness 50T of the semiconductor wafer 50, the occurrence of chipping phenomenon can be suppressed during processing, so the thickness 51T of the support member 51 and the semiconductor wafer The thickness 50T may be the same. For example, when the silicon substrate is used as the support member 51, the thickness 51 T of the support member 51 and the thickness 50 T of the semiconductor wafer 50 are made the same, thereby manufacturing the semiconductor wafer 50 and manufacturing the support member 51. The process can be shared.

  As shown in FIG. 74, the support member 51 is dicing with the first region 51c, which is a region where the plurality of chip formation regions 50a of the semiconductor wafer WH3 are arranged to face each other in the second wafer mounting step shown in FIG. The region 50b includes a second region 51d that is a region opposed to the region 50b.

  Also, as shown in FIG. 74, the support member 51 and the chip stack MCS (see FIG. 72) are peeled off from the surface 51a, which is the wafer stacking surface of the support member 51, in the support member peeling step shown in FIG. A release material layer 52, which is a resin layer containing a resin component for facilitating peeling at the time, is formed so as to cover the surface 51a. The release material layer 52 includes a resin component whose physical properties change so that the release material layer 52 can be easily peeled off by applying energy such as ultraviolet rays or light from the outside in the supporting member peeling step shown in FIG. 73. .

  As shown in FIG. 74, the semiconductor pillar WH3 prepared in the second wafer preparation step shown in FIG. 73 does not have the conductor pillar 7p shown in FIG. In the example shown in FIG. 74, a sealing material 6 is formed so as to cover the entire surface 3a of the semiconductor wafer WH3, and each of the plurality of surface electrodes 3ap formed on the surface 3a of the semiconductor wafer WH3 has a sealing material layer. 6 is sealed.

  Next, in the second wafer mounting step shown in FIG. 73, as shown in FIG. 75, the semiconductor wafer WH3 is placed with the surface 51a of the support member 51 and the surface 3a of the semiconductor wafer WH3 facing each other. The support member 51 is bonded and fixed via the sealing material layer 6 and the release material layer 52. FIG. 75 is a cross-sectional view showing a state in which the semiconductor wafer is stacked on the support member in the second wafer mounting step shown in FIG.

  As shown in FIG. 75, in the second wafer mounting step, the semiconductor wafer WH3 is mounted on the surface 51a of the support member 51. Specifically, for example, the semiconductor wafer WH3 shown in FIG. 74 is turned upside down, and the sealing formed on the semiconductor wafer WH3 in a state where the surface 51a of the support member 51 and the surface 3a of the semiconductor wafer WH3 face each other. The release material layer 52 formed on the material layer 6 and the support member 51 is bonded together. In this step, the upper surface 6a of the sealing material layer 6 and the upper surface 52a of the release material layer 52 are brought into close contact with each other and bonded and fixed. Here, as shown in FIG. 75, in the semiconductor wafer WH3, a groove 50tr is formed in advance as in the first embodiment, and the sealing material layer 6 in the dicing region 50b is removed. Accordingly, in the dicing region 50b, a hollow section exists between the semiconductor substrate SS constituting the semiconductor wafer WH3 and the release material layer 52.

  In the present embodiment, the support member 51 is a member that does not eventually form the chip stack MCS (see FIG. 72). Therefore, unlike the first embodiment, in this step, it is not necessary to electrically connect the plurality of conductor pillars 7p formed in each of the plurality of chip formation regions 50a of the semiconductor wafer WH3 to other members.

  Thereafter, a plurality of semiconductor wafers 50 are stacked in the same procedure as the assembly flow shown in FIG. 13 described in the first embodiment. When the fourth wafer back grinding step shown in FIG. 73 is completed, as shown in FIG. 76, each of the plurality of semiconductor wafers WH1, WH2, and WH3 is divided for each chip formation region 50a. FIG. 76 is an enlarged cross-sectional view showing the periphery of the dicing area at the time when the fourth wafer back surface grinding step shown in FIG. 73 is completed.

  73, the physical properties of the resin contained in the release material layer 52 are changed by applying energy to the release material layer 52 shown in FIG. For example, when the release material layer 52 contains an ultraviolet curable resin, the release material layer 52 is irradiated with ultraviolet rays so that the upper surface 52 a of the release material layer 52 and the upper surface 6 a of the sealing material layer 6 are adhered to each other. The interface is easy to peel off. Further, for example, when the release material layer 52 includes a light-to-heat conversion substance that generates heat when irradiated with light, the release material layer 52 and the sealing material layer 6 are irradiated by irradiating the release material layer 52 with light. It is possible to make it easy to peel off by generating bubbles at the close contact interface.

  In each of the second, third, and fourth wafer back surface grinding steps shown in FIG. 73, when the back surface grinding process is performed so as to remove the bottom surface 5trb of the groove 50tr shown in FIG. 75, the dicing area as shown in FIG. The insulating film 3ps made of, for example, silicon oxide remains in 50b. However, since the insulating film 3ps is a very thin film of 1 μm or less, for example, the insulating film 3ps remaining in the dicing region 50b is destroyed when the chip stack MCS is peeled off. However, when the insulating film 3ps is cut, cutting with a dicing blade (not shown) can be performed in a state where the plurality of chip stacked bodies MCS are fixed to the support member 51 shown in FIG. In this case, the insulating film 3ps remaining in the dicing region 50b can be cut more reliably.

  In this embodiment, a silicon substrate in which circuit elements are not formed, and a support member such as a glass substrate as a base material, and an embodiment in which a semiconductor wafer is stacked on the base material to obtain a chip stacked body, Although an example has been described, there are various modifications to the present embodiment. For example, FIG. 73 has been described as a modification to FIG. 13 described in the first embodiment, but can be applied as a modification to FIG. 66 described in the second embodiment. Further, the present invention can be applied in combination with the first modification described in the first embodiment, the second modification, or the second modification described in the second embodiment.

  The manufacturing method of the semiconductor device described in the present embodiment is the same as that of the first embodiment except for the differences described above. Therefore, the overlapping description is omitted.

<Other variations>
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment and the second embodiment, the chip stacked body MCS in which the four memory chips MC1, MC2, MC3, and MC4 are stacked is described as an example. However, the number of stacked semiconductor chips 3 is as follows. It is not limited to four. For example, the minimum unit can be applied to a chip stack MCS in which two semiconductor chips 3 are stacked. For example, although not shown, the present invention can be applied to an embodiment in which more than four semiconductor wafers are stacked.

  Further, for example, in the above-described first to third embodiments, as an example of the chip stacked body MCS in which a plurality of semiconductor chips 3 are stacked, an embodiment in which memory chips having the same planar dimensions are stacked has been described. However, the type of semiconductor chips 3 to be stacked is not limited to the same type. For example, the present invention can be applied to a chip stack in which a plurality of memory chips and logic chips are stacked. However, when multiple semiconductor wafers are stacked, the chipping phenomenon is suppressed when multiple chip stacks are obtained by arranging the dicing regions of each semiconductor wafer to overlap in the thickness direction. Can do. Therefore, from the viewpoint of minimizing the plane area of the logic chip and increasing the number of logic chips that can be obtained from one semiconductor wafer, the logic chip LC is the same as the chip stack MCS as described in the first embodiment. It is preferable to form them separately. In other words, in the chip stacked body preparation step, it is preferable that the same circuit is formed in each of the plurality of chip formation regions of the plurality of stacked semiconductor wafers 50.

  In addition, a part of the contents described in the embodiment will be described below.

A semiconductor device manufacturing method including the following steps:
(A) a first surface, a plurality of first regions provided on the first surface, a second region provided between adjacent first regions of the plurality of first regions, and the first surface Providing a support member having an opposite first back surface;
(B) a second surface, a plurality of chip formation regions provided on the second surface, a cutting region provided between adjacent chip formation regions of the plurality of chip formation regions, and the second surface Preparing a plurality of semiconductor wafers having a second back surface on the opposite side and having a sealing material layer formed in close contact with the second surface including the plurality of chip formation regions and the cutting region;
Here, each of the plurality of chip formation regions of the plurality of semiconductor wafers includes a plurality of pads formed on the second surface, and a plurality of conductor columns respectively formed on the plurality of pads. And
Each of the plurality of conductor columns is covered with the sealing material layer such that a part of each of the plurality of conductor columns is exposed,
Between the second surface and the second back surface, a plurality of internal electrodes respectively connected to the plurality of conductor pillars via the plurality of pads are formed,
(C) The sealing is performed so that the plurality of chip formation regions overlap with the plurality of first regions, the cutting region overlaps with the second region, and the second surface faces the first surface. Laminating the plurality of semiconductor wafers on the first surface side of the support member via a material layer;
Here, in the step (c), the following steps (c1), (c2), and (c3) are repeated a plurality of times,
(C1) bonding one of the plurality of semiconductor wafers on the first surface of the support member via the sealing material layer;
(C2) After the step (c1), grinding the second back surface of one of the plurality of semiconductor wafers to expose each of the plurality of internal electrodes;
(C3) After the step (c1), by moving a first dicing blade to the cutting region, a step of removing a portion formed at a position overlapping one cutting region of the plurality of semiconductor wafers;
(D) After the step (c), the second dicing blade having a width smaller than that of the first dicing blade is caused to travel along the cutting region and the second region, thereby including the plurality of semiconductor wafers. A step of dividing the wafer stack into a plurality of chip stacks.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Wiring board 2a Upper surface (surface, main surface, chip mounting surface)
2b Bottom surface (surface, main surface, mounting surface)
2c Side surface 2d, 2d1 wiring 2d2 via wiring 2e Insulating layer (core layer)
2f Bonding lead (terminal, chip mounting surface side terminal, electrode)
2g Land 2h, 2k Insulating film (solder resist film)
2hw, 2kw Opening 2p1, 2p2 Chip mounting area (chip mounting part)
3 Semiconductor chip 3a surface (main surface, upper surface)
3ap, 3ap1, 3ap2 Surface electrode (electrode, pad)
3b Back surface (main surface, bottom surface)
3bp, 3bp2 Back electrode (electrode, pad)
3c Side surface 3d Wiring layer (wiring layer for semiconductor chip)
3iv Internal electrode 3ps Insulating film 3tsh Hole (hole, opening)
3tsv penetration electrode 4 Sealing body (resin body)
4a Top surface (surface, surface)
4b Bottom surface (surface, back surface)
4c Side 5 Solder ball (external terminal, electrode, external electrode)
6 Sealing material layer (sealed body for chip laminated body, resin body for chip laminated body)
6a Upper surface 6th Through hole 7 Connection material 7b Projection electrode (bump electrode)
7p Conductor column 7s Solder material 20 Wiring board 20a Device region 20b Frame (outer frame)
20c Dicing line (Dicing area)
25 Mask 26 Support base material 27 Protective layer 28 Polishing jig 30 Nozzle 35 Dicing blade (rotary blade)
36 Tape material (dicing tape)
40 Dicing tape 41, 42, 44 Dicing blade 43 Support member 50 Semiconductor wafer 50a Chip formation region 50b Dicing region (cutting region, cutting region, cutting part)
50T, 51T thickness 50tr groove 50trb bottom surface 51 support member 51a front surface 51b back surface 51c first region 51d second region 52 release material layer 52a top surface AS address line (signal line)
CR1, CR2 Core circuit (main circuit)
CU Control circuit DR Power supply circuit (Drive circuit)
DR1 power supply circuit (input / output power supply circuit)
DR2 power supply circuit (core power supply circuit)
DR3 power supply circuit (input / output power supply circuit)
DR4 power supply circuit (core power supply circuit)
DS data line (signal line)
DT1 depth GIF external interface circuit (external input / output circuit)
LC logic chip (semiconductor chip)
MC1, MC2, MC3, MC4 Memory chip (semiconductor chip)
MCS chip stack (stack, memory chip stack, semiconductor chip stack, semiconductor device)
MM main memory circuit (memory circuit)
MR memory area (memory circuit element array area)
NCL, NCL1, NCL2 Adhesive (insulating adhesive)
NIF internal interface circuit (internal input / output circuit)
NS1, NS2 I / O circuit NS2 Core circuit OS Signal line PU Operation processing circuit Rb Diameter SG Signal line SM Auxiliary memory circuit (memory circuit)
SS Semiconductor substrate SSb Back surface (main surface, bottom surface)
SSf Main surface (surface, upper surface)
T1 Thickness Tb Height V1, V2, V3 Power supply lines WB1, WB2 Widths WH1, WH2, WH3, WH4 Semiconductor wafer WHS Wafer stack WT1 Width (cutting width)

Claims (20)

A semiconductor device manufacturing method including the following steps:
(A) A first surface, a plurality of first chip formation regions provided on the first surface, and a first cutting region provided between adjacent first chip formation regions among the plurality of first chip formation regions. And a first sealing material layer having a first back surface opposite to the first surface, and in close contact with the first surface including the plurality of first chip formation regions and the first cutting regions. Preparing a formed first semiconductor wafer;
Here, each of the plurality of first chip formation regions of the first semiconductor wafer includes a plurality of first pads formed on the first surface and a plurality of first pads formed on the plurality of first pads, respectively. 1 conductor pillar, and
Each of the plurality of first conductor columns is covered with the first sealing material layer such that a part of each of the plurality of first conductor columns is exposed,
(B) After the step (a), a step of removing the first sealing material layer disposed at a position overlapping the first cutting region;
(C) a second surface, a plurality of second chip formation regions provided on the second surface, and a second cutting region provided between adjacent second chip formation regions of the plurality of second chip formation regions. And the second sealing material layer has a second back surface opposite to the second surface, and is in close contact with the second surface including the plurality of second chip formation regions and the second cutting regions. Preparing a formed second semiconductor wafer;
Here, each of the plurality of second chip formation regions of the second semiconductor wafer includes a plurality of second pads formed on the second surface and a plurality of second pads formed on the plurality of second pads, respectively. Two conductor pillars,
Each of the plurality of second conductor pillars is covered with the second sealing material layer so that a part of each of the plurality of second conductor pillars is exposed,
Between the second surface and the second back surface, there are formed a plurality of second internal electrodes respectively electrically connected to the plurality of second conductor pillars via the plurality of second pads,
(D) After the step (c), a step of removing the second sealing material layer disposed at a position overlapping with the second cutting region;
(E) The plurality of second chip formation regions respectively overlap with the plurality of first chip formation regions, the second cutting region overlaps with the first cutting region, and the second surface is the first surface. Stacking a second semiconductor wafer on the first semiconductor wafer via the first sealing material layer and the second sealing material layer so as to face each other;
(F) After the step (e), the step of grinding the second back surface of the second semiconductor wafer to expose each of the plurality of second internal electrodes;
(G) A step of dividing the wafer stack including the first and second semiconductor wafers into a plurality of chip stacks after the step (f). In claim 1,
In the step (g),
A method of manufacturing a semiconductor device, wherein a wafer dicing body is divided into a plurality of chip laminated bodies by running a first dicing blade along the first cutting area and the second cutting area. In claim 2,
In the step (b), a second dicing blade having a width wider than the first dicing blade is caused to travel in the first cutting region, so that the first cutting region of the first semiconductor wafer is overlapped with the first cutting region. Removing the first sealing material layer,
In the step (d), the second sealing material layer disposed at a position overlapping the second cutting region of the second semiconductor wafer by moving the second dicing blade to the second cutting region. A method of manufacturing a semiconductor device to be removed. In claim 3,
In the step (b), by moving the second dicing blade to the first cutting region, a part of the first cutting region of the first semiconductor wafer is removed, and the thickness direction of the first semiconductor wafer Forming a first groove having a first bottom surface located between the first surface and the first back surface along
In the step (d), by moving the second dicing blade to the second cutting region, a part of the second cutting region of the second semiconductor wafer is removed, and the thickness direction of the second semiconductor wafer A method of manufacturing a semiconductor device, wherein a second groove having a second bottom surface located between the second front surface and the second back surface is formed along the line. In claim 4,
A method for manufacturing a semiconductor device, further comprising the following steps:
(H) After the step (f) and before the step (g), the step of grinding the first back surface of the first semiconductor wafer to reduce the thickness of the first semiconductor wafer. . In claim 5,
In the step (f), a semiconductor device manufacturing method in which a grinding process is performed until the second bottom surface of the second groove formed in the second semiconductor wafer is removed. In claim 1,
A method for manufacturing a semiconductor device, further comprising the following steps:
(I) After the step (f) and before the step (g), electrically connect to the plurality of second internal electrodes exposed on the second back surface of the second semiconductor wafer. Forming a plurality of protruding electrodes. In claim 7,
In the step (f), a semiconductor device manufacturing method in which a grinding process is performed so as to leave a part of the second cutting region of the second semiconductor wafer. In claim 8,
The method for manufacturing a semiconductor device, wherein the plurality of protruding electrodes formed in the step (i) have a cylindrical shape and a height that is larger than a length of a diameter. In claim 1,
In the step (b), on the first surface side, by running a dicing blade in the first cutting region, the first surface and the first back surface along the thickness direction of the first semiconductor wafer. Forming a first groove having a first bottom surface located therebetween;
In the step (d), a part of the second cutting region of the second semiconductor wafer is removed by running the dicing blade in the second cutting region on the second surface side, and the second semiconductor Forming a second groove having a second bottom surface located between the second surface and the second back surface along the thickness direction of the wafer;
In the step (f), a grinding process is performed until the second bottom surface of the second groove formed in the second semiconductor wafer is removed,
In the step (g), a semiconductor device that divides the wafer stack into the plurality of chip stacks by grinding until the first bottom surface of the first groove formed in the first semiconductor wafer is removed. Manufacturing method. In claim 1,
A method of manufacturing a semiconductor device, wherein the same circuit is formed in each of the plurality of first and second chip formation regions. A semiconductor device manufacturing method including the following steps:
(A) A first surface, a plurality of first chip formation regions provided on the first surface, and a first cutting region provided between adjacent first chip formation regions among the plurality of first chip formation regions. And a first sealing material layer having a first back surface opposite to the first surface, and in close contact with the first surface including the plurality of first chip formation regions and the first cutting regions. Preparing a formed first semiconductor wafer;
Here, each of the plurality of first chip formation regions of the first semiconductor wafer includes a plurality of first pads formed on the first surface and a plurality of first pads formed on the plurality of first pads, respectively. 1 conductor pillar, and
Each of the plurality of first conductor columns is covered with the first sealing material layer such that a part of each of the plurality of first conductor columns is exposed,
(B) a second surface, a plurality of second chip formation regions provided on the second surface, and a second cutting region provided between adjacent second chip formation regions among the plurality of second chip formation regions. And the second sealing material layer has a second back surface opposite to the second surface, and is in close contact with the second surface including the plurality of second chip formation regions and the second cutting regions. Preparing a formed second semiconductor wafer;
Here, each of the plurality of second chip formation regions of the second semiconductor wafer includes a plurality of second pads formed on the second surface and a plurality of second pads formed on the plurality of second pads, respectively. Two conductor pillars,
Each of the plurality of second conductor pillars is covered with the second sealing material layer so that a part of each of the plurality of second conductor pillars is exposed,
Between the second surface and the second back surface, there are formed a plurality of second internal electrodes respectively electrically connected to the plurality of second conductor pillars via the plurality of second pads,
(C) The plurality of second chip formation regions overlap with the plurality of first chip formation regions, respectively, the second cutting region overlaps with the first cutting region, and the second surface becomes the first surface. Stacking a second semiconductor wafer on the first semiconductor wafer via the first sealing material layer and the second sealing material layer so as to face each other;
(D) After the step (c), grinding the second back surface of the second semiconductor wafer to expose each of the plurality of second internal electrodes;
(E) After the step (c), by moving the first dicing blade to the second cutting region, a portion formed in a position overlapping the second cutting region of the second semiconductor wafer. Removing step;
(F) After the step (d) and the step (e), a second dicing blade having a narrower width than the first dicing blade is caused to travel along the first cutting region and the second cutting region. , Dividing the wafer stack including the first and second semiconductor wafers into a plurality of chip stacks. In claim 12,
The step (e) is a method for manufacturing a semiconductor device performed after the step (d). In claim 12,
A method for manufacturing a semiconductor device, further comprising the following steps:
(G) After the steps (d) and (e) and before the step (f), the thickness of the first semiconductor wafer is obtained by grinding the first back surface of the first semiconductor wafer. Thinning process. In claim 12,
A method for manufacturing a semiconductor device, further comprising the following steps:
(H) After the step (d) and before the step (f), electrically connect to the plurality of second internal electrodes exposed on the second back surface of the second semiconductor wafer. Forming a plurality of protruding electrodes. A semiconductor device manufacturing method including the following steps:
(A) a first surface, a plurality of first regions provided on the first surface, a second region provided between adjacent first regions of the plurality of first regions, and the first surface Providing a support member having an opposite first back surface;
(B) a second surface, a plurality of chip formation regions provided on the second surface, a cutting region provided between adjacent chip formation regions of the plurality of chip formation regions, and the second surface Preparing a plurality of semiconductor wafers having a second back surface on the opposite side and having a sealing material layer formed in close contact with the second surface including the plurality of chip formation regions and the cutting region;
Here, each of the plurality of chip formation regions of the plurality of semiconductor wafers includes a plurality of pads formed on the second surface, and a plurality of conductor columns respectively formed on the plurality of pads. And
Each of the plurality of conductor columns is covered with the sealing material layer such that a part of each of the plurality of conductor columns is exposed,
Between the second surface and the second back surface, a plurality of internal electrodes respectively connected to the plurality of conductor pillars via the plurality of pads are formed,
(C) After the step (b), for each of the plurality of semiconductor wafers, a step of removing the sealing material layer disposed at a position overlapping the cutting region;
(D) The sealing so that the plurality of chip formation regions overlap with the plurality of first regions, the cutting region overlaps with the second region, and the second surface faces the first surface. Laminating the plurality of semiconductor wafers on the first surface side of the support member via a material layer;
Here, in the step (d), the following steps (d1) and (d2) are repeated a plurality of times,
(D1) bonding one of the plurality of semiconductor wafers on the first surface of the support member via the sealing material layer;
(D2) After the step (d1), grinding the second back surface of one of the plurality of semiconductor wafers to expose each of the plurality of internal electrodes;
(E) A step of dividing, after the step (d), a wafer laminated body in which the plurality of semiconductor wafers are laminated into a plurality of chip laminated bodies. In claim 16,
In the step (c), for each of the plurality of semiconductor wafers, on the second surface side, a dicing blade is caused to travel to the cutting region, so that the second semiconductor wafer along the thickness direction of the plurality of semiconductor wafers. Forming a first groove having a first bottom surface located between the front surface and the second back surface;
In the step (e), a grinding process is performed until the first bottom surface of the first groove formed in each of the plurality of semiconductor wafers is removed, whereby the wafer stack is attached to the support member. A method of manufacturing a semiconductor device that is separated into a plurality of chip stacks connected via each other. In claim 17,
The first surface of the support member prepared in the step (a) includes a release material layer containing a resin component that facilitates the separation of the support member and the plurality of chip stacks in the step (e). Is glued,
In the step (e), a method of manufacturing a semiconductor device in which the plurality of chip stacks are peeled off from the support member after the release material layer is irradiated with light. In claim 18,
The method for manufacturing a semiconductor device, wherein the support member is a glass substrate or a silicon substrate on which circuit elements are not formed. In claim 16,
(A) In the support member prepared in the step,
A second sealing material layer is formed so as to be in close contact with the first surface including the plurality of first regions and the second region;
Each of the plurality of first regions of the support member includes a plurality of second pads formed on the first surface, and a plurality of second conductor columns formed on the plurality of second pads, respectively. And
Each of the plurality of second conductor pillars is covered with the second sealing material layer so that a part of each of the plurality of second conductor pillars is exposed,
A method for manufacturing a semiconductor device, wherein the second sealing material layer disposed at a position overlapping the second region is removed.

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