CN102063283A - Asynchronous first-in first-out interface, interface operation method and integrated receiver - Google Patents

Asynchronous first-in first-out interface, interface operation method and integrated receiver Download PDF

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CN102063283A
CN102063283A CN 200910221274 CN200910221274A CN102063283A CN 102063283 A CN102063283 A CN 102063283A CN 200910221274 CN200910221274 CN 200910221274 CN 200910221274 A CN200910221274 A CN 200910221274A CN 102063283 A CN102063283 A CN 102063283A
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CN102063283B (en
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陈则朋
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Richwave Technology Corp
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Abstract

An asynchronous FIFO interface having a read clock and a write clock that are asynchronous includes a buffer, a clock controller, a reference source, and a signal source. The buffer receives a digital signal from an analog-to-digital converter according to the write clock and outputs a digital signal to a processor according to the read clock. The clock controller outputs a clock control signal according to the amount of data stored in the buffer. The reference source provides an oscillation frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency and the input frequency to adjust the output read clock, wherein the second integer divisor is controlled by the clock control signal.

Description

异步先进先出接口、接口操作方法和整合式接收器 Asynchronous First-In-First-Out Interfaces, Interface Manipulation Methods, and Integrated Receivers

技术领域technical field

本发明涉及异步先进先出(first in first out，FIFO)接口，特别是涉及射频(radio frequency，RF)装置中的异步FIFO接口。The present invention relates to an asynchronous first in first out (FIFO) interface, in particular to an asynchronous FIFO interface in a radio frequency (radio frequency, RF) device.

背景技术Background technique

随着无线通讯(手机、无线网络)的普及，市场对通讯系统更低价、更低耗能及有更小外型尺寸(form-factor)的射频(radio frequency，RF)收发器的需求日益殷切。最近，模拟收发器、数字处理器及频率产生器已整合至单一芯片上以满足上述需求。在RF收发器中，模拟电路和数字电路对频率的需求是不同的。举例而言，模拟数字转换器(analog-to-digital converter，ADC)和数字模拟转换器(digital-to-analog converter，DAC)在模拟电路中需要低颤动(jitter)时钟以增加数据转换的精确度。然而，在数字电路中，数字处理器却不一定需要低颤动的时钟。With the popularization of wireless communication (mobile phone, wireless network), the market demand for radio frequency (radio frequency, RF) transceivers with lower cost, lower power consumption and smaller form-factor for communication systems is increasing. earnestly. Recently, analog transceivers, digital processors, and frequency generators have been integrated on a single chip to meet the above requirements. In RF transceivers, analog and digital circuits have different frequency requirements. For example, analog-to-digital converters (ADC) and digital-to-analog converters (DAC) require low-jitter clocks in analog circuits to increase the accuracy of data conversion. Spend. However, in digital circuits, digital processors do not necessarily require low-jitter clocks.

有鉴于这个问题，图1的现有电路将ADC和数字处理器之间的时钟独立。图1显示了使用异步先进先出接口120的一接收器100的方块图。接收器100包括一射频前端接收器110、一模拟数字转换器(ADC)112、一第一信号源114、一FIFO缓冲器121、一时钟控制器122、一可变整数除法器124、一基带处理器130、一第二信号源132和一参考源140。In view of this problem, the existing circuit of Fig. 1 separates the clock between the ADC and the digital processor. FIG. 1 shows a block diagram of a receiver 100 using an asynchronous FIFO interface 120 . The receiver 100 includes a radio frequency front-end receiver 110, an analog-to-digital converter (ADC) 112, a first signal source 114, a FIFO buffer 121, a clock controller 122, a variable integer divider 124, a baseband Processor 130 , a second signal source 132 and a reference source 140 .

射频前端接收器110接收由发射器(未显示于图面)所发送的一射频(RF)信号，并且依照第一信号源114所产生的局部信号将该RF信号降频转换成一中频(Intermediate Frequency，IF)信号。该局部信号是由低颤动的第一信号源114所产生以增加信噪比(signal to noise ratio，SNR)且降低当降频转换时的相邻通道阻塞效应。ADC 112将中频讯号转换成数据，并根据局部讯号所产生的可变频率时钟输出数据，用以避免额外低颤动信号源的使用，和满足该低颤动时钟的需求。基带处理器130于该数据上，依照由第二信号源132所产生的第二讯号操作讯号处理功能，例如：传输模式检测、时域数据处理、频域数据处理和信道编码等。第二信号源132为一固定频率信号源，例如一环式振荡器，以降低硬件成本。第二讯号运作成基带处理器130的一时钟。第一信号源114和第二信号源132可共享单一参考源140以进一步降低硬件成本。The RF front-end receiver 110 receives a radio frequency (RF) signal sent by a transmitter (not shown in the figure), and down-converts the RF signal into an intermediate frequency (Intermediate Frequency) according to the local signal generated by the first signal source 114 , IF) signal. The local signal is generated by the low-jitter first signal source 114 to increase the signal-to-noise ratio (SNR) and reduce adjacent channel blocking effects when down-converting. The ADC 112 converts the intermediate frequency signal into data, and outputs the data according to the variable frequency clock generated by the partial signal, so as to avoid the use of an additional low-jitter signal source and meet the requirement of the low-jitter clock. The baseband processor 130 operates signal processing functions on the data according to the second signal generated by the second signal source 132 , such as transmission mode detection, time domain data processing, frequency domain data processing, and channel coding. The second signal source 132 is a fixed frequency signal source, such as a ring oscillator, to reduce hardware cost. The second signal operates as a clock for the baseband processor 130 . The first signal source 114 and the second signal source 132 can share a single reference source 140 to further reduce hardware cost.

由第二信号源132提供到基带处理器130的时钟可与各个信号源所提供到ADC 112的时钟异步。因此在图1的现有电路中采用了一异步FIFO接口120来处理ADC 112与基带处理器130间该异步数据的传递。异步FIFO接口120包括FIFO缓冲器121、时钟控制器122和可变整数除法器124。FIFO缓冲器121耦接于基带处理器130和ADC 112间，缓冲两者间的数据传递。FIFO缓冲器121依照一写入时钟(Write clock)从ADC 112接收数据和依照一读出时钟(Read clock)输出数据至基带处理器130。写入时钟是ADC 112的时钟而读出时钟是基带处理器130的时钟。当ADC 112的写入时钟快于基带处理器130的读出时钟，会造成FIFO缓冲器121数据的溢出，因此时钟控制器122将可变整数除法器124的除数值增加，以降低写入时钟的频率。相反地，ADC 112的写入时钟慢于基带处理器130的读出时钟，会造成FIFO缓冲器121数据的清空，因此时钟控制器122将可变整数除法器124的除数值减少，以提高写入时钟的频率。The clock provided to the baseband processor 130 by the second signal source 132 may be asynchronous to the clocks provided to the ADC 112 by the respective signal sources. Therefore, an asynchronous FIFO interface 120 is adopted in the existing circuit of FIG. 1 to handle the transmission of the asynchronous data between the ADC 112 and the baseband processor 130. The asynchronous FIFO interface 120 includes a FIFO buffer 121 , a clock controller 122 and a variable integer divider 124 . The FIFO buffer 121 is coupled between the baseband processor 130 and the ADC 112 to buffer data transfer between the two. The FIFO buffer 121 receives data from the ADC 112 according to a write clock (Write clock) and outputs data to the baseband processor 130 according to a read clock (Read clock). The write clock is the ADC 112 clock and the read clock is the baseband processor 130 clock. When the write clock of ADC 112 is faster than the read clock of baseband processor 130, it will cause the overflow of FIFO buffer 121 data, so the clock controller 122 will increase the divisor value of variable integer divider 124 to reduce the write clock Frequency of. Conversely, the write clock of the ADC 112 is slower than the read clock of the baseband processor 130, which will cause the FIFO buffer 121 data to be emptied, so the clock controller 122 reduces the divisor value of the variable integer divider 124 to improve the write speed. input clock frequency.

在图1的现有电路中，是通过时钟控制器122调整可变整数除法器124的除数值来控制ADC 112的写入时钟，进而达到控制FIFO缓冲器121的数据状态。然而，FIFO缓冲器121数据状态的控制并不一定非得通过可变整数除法器124来调整。In the existing circuit of FIG. 1 , the clock controller 122 adjusts the divisor value of the variable integer divider 124 to control the write clock of the ADC 112, thereby controlling the data state of the FIFO buffer 121. However, the control of the data state of the FIFO buffer 121 does not necessarily have to be adjusted by the variable integer divider 124 .

发明内容Contents of the invention

有鉴于此，本发明的一实施例揭示一种异步先进先出接口，具有异步的一读出时钟和一写入时钟，包括一FIFO缓冲器、一时钟控制器、一参考源和一信号源。FIFO缓冲器根据写入时钟从一模拟数字转换器接收一数字讯号，以及根据读出时钟输出一数字讯号至一处理器。时钟控制器根据储存于FIFO缓冲器中的数据量输出一时钟控制讯号。参考源提供一震荡频率。信号源将震荡频率除以一第一整数除数以产生一参考频率、将读出时钟除以一第二整数除数以产生一输入频率，以及借着比较参考频率和输入频率来输出一控制信号，用以调整所输出的读出时钟，其中第二整数除数为时钟控制讯号所控制。In view of this, an embodiment of the present invention discloses an asynchronous first-in-first-out interface, which has an asynchronous read clock and a write clock, including a FIFO buffer, a clock controller, a reference source and a signal source . The FIFO buffer receives a digital signal from an analog-to-digital converter according to a write clock, and outputs a digital signal to a processor according to a read clock. The clock controller outputs a clock control signal according to the amount of data stored in the FIFO buffer. The reference source provides an oscillating frequency. the signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency, It is used to adjust the output readout clock, wherein the second integer divisor is controlled by the clock control signal.

此外，本发明的另一实施例揭示一种接口操作方法，用于操作具有一写入时钟和一读出时钟的一异步接口，上述异步接口包括一FIFO缓冲器。上述方法包括根据写入时钟从一模拟数字转换器接收一数字讯号至FIFO缓冲器、根据读出时钟从FIFO缓冲器输出一数字讯号至一处理器、根据储存于FIFO缓冲器中的数据量输出一时钟控制讯号、提供一震荡频率、将震荡频率除以一第一整数除数以产生一参考频率、将读出时钟除以一第二整数除数以产生一输入频率，以及借着比较参考频率和输入频率来调整读出时钟，其中第二整数除数为时钟控制讯号所控制。In addition, another embodiment of the present invention discloses an interface operation method for operating an asynchronous interface having a write clock and a read clock, and the asynchronous interface includes a FIFO buffer. The method includes receiving a digital signal from an analog-to-digital converter to a FIFO buffer according to a write clock, outputting a digital signal from the FIFO buffer to a processor according to a read clock, and outputting a digital signal according to the amount of data stored in the FIFO buffer. a clock control signal, providing an oscillating frequency, dividing the oscillating frequency by a first integer divisor to generate a reference frequency, dividing the read clock by a second integer divisor to generate an input frequency, and by comparing the reference frequency and The input frequency is used to adjust the read clock, wherein the second integer divisor is controlled by the clock control signal.

此外，本发明的另一实施例揭示一种异步先进先出接口，具有异步的一读出时钟和一写入时钟，包括一FIFO缓冲器、一时钟控制器、一参考源和一信号源。FIFO缓冲器根据写入时钟从一模拟数字转换器接收一数字讯号，以及根据读出时钟输出一数字讯号至一处理器。时钟控制器根据储存于FIFO缓冲器中的数据量输出一第一组控制位。参考源提供一震荡频率。信号源将震荡频率除以一第一整数除数以产生一参考频率、将读出时钟除以一第二整数除数以产生一输入频率、借着比较参考频率和输入频率来输出一第二组控制位、将第一组控制位与第二组控制位相加以得到一总控制位，以及根据总控制位调整所输出的读出时钟。In addition, another embodiment of the present invention discloses an asynchronous FIFO interface with a read clock and a write clock asynchronously, including a FIFO buffer, a clock controller, a reference source and a signal source. The FIFO buffer receives a digital signal from an analog-to-digital converter according to a write clock, and outputs a digital signal to a processor according to a read clock. The clock controller outputs a first group of control bits according to the amount of data stored in the FIFO buffer. The reference source provides an oscillating frequency. The signal source divides the oscillating frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a second set of control by comparing the reference frequency with the input frequency bits, adding the first set of control bits and the second set of control bits to obtain a total control bit, and adjusting the output readout clock according to the total control bit.

此外，本发明的另一实施例揭示一种接口操作方法，用于操作具有一写入时钟和一读出时钟的一异步接口，上述异步接口包括一FIFO缓冲器。上述方法包括根据写入时钟从一模拟数字转换器接收一数字讯号至FIFO缓冲器、根据读出时钟从FIFO缓冲器输出一数字讯号至一处理器、根据储存于FIFO缓冲器中的数据量输出一第一组控制位、提供一震荡频率、将震荡频率除以一第一整数除数以产生一参考频率、将读出时钟除以一第二整数除数以产生一输入频率、借着比较参考频率和输入频率来输出一第二组控制位、将第一组控制位与第二组控制位相加以得到一总控制位，以及根据总控制位调整所输出的读出时钟。In addition, another embodiment of the present invention discloses an interface operation method for operating an asynchronous interface having a write clock and a read clock, and the asynchronous interface includes a FIFO buffer. The method includes receiving a digital signal from an analog-to-digital converter to a FIFO buffer according to a write clock, outputting a digital signal from the FIFO buffer to a processor according to a read clock, and outputting a digital signal according to the amount of data stored in the FIFO buffer. A first set of control bits, providing an oscillating frequency, dividing the oscillating frequency by a first integer divisor to generate a reference frequency, dividing the read clock by a second integer divisor to generate an input frequency, by comparing the reference frequency and the input frequency to output a second group of control bits, add the first group of control bits to the second group of control bits to obtain a total control bit, and adjust the output readout clock according to the total control bit.

此外，本发明的另一实施例揭示一种整合式接收器，包括一频率合成器、一时钟系统、一模拟接收路径电路、一低中频转换电路、一处理器和一异步先进先出接口。频率合成器产生一输出信号。时钟系统根据输出信号产生一混合信号以及一写入时钟。模拟接收路径电路根据混合信号产生一低中频讯号。低中频转换电路根据写入时钟将低中频讯号转换成一第一数字讯号。处理器根据一读出时钟处理一第二数字讯号。异步先进先出接口耦接于低中频转换电路和处理器之间，并具有异步的读出时钟和写入时钟，包括一缓冲器、一时钟控制器、一参考源和一信号源。缓冲器根据写入时钟从数字转换电路接收第一数字讯号，以及根据读出时钟输出第二数字讯号至处理器。时钟控制器根据储存于缓冲器中的数据量输出一时钟控制讯号。参考源提供一震荡频率。信号源将震荡频率除以一第一整数除数以产生一参考频率，将读出时钟除以一第二整数除数以产生一输入频率，以及借着比较参考频率和输入频率来输出一控制信号，用以调整所输出的读出时钟，其中第二整数除数为时钟控制讯号所控制。In addition, another embodiment of the present invention discloses an integrated receiver, including a frequency synthesizer, a clock system, an analog receive path circuit, a low-IF conversion circuit, a processor and an asynchronous FIFO interface. The frequency synthesizer generates an output signal. The clock system generates a mixed signal and a writing clock according to the output signal. The analog receive path circuit generates a low intermediate frequency signal from the mixed signal. The low-IF conversion circuit converts the low-IF signal into a first digital signal according to the write clock. The processor processes a second digital signal according to a readout clock. The asynchronous FIFO interface is coupled between the low-IF conversion circuit and the processor, and has asynchronous read clock and write clock, including a buffer, a clock controller, a reference source and a signal source. The buffer receives the first digital signal from the digital conversion circuit according to the write clock, and outputs the second digital signal to the processor according to the read clock. The clock controller outputs a clock control signal according to the amount of data stored in the buffer. The reference source provides an oscillating frequency. the signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency, It is used to adjust the output readout clock, wherein the second integer divisor is controlled by the clock control signal.

此外，本发明的另一实施例揭示一种整合式接收器，包括一频率合成器、一时钟系统、一模拟接收路径电路、一低中频转换电路、一处理器和一异步先进先出接口。频率合成器产生一输出信号。时钟系统根据输出信号产生一混合信号以及一写入时钟。模拟接收路径电路根据混合信号产生一低中频讯号。低中频转换电路根据写入时钟将低中频讯号转换成一第一数字讯号。处理器根据一读出时钟处理一第二数字讯号。异步先进先出接口耦接于低中频转换电路和处理器之间，并具有异步的读出时钟和写入时钟，包括一缓冲器、一时钟控制器、一参考源和一信号源。缓冲器根据写入时钟从数字转换电路接收第一数字讯号，以及根据读出时钟输出第二数字讯号至处理器。时钟控制器根据储存于缓冲器中的数据量输出一第一组控制位。参考源提供一震荡频率。信号源将震荡频率除以一第一整数除数以产生一参考频率，将读出时钟除以一第二整数除数以产生一输入频率，借着比较参考频率和输入频率来输出一第二组控制位，将第一组控制位与第二组控制位相加以得到一总控制位，以及根据总控制位调整所输出的读出时钟。In addition, another embodiment of the present invention discloses an integrated receiver, including a frequency synthesizer, a clock system, an analog receive path circuit, a low-IF conversion circuit, a processor and an asynchronous FIFO interface. The frequency synthesizer generates an output signal. The clock system generates a mixed signal and a writing clock according to the output signal. The analog receive path circuit generates a low intermediate frequency signal from the mixed signal. The low-IF conversion circuit converts the low-IF signal into a first digital signal according to the write clock. The processor processes a second digital signal according to a readout clock. The asynchronous FIFO interface is coupled between the low-IF conversion circuit and the processor, and has asynchronous read clock and write clock, including a buffer, a clock controller, a reference source and a signal source. The buffer receives the first digital signal from the digital conversion circuit according to the write clock, and outputs the second digital signal to the processor according to the read clock. The clock controller outputs a first group of control bits according to the amount of data stored in the buffer. The reference source provides an oscillating frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a second set of control by comparing the reference frequency and the input frequency bits, adding the first set of control bits and the second set of control bits to obtain a total control bit, and adjusting the output readout clock according to the total control bit.

附图说明Description of drawings

图1显示使用异步先进先出接口的一接收器的方块图；Figure 1 shows a block diagram of a receiver using an asynchronous FIFO interface;

图2显示根据本发明一实施例所述的使用异步先进先出接口的一接收器的方块图；FIG. 2 shows a block diagram of a receiver using an asynchronous FIFO interface according to an embodiment of the present invention;

图3A显示根据本发明一实施例所述的一第二信号源的方块图；FIG. 3A shows a block diagram of a second signal source according to an embodiment of the present invention;

图3B显示根据本发明另一实施例所述的第二信号源的方块图；FIG. 3B shows a block diagram of a second signal source according to another embodiment of the present invention;

图4A显示根据本发明一实施例所述的FIFO缓冲器中数据量递减的示意图；FIG. 4A shows a schematic diagram of decreasing the amount of data in the FIFO buffer according to an embodiment of the present invention;

图4B显示根据本发明一实施例所述的FIFO缓冲器中数据量递增的示意图；FIG. 4B shows a schematic diagram of increasing the amount of data in the FIFO buffer according to an embodiment of the present invention;

图5显示本发明一实施例所述的接口操作方法；Fig. 5 shows the interface operation method described in an embodiment of the present invention;

图6显示本发明另一实施例所述的接口操作方法；Fig. 6 shows the interface operation method described in another embodiment of the present invention;

图7显示根据本发明一实施例所述的接收器于实际应用的电路图；FIG. 7 shows a circuit diagram of a practical application of the receiver according to an embodiment of the present invention;

图8A显示一整合式接收器的电路图；以及Figure 8A shows a circuit diagram of an integrated receiver; and

图8B显示本发明的异步先进先出接口应用于图8A的整合式接收器的范例。FIG. 8B shows an example of applying the asynchronous FIFO interface of the present invention to the integrated receiver of FIG. 8A .

附图符号说明Description of reference symbols

100、200～接收器        102～低噪声放大器100, 200～receiver 102～low noise amplifier

104～混合器             106～低中频转换电路104～mixer 106～low-intermediate frequency conversion circuit

108～数字讯号处理器     110～射频前端接收器108～digital signal processor 110～RF front-end receiver

112～模拟数字转换器     113～射频讯号112～analog-to-digital converter 113～radio frequency signal

114、132、132A、132B～信号源114, 132, 132A, 132B～signal source

116～低中频讯号         121、221～FIFO缓冲器116～low intermediate frequency signal 121, 221～FIFO buffer

120、220～异步FIFO接口120, 220～asynchronous FIFO interface

120A、120B～数字讯号    122～时钟控制器120A, 120B～digital signal 122～clock controller

124～可变整数除法器     130～基带处理器124～variable integer divider 130～baseband processor

132、204、1325～除法器  140～参考源132, 204, 1325～divider 140～reference source

150～喇叭               209～频率合成器150～speaker 209～frequency synthesizer

212～数字模拟转换器     224～固定除法器212～digital-to-analog converter 224～fixed divider

300～时钟系统300～clock system

410、412、414、420、422、424～缓冲器410, 412, 414, 420, 422, 424～buffer

800A、800B～整合式接收器800A, 800B～integrated receiver

1321～可变整数除法器1321～variable integer divider

1322～相位频率检测器/电荷泵浦1322～phase frequency detector/charge pump

1323～回路滤波器        1324～电压控制震荡器1323～Loop Filter 1324～Voltage Controlled Oscillator

CLK_BB1、CLK_BB2～时钟频率CLK_BB1, CLK_BB2～clock frequency

fOSC～频率合成器的输出频率f OSC ~ the output frequency of the frequency synthesizer

fxtal～震荡频率                Fin1、Fin2～输入频率f xtal ～oscillation frequency F in1 、 F in2 ～input frequency

Fref1、Fref2～参考频率         FIFO_R～读取数据F ref1 , F ref2 ~ reference frequency FIFO_R ~ read data

FIFO_W～写入数据FIFO_W～write data

具体实施方式Detailed ways

为使本发明的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并结合附图详细说明如下。In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

图2显示根据本发明一实施例所述的使用异步先进先出接口的一接收器200的方块图。接收器200包括一射频前端接收器110、一模拟数字转换器112、一第一信号源114、一FIFO缓冲器121、一时钟控制器122、一可变整数除法器124、一基带处理器130、一第二信号源132和一参考源140。与图1现有架构相同的是，本实施例中亦采用了一异步FIFO接口220来处理ADC 112与基带处理器130间的异步数据传送。与图1的现有架构不同的是，异步FIFO接口220包括FIFO缓冲器121、时钟控制器122、第二信号源132和参考源140。FIFO缓冲器121耦接于基带处理器130和ADC 112间，缓冲两者间的数据传递。FIFO缓冲器121依照一写入时钟从ADC 112接收数据和依照一读出时钟输出数据至基带处理器130。写入时钟是ADC112的时钟而读出时钟是基带处理器130的时钟。当基带处理器130的读出时钟慢于ADC 112的写入时钟，会造成FIFO缓冲器121数据的溢出，因此时钟控制器122将第二信号源132输出的读出时钟的频率增加，以便增加基带处理器130的读出时钟。相反地，当基带处理器130的读出时钟快于ADC 112的写入时钟，会造成FIFO缓冲器121数据的清空，因此时钟控制器122将第二信号源132输出的读出时钟的频率降低，以便降低基带处理器130的读出时钟。借着控制第二信号源132的输出读出时钟的方式，可保持与ADC 112的写入时钟的平衡而不会使得FIFO缓冲器121的数据溢出或清空。以上为本发明概略的叙述，其详细的实施细节描述如下。FIG. 2 shows a block diagram of a receiver 200 using an asynchronous FIFO interface according to an embodiment of the invention. The receiver 200 includes a radio frequency front-end receiver 110, an analog-to-digital converter 112, a first signal source 114, a FIFO buffer 121, a clock controller 122, a variable integer divider 124, a baseband processor 130 , a second signal source 132 and a reference source 140 . Similar to the existing architecture in FIG. 1 , an asynchronous FIFO interface 220 is also used in this embodiment to handle the asynchronous data transmission between the ADC 112 and the baseband processor 130 . Different from the existing architecture in FIG. 1 , the asynchronous FIFO interface 220 includes a FIFO buffer 121 , a clock controller 122 , a second signal source 132 and a reference source 140 . The FIFO buffer 121 is coupled between the baseband processor 130 and the ADC 112 to buffer data transfer between the two. The FIFO buffer 121 receives data from the ADC 112 according to a write clock and outputs data to the baseband processor 130 according to a read clock. The write clock is the ADC 112 clock and the read clock is the baseband processor 130 clock. When the read clock of the baseband processor 130 is slower than the write clock of the ADC 112, the FIFO buffer 121 data will overflow, so the clock controller 122 increases the frequency of the read clock output by the second signal source 132, so as to increase Readout clock for baseband processor 130 . Conversely, when the read clock of the baseband processor 130 is faster than the write clock of the ADC 112, the FIFO buffer 121 data will be emptied, so the clock controller 122 reduces the frequency of the read clock output by the second signal source 132 , so as to reduce the read clock of the baseband processor 130 . By controlling the output read clock of the second signal source 132, the balance with the write clock of the ADC 112 can be maintained without overflowing or emptying the data of the FIFO buffer 121. The above is a general description of the present invention, and its detailed implementation details are described as follows.

图3A显示根据本发明一实施例所述的第二信号源的方块图。第二信号源132A可以是一合成器(Synthesizer)，包括一可变整数除法器1321、一相位频率检测器/电荷泵浦(Phase Frequency Detector/Charge Pump，PFD/CP)1322、一回路滤波器(loop filter)1323、一电压控制震荡器(Voltage-ControlledOscillator，VCO)1324和一除法器1325。在图3A中，时钟频率CLK_BB1是提供至基带处理器130的时钟，而FIFO缓冲器121是依照该时钟频率CLK_BB1输出数据至基带处理器130。因此，当FIFO缓冲器121中的数据状态不平衡(数据过满或清空)时，可调整时钟频率CLK_BB1的大小。在图3A中，可变整数除法器1321具有将基带处理器130的时钟频率CLK_BB1除以一整数M的功能，其中M的值是由时钟控制器122决定。可变整数除法器1321将基带处理器130的时钟频率CLK_BB1除以整数M之后，所输出的频率(CLK_BB1/M)传送至PFD/CP 1322当成其输入频率fin1。另一方面，除法器1325接收参考源140的震荡频率fxtal，并将其除以一整数值N以输出参考频率fref1。参考源140的震荡频率fxtal可以是由一晶体震荡器(Crystal)产生。PFD/CP 1322接收输入频率fin1和参考频率fref1，检测/比较两者之间的差异量并送出结果给回路滤波器1323，回路滤波器1323再送出控制讯号给VCO 1324，使得VCO 1324调整其所输出的时钟频率CLK_BB1。当时钟频率CLK_BB1的频率稳定时，其值为参考源140震荡频率fxtal的(M/N)倍。时钟控制器122可根据FIFO缓冲器121的时钟数据状态调整可变整数除法器1321的除数值(M)大小，进而调整VCO 1324输出至基带处理器130的时钟频率CLK_BB1。举例来说，当储存于FIFO缓冲器121中的数据量高于一上限值时，代表FIFO缓冲器121中的数据量可能到达过满的状态，因此时钟控制器122可调整可变整数除法器1321的除数值(M)大小来增加时钟频率CLK_BB1。如此一来，FIFO缓冲器121便依照增加的时钟频率CLK_BB1输出数据至基带处理器130，提升基带处理器130从FIFO缓冲器121读取数据的速度。其中，增加后的时钟频率CLK_BB1可大于ADC 112写入FIFO缓冲器121的速度，以解决FIFO缓冲器121中数据过满的情况。同样地，当储存于FIFO缓冲器121中的数据量低于一下限值时，代表FIFO缓冲器121中的数据量可能到达过清空状态，因此时钟控制器122可调整可变整数除法器1321的除数值(M)大小来降低时钟频率CLK_BB1。如此一来，FIFO缓冲器121便依照降低的时钟频率CLK_BB1输出数据至基带处理器130，减少基带处理器130从FIFO缓冲器121读取数据的速度。其中，降低后的时钟频率CLK_BB1可小于ADC 112写入FIFO缓冲器121的速度，以解决FIFO缓冲器121中数据清空的情况。值得注意的是，虽然以上的实施例提到时钟控制器122根据FIFO缓冲器121的数据状态调整可变整数除法器1321的除数值(M)大小，进而调整VCO 1324输出至基带处理器130的时钟频率CLK_BB1，然而，在本发明另一实施例中，可变整数除法器1321的除数值(M)大小亦可由基带处理器130根据目前的数据处理状况来决定。亦即，基带处理器130亦可通过时钟控制器122自行调整其时钟频率。FIG. 3A shows a block diagram of a second signal source according to an embodiment of the invention. The second signal source 132A can be a synthesizer (Synthesizer), including a variable integer divider 1321, a phase frequency detector/charge pump (Phase Frequency Detector/Charge Pump, PFD/CP) 1322, a loop filter (loop filter) 1323 , a voltage-controlled oscillator (Voltage-Controlled Oscillator, VCO) 1324 and a divider 1325 . In FIG. 3A , the clock frequency CLK_BB1 is provided to the baseband processor 130 , and the FIFO buffer 121 outputs data to the baseband processor 130 according to the clock frequency CLK_BB1 . Therefore, when the data state in the FIFO buffer 121 is unbalanced (data is too full or empty), the clock frequency CLK_BB1 can be adjusted. In FIG. 3A , the variable integer divider 1321 has the function of dividing the clock frequency CLK_BB1 of the baseband processor 130 by an integer M, where the value of M is determined by the clock controller 122 . After the variable integer divider 1321 divides the clock frequency CLK_BB1 of the baseband processor 130 by an integer M, the output frequency (CLK_BB1/M) is sent to the PFD/CP 1322 as its input frequency f in1 . On the other hand, the divider 1325 receives the oscillating frequency f xtal of the reference source 140 and divides it by an integer value N to output the reference frequency f ref1 . The oscillation frequency f xtal of the reference source 140 may be generated by a crystal oscillator (Crystal). The PFD/CP 1322 receives the input frequency f in1 and the reference frequency f ref1 , detects/compares the difference between them and sends the result to the loop filter 1323, and the loop filter 1323 then sends a control signal to the VCO 1324 to make the VCO 1324 adjust Its output clock frequency CLK_BB1. When the frequency of the clock frequency CLK_BB1 is stable, its value is (M/N) times the oscillation frequency f xtal of the reference source 140 . The clock controller 122 can adjust the divisor value (M) of the variable integer divider 1321 according to the clock data status of the FIFO buffer 121 , and then adjust the clock frequency CLK_BB1 output from the VCO 1324 to the baseband processor 130 . For example, when the amount of data stored in the FIFO buffer 121 is higher than an upper limit, it means that the amount of data in the FIFO buffer 121 may reach an overfull state, so the clock controller 122 can adjust the variable integer division The divisor value (M) of the device 1321 is used to increase the clock frequency CLK_BB1. In this way, the FIFO buffer 121 outputs data to the baseband processor 130 according to the increased clock frequency CLK_BB1 , so as to increase the speed at which the baseband processor 130 reads data from the FIFO buffer 121 . Wherein, the increased clock frequency CLK_BB1 may be greater than the speed at which the ADC 112 writes into the FIFO buffer 121 , so as to solve the situation that the data in the FIFO buffer 121 is too full. Similarly, when the amount of data stored in the FIFO buffer 121 is lower than the lower limit, it means that the amount of data in the FIFO buffer 121 may have reached an over-empty state, so the clock controller 122 can adjust the variable integer divider 1321 The divisor value (M) is used to reduce the clock frequency CLK_BB1. In this way, the FIFO buffer 121 outputs data to the baseband processor 130 according to the reduced clock frequency CLK_BB1 , reducing the speed at which the baseband processor 130 reads data from the FIFO buffer 121 . Wherein, the reduced clock frequency CLK_BB1 may be lower than the speed at which the ADC 112 writes into the FIFO buffer 121 , so as to solve the situation that the data in the FIFO buffer 121 is empty. It is worth noting that although the above embodiments mentioned that the clock controller 122 adjusts the divisor value (M) of the variable integer divider 1321 according to the data state of the FIFO buffer 121, and then adjusts the output of the VCO 1324 to the baseband processor 130. The clock frequency CLK_BB1, however, in another embodiment of the present invention, the divisor value (M) of the variable integer divider 1321 can also be determined by the baseband processor 130 according to the current data processing status. That is, the baseband processor 130 can also adjust its clock frequency by itself through the clock controller 122 .

图3B显示根据本发明另一实施例所述的第二信号源的方块图。第二信号源132B可以是一合成器(Synthesizer)，包括一除法器1421、一相位频率检测器(Phase Frequency Detector，PFD)1422、一数字回路滤波器1423、一加法器1424、一数字电压控制震荡器(Digital Voltage-Controlled Oscillator，DCO)1425和一除法器1426。与图3A的实施例相同，时钟频率CLK_BB2是基带处理器130的时钟，而FIFO缓冲器121是依照该时钟频率CLK_BB2输出数据至基带处理器130。因此，当FIFO缓冲器121中的数据状态不平衡(数据过满或清空)时，可调整时钟频率CLK_BB2的大小。然而，与图3A的实施例不同的是，图3B第二信号源的实施架构属于数字的方式，如下所述。在图3B中，除法器1421具有将基带处理器130的时钟频率CLK_BB2分频的功能，将所输出的频率送至PFD 1422作为其输入频率fin2。此外，除法器1426接收参考源140的震荡频率fxtal，并将其分频以输出参考频率fref2。参考源140的震荡频率fxtal可以是由一晶体震荡器产生。PFD 1422接收输入频率fin2和参考频率fref2，检测/比较两者之间的差异量并送出结果给数字回路滤波器1423，数字回路滤波器1423再送出一组控制位(control bits)给加法器1424。加法器1424亦接收时钟控制器122所输出的另一组控制位，并将两组控制位相加输出一总控制位给DCO 1425，使得DCO 1425调整其输出至基带处理器130的时钟频率CLK_BB2。举例来说，当储存于FIFO缓冲器121中的数据量高于一上限值时，代表FIFO缓冲器121中的数据量可能到达过满的状态，因此时钟控制器122可调整其输出的控制位的值(例如给予较大的控制位的值)来增加时钟频率CLK_BB2。如此一来，FIFO缓冲器121便依照增加的时钟频率CLK_BB2输出数据至基带处理器130，提升基带处理器130从FIFO缓冲器121读取数据的速度。其中，增加后的时钟频率CLK_BB2可大于ADC 112写入FIFO缓冲器121的速度，以解决FIFO缓冲器121中数据过满的情况。同样地，当储存于FIFO缓冲器121中的数据量低于一下限值时，代表FIFO缓冲器121中的数据量可能到达过清空状态，因此时钟控制器122可调整其输出的控制位的值(例如给予较小的控制位的值)来降低时钟频率CLK_BB2。如此一来，FIFO缓冲器121便依照降低的时钟频率CLK_BB2输出数据至基带处理器130，减少基带处理器130从FIFO缓冲器121读取数据的速度。其中，降低后的时钟频率CLK_BB2可小于ADC 112写入FIFO缓冲器121的速度，以解决FIFO缓冲器121中数据清空的情况。与图3A的实施例相同，时钟控制器122所输出的控制位的值亦可由基带处理器130根据目前的数据处理状况来决定。亦即，基带处理器130亦可通过时钟控制器122自行调整其时钟频率。必须注意的是，在此实施例中，只有在电路初始状态时才需要使用到数字回路滤波器1423的输出值，而在之后的操作中将数字回路滤波器1423的值闩锁住不再变动。取而代的的是，时钟控制器122根据FIFO缓冲器121的数据状态调整其所输出的控制位的值，进而调整总控制位的值。如此一来，DCO 1425可根据总控制位动态地调整其输出至基带处理器130的时钟频率CLK_BB2。更具体地说，当FIFO缓冲器121的数据状态为接近数据溢出时(数据超过上限值)，时钟控制器122可输出正的第二控制位的值，使得加法器1424输出较大的总控制位给DCO 1425，进而使DCO 1425提高其输出的时钟频率CLK_BB2。相反地，当FIFO缓冲器121的数据状态为接近数据清空时(数据低于下限值)，时钟控制器122可输出负的第二控制位的值，使得加法器1424输出较小的总控制位给DCO 1425，进而使DCO 1425降低其输出的时钟频率CLK_BB2。在以上两个实施例中，提到了FIFO缓冲器121中数据过满或清空的情况，以下将概略叙述FIFO缓冲器121中数据递增或递减的状态。FIG. 3B shows a block diagram of a second signal source according to another embodiment of the invention. The second signal source 132B can be a synthesizer (Synthesizer), including a divider 1421, a phase frequency detector (Phase Frequency Detector, PFD) 1422, a digital loop filter 1423, an adder 1424, a digital voltage control An oscillator (Digital Voltage-Controlled Oscillator, DCO) 1425 and a divider 1426 . Same as the embodiment in FIG. 3A , the clock frequency CLK_BB2 is the clock of the baseband processor 130 , and the FIFO buffer 121 outputs data to the baseband processor 130 according to the clock frequency CLK_BB2 . Therefore, when the state of data in the FIFO buffer 121 is unbalanced (data is too full or empty), the clock frequency CLK_BB2 can be adjusted. However, different from the embodiment in FIG. 3A , the implementation structure of the second signal source in FIG. 3B is digital, as described below. In FIG. 3B , the divider 1421 has the function of dividing the clock frequency CLK_BB2 of the baseband processor 130 , and sends the output frequency to the PFD 1422 as its input frequency fin2 . In addition, the divider 1426 receives the oscillating frequency f xtal of the reference source 140 and divides it to output the reference frequency f ref2 . The oscillation frequency f xtal of the reference source 140 can be generated by a crystal oscillator. The PFD 1422 receives the input frequency f in2 and the reference frequency f ref2 , detects/compares the difference between them and sends the result to the digital loop filter 1423, and the digital loop filter 1423 sends a set of control bits to the addition device 1424. The adder 1424 also receives another group of control bits output by the clock controller 122, and adds the two groups of control bits to output a total control bit to the DCO 1425, so that the DCO 1425 adjusts the clock frequency CLK_BB2 output to the baseband processor 130 . For example, when the amount of data stored in the FIFO buffer 121 is higher than an upper limit, it means that the amount of data in the FIFO buffer 121 may reach an overfull state, so the clock controller 122 can adjust its output control bit value (for example, give a larger control bit value) to increase the clock frequency CLK_BB2. In this way, the FIFO buffer 121 outputs data to the baseband processor 130 according to the increased clock frequency CLK_BB2 , so that the speed at which the baseband processor 130 reads data from the FIFO buffer 121 is increased. Wherein, the increased clock frequency CLK_BB2 may be greater than the speed at which the ADC 112 writes into the FIFO buffer 121 , so as to solve the situation that the data in the FIFO buffer 121 is too full. Similarly, when the amount of data stored in the FIFO buffer 121 is lower than the lower limit, it means that the amount of data in the FIFO buffer 121 may have reached an over-empty state, so the clock controller 122 can adjust the value of its output control bit (for example, give a smaller control bit value) to reduce the clock frequency CLK_BB2. In this way, the FIFO buffer 121 outputs data to the baseband processor 130 according to the reduced clock frequency CLK_BB2 , reducing the speed at which the baseband processor 130 reads data from the FIFO buffer 121 . Wherein, the reduced clock frequency CLK_BB2 may be lower than the speed at which the ADC 112 writes into the FIFO buffer 121 , so as to solve the situation that the data in the FIFO buffer 121 is empty. Same as the embodiment in FIG. 3A , the value of the control bit output by the clock controller 122 can also be determined by the baseband processor 130 according to the current data processing status. That is, the baseband processor 130 can also adjust its clock frequency by itself through the clock controller 122 . It must be noted that in this embodiment, the output value of the digital loop filter 1423 is only used in the initial state of the circuit, and the value of the digital loop filter 1423 is latched in subsequent operations and will not change . Instead, the clock controller 122 adjusts the value of the control bit output by it according to the data state of the FIFO buffer 121 , and then adjusts the value of the overall control bit. In this way, the DCO 1425 can dynamically adjust the clock frequency CLK_BB2 output to the baseband processor 130 according to the overall control bit. More specifically, when the data state of the FIFO buffer 121 is close to data overflow (the data exceeds the upper limit), the clock controller 122 can output the value of the positive second control bit, so that the adder 1424 outputs a larger total The control bit is given to DCO 1425, which in turn causes DCO 1425 to increase its output clock frequency CLK_BB2. Conversely, when the data state of the FIFO buffer 121 is close to data empty (data is lower than the lower limit value), the clock controller 122 can output a negative value of the second control bit, so that the adder 1424 outputs a smaller total control bit bit to the DCO 1425, which in turn causes the DCO 1425 to reduce its output clock frequency CLK_BB2. In the above two embodiments, the situation that the data in the FIFO buffer 121 is too full or empty is mentioned, and the state of incrementing or decrementing the data in the FIFO buffer 121 will be briefly described below.

图4A表示该FIFO缓冲器121中的数据量递减。举例而言，写入时钟的频率为4/T而读出时钟的频率为5/T。该FIFO缓冲器的读出速度较该FIFO缓冲器121的写入时钟快，因此该数据量在每个T期间内皆会递减。参考图4A，FIFO_R表示该FIFO缓冲器121于此区域读出数据，FIFO_W表示该FIFO缓冲器121于此区域写入数据，而黑点表示该数据储存于缓冲器。410表示于to时的该FIFO缓冲器121，412表示于to+T时的该FIFO缓冲器121，而414表示于to+2T时的FIFO缓冲器121。当该数据量降至下限的下时，则FIFO缓冲器的空讯号会被拉高而于下个期间发送「发生错误」(errorhappened)讯息。FIG. 4A shows that the amount of data in the FIFO buffer 121 is decremented. For example, the frequency of the write clock is 4/T and the frequency of the read clock is 5/T. The reading speed of the FIFO buffer is faster than the writing clock of the FIFO buffer 121 , so the data amount decreases every T period. Referring to FIG. 4A , FIFO_R indicates that the FIFO buffer 121 reads data in this area, FIFO_W indicates that the FIFO buffer 121 writes data in this area, and black dots indicate that the data is stored in the buffer. 410 represents the FIFO buffer 121 at t o , 412 represents the FIFO buffer 121 at t o +T, and 414 represents the FIFO buffer 121 at t o +2T. When the amount of data falls below the lower limit, the empty signal of the FIFO buffer will be pulled high and an "error happened" message will be sent in the next period.

图4B表示该FIFO缓冲器121内的数据量递增。举例而言，写入时钟的频率为6/T读出时钟的频率为5/T。该数据量在每个T期间内皆会递增。参照图4B，420表示于t1时的该FIFO缓冲器121，422表示于t1+T时的该FIFO缓冲器121，而424表示于t1+4T时的FIFO缓冲器121。当该数据量超出上限的上时，则FIFO缓冲器的满讯号会被拉高而于下个期间发送「发生错误」讯息。FIG. 4B shows that the amount of data in the FIFO buffer 121 increases. For example, the frequency of the write clock is 6/T and the frequency of the read clock is 5/T. The amount of data will increase every T period. Referring to FIG. 4B , 420 represents the FIFO buffer 121 at t 1 , 422 represents the FIFO buffer 121 at t 1 +T, and 424 represents the FIFO buffer 121 at t 1 +4T. When the amount of data exceeds the upper limit, the full signal of the FIFO buffer will be pulled high and an "error occurred" message will be sent in the next period.

如上所述，当该读出时钟和该写入时钟异步，该FIFO缓冲器会遭遇到过满或过空的问题而导致数据传递错误。然而，其可用控制该读出时钟的频率的方式避免。图5显示本发明一实施例所述的接口操作方法，用于操作图2所示的具有一写入时钟和一读出时钟的异步FIFO接口220，并结合使用图3A所述的第二信号源132A。首先，在步骤S50中，根据写入时钟从ADC 112接收一数字讯号至FIFO缓冲器121。在步骤S51中，根据读出时钟从FIFO缓冲器121输出一数字讯号至基带处理器130。在步骤S52中，由参考源140提供一震荡频率fxtal。在步骤S53中，图3A中的除法器1325将震荡频率除以第一整数除数N以产生一参考频率fref1。在步骤S54中，图3A中的可变整数除法器1321将读出时钟除以一第二整数除数M以产生一输入频率fin1。在步骤S55中，相位频率检测器/电荷泵浦1322比较参考频率fref1和输入频率fin1，而回路滤波器1323根据比较结果输出一控制讯号。在步骤S56中，图3A中的电压控制震荡器1324根据控制讯号调整所输出的读出时钟。在图5的流程图中，第二整数除数M为时钟控制讯号所控制，亦即，当读出时钟过低造成异步FIFO接口220数据过满时，即调整第二整数除数M的值，以便增加读出时钟的频率，反之亦然。As mentioned above, when the read clock and the write clock are asynchronous, the FIFO buffer may encounter overfull or overempty problems resulting in data transfer errors. However, it can be avoided by controlling the frequency of the readout clock. FIG. 5 shows an interface operation method according to an embodiment of the present invention, which is used to operate the asynchronous FIFO interface 220 shown in FIG. 2 with a write clock and a read clock, and uses the second signal described in FIG. 3A in combination source 132A. First, in step S50, a digital signal is received from the ADC 112 to the FIFO buffer 121 according to the write clock. In step S51 , output a digital signal from the FIFO buffer 121 to the baseband processor 130 according to the read clock. In step S52 , an oscillating frequency f xtal is provided by the reference source 140 . In step S53 , the divider 1325 in FIG. 3A divides the oscillating frequency by the first integer divisor N to generate a reference frequency f ref1 . In step S54 , the variable integer divider 1321 in FIG. 3A divides the read clock by a second integer divisor M to generate an input frequency fin1 . In step S55 , the phase frequency detector/charge pump 1322 compares the reference frequency f ref1 with the input frequency f in1 , and the loop filter 1323 outputs a control signal according to the comparison result. In step S56 , the VCO 1324 in FIG. 3A adjusts the output readout clock according to the control signal. In the flowchart of FIG. 5, the second integer divisor M is controlled by the clock control signal, that is, when the read clock is too low and the asynchronous FIFO interface 220 data is too full, the value of the second integer divisor M is adjusted so that Increase the frequency of the readout clock and vice versa.

图6显示本发明另一实施例所述的接口操作方法，用于操作图2所示的具有一写入时钟和一读出时钟的异步FIFO接口220，并结合使用图3B所述的第二信号源132B。首先，在步骤S60中，根据写入时钟从ADC 112接收一数字讯号至FIFO缓冲器121。在步骤S61中，根据读出时钟从FIFO缓冲器121输出一数字讯号至一基带处理器130。在步骤S62中，根据储存于FIFO缓冲器121中的数据量输出第一组控制位。在步骤S63中，由参考源提供一震荡频率fxtal。在步骤S64中，图3B的除法器1426将震荡频率fxtal除以一第一整数除数以产生一参考频率fref2。在步骤S65中，图3B的除法器1421将读出时钟除以一第二整数除数以产生一输入频率fin2。在步骤S66中，比较参考频率fref2和输入频率fin2。在步骤S67中，根据比较结果输出一第二组控制位。在步骤S68中，图3B的加法器1424将第一组控制位与第二组控制位相加以得到一总控制位。在步骤S69中，图3B的数字电压控制震荡器1425将根据总控制位调整所输出的读出时钟。更精确地说，当FIFO缓冲器121接近数据清空的状态时，步骤S62中所输出的第一组控制位可为负，使得相加后的总控制位变小而降低所输出的读出时钟。相反地，当FIFO缓冲器121接近数据溢出的状态时，步骤S62中所输出的第一组控制位可为正，使得相加后的总控制位变大而增加所输出的读出时钟。FIG. 6 shows an interface operation method according to another embodiment of the present invention, which is used to operate the asynchronous FIFO interface 220 shown in FIG. 2 with a write clock and a read clock, and uses the second described in FIG. Signal source 132B. First, in step S60, a digital signal is received from the ADC 112 to the FIFO buffer 121 according to the write clock. In step S61 , output a digital signal from the FIFO buffer 121 to a baseband processor 130 according to the read clock. In step S62 , a first group of control bits is output according to the amount of data stored in the FIFO buffer 121 . In step S63, an oscillating frequency f xtal is provided by a reference source. In step S64 , the divider 1426 of FIG. 3B divides the oscillation frequency f xtal by a first integer divisor to generate a reference frequency f ref2 . In step S65 , the divider 1421 of FIG. 3B divides the read clock by a second integer divisor to generate an input frequency fin2 . In step S66, the reference frequency f ref2 is compared with the input frequency f in2 . In step S67, a second group of control bits is output according to the comparison result. In step S68, the adder 1424 of FIG. 3B adds the first set of control bits to the second set of control bits to obtain a total control bit. In step S69 , the digital voltage controlled oscillator 1425 of FIG. 3B adjusts the output readout clock according to the overall control bit. More precisely, when the FIFO buffer 121 is close to the state of data emptying, the first set of control bits output in step S62 can be negative, so that the total control bits after the addition become smaller and the output readout clock is reduced. . On the contrary, when the FIFO buffer 121 is close to the state of data overflow, the first set of control bits output in step S62 may be positive, so that the total control bits after the addition become larger to increase the output readout clock.

此外，虽然本发明的实施例中揭示的是根据FIFO缓冲器121中的数据量状态，使得时钟控制器122作相对应的调整动作，然而，在本发明另一实施例中，时钟控制器122的动作可以由基带处理器130而定。亦即，基带处理器130可根据目前的数据处理情况，告知时钟控制器122需增加或减少目前的时钟频率。In addition, although it is disclosed in the embodiment of the present invention that the clock controller 122 makes corresponding adjustment actions according to the state of the data volume in the FIFO buffer 121, however, in another embodiment of the present invention, the clock controller 122 The action of can be determined by the baseband processor 130 . That is, the baseband processor 130 can inform the clock controller 122 to increase or decrease the current clock frequency according to the current data processing situation.

图7显示根据本发明一实施例所述的接收器200于实际应用的电路图。在图7中，除了ADC 112前端的设频前端接收器110之外，还包括了输出端数字模拟转换器(digital-to-analog converter，DAC)212后端的喇叭(speaker)150。其中，异步FIFO接口220还包括了输出端的FIFO缓冲器221。与上述的原理相同，FIFO缓冲器221根据基带处理器130的时钟从基带处理器130接收数据，以及根据由固定除法器224所除出来的读出时钟输出数据至DAC 212，DAC 212并将相关的音讯数据传送至喇叭150。FIG. 7 shows a circuit diagram of the practical application of the receiver 200 according to an embodiment of the present invention. In FIG. 7, in addition to the frequency-setting front-end receiver 110 at the front end of the ADC 112, a speaker 150 at the rear end of a digital-to-analog converter (digital-to-analog converter, DAC) 212 at the output end is also included. Wherein, the asynchronous FIFO interface 220 also includes a FIFO buffer 221 at the output end. Same as above-mentioned principle, FIFO buffer 221 receives data from baseband processor 130 according to the clock of baseband processor 130, and outputs data to DAC 212 according to the readout clock divided by fixed divider 224, and DAC 212 correlates The audio data is sent to the speaker 150 .

此外，本发明亦可应用于整合式接收器。图8A显示根据本发明实施例所述的整合式接收器800A的代表图，其中低噪声放大器(low noiseamplifier，LNA)102属于模拟接收路径电路的一部分。LNA 102根据所接收的射频讯号113输出讯号给混合器(mixer)104。混合器104根据一混合信号118产生低中频(low-IF)讯号116给低中频转换电路(low-IF conversioncircuitry)106。低中频转换电路106根据一数字取样时钟信号205将所接收的低中频讯号116数字化，并输出数字讯号120给数字讯号处理器(DigitalSignal Processor，DSP)108。DSP 108根据一数字时钟信号(在此图中亦为信号205，但在稍后叙述的图8B的应用中则不为信号205)来处理数字讯号120。在图8A图的电路中，混合信号118、数字取样时钟信号205(属于低中频转换电路106)、数字时钟信号205(属于DSP 108)是由一时钟系统300产生，其中该时钟系统300包括除法器132、202和204。时钟系统300接收由频率合成器209所产生的频率fOSC，并利用上述除法器132、204和202来产生混合信号118、数字取样时钟信号205、数字时钟信号205。本发明的异步先进先出接口220可应用于低中频转换电路106和DSP 108之间，如图8B图所示。In addition, the present invention can also be applied to integrated receivers. FIG. 8A shows a representative diagram of an integrated receiver 800A in which a low noise amplifier (LNA) 102 is part of the analog receive path circuitry according to an embodiment of the present invention. The LNA 102 outputs a signal to a mixer 104 according to the received RF signal 113 . The mixer 104 generates a low-IF signal 116 to a low-IF conversion circuit (low-IF conversion circuit) 106 according to a mixed signal 118 . The low-IF conversion circuit 106 digitizes the received low-IF signal 116 according to a digital sampling clock signal 205 , and outputs a digital signal 120 to a Digital Signal Processor (Digital Signal Processor, DSP) 108 . DSP 108 processes digital signal 120 according to a digital clock signal (also signal 205 in this figure, but not signal 205 in the application of FIG. 8B described later). In the circuit of Fig. 8 A figure, mixed signal 118, digital sampling clock signal 205 (belonging to low intermediate frequency conversion circuit 106), digital clock signal 205 (belonging to DSP 108) are produced by a clock system 300, and wherein this clock system 300 comprises division 132, 202 and 204. The clock system 300 receives the frequency f OSC generated by the frequency synthesizer 209 , and uses the above-mentioned dividers 132 , 204 and 202 to generate the mixed signal 118 , the digital sampling clock signal 205 , and the digital clock signal 205 . The asynchronous FIFO interface 220 of the present invention can be applied between the low-IF conversion circuit 106 and the DSP 108, as shown in FIG. 8B.

在图8B应用本发明的异步先进先出接口220的范例中，异步先进先出接口220中的FIFO缓冲器121依照写入时钟从低中频转换电路106接收数字讯号120A和依照读出时钟输出数字讯号120B至DSP 108，并根据FIFO缓冲器121的数据状态缓冲低中频转换电路106和DSP 108两者之间的数据读写，其中的操作原理与上述内容皆完全相同，因此在此不再重复叙述。In the example of the asynchronous FIFO interface 220 of the present invention applied in FIG. 8B, the FIFO buffer 121 in the asynchronous FIFO interface 220 receives the digital signal 120A from the low-IF conversion circuit 106 according to the write clock and outputs the digital signal according to the read clock. The signal 120B is sent to the DSP 108, and according to the data status of the FIFO buffer 121, the data read and write between the low-IF conversion circuit 106 and the DSP 108 is buffered. narrative.

本发明虽以较佳实施例揭示如上，然其并非用以限定本发明的范围，本领域的技术人员，在不脱离本发明的精神和范围的前提下，可做若干的更动与润饰，因此本发明的保护范围以本发明的权利要求为准。Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims of the present invention.

Claims (45)

1. an asynchronous first in first out interface has an asynchronous readout clock and and writes clock, comprising:
One impact damper receives a digital signal according to the above-mentioned clock that writes from an analog-digital converter, and exports digital signal to a processor according to above-mentioned readout clock;
One clock controller is according to the data volume output clock system signal in a period of time that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency; And
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, and export a control signal by more above-mentioned reference frequency and above-mentioned incoming frequency, in order to adjust the above-mentioned readout clock of being exported, wherein above-mentioned second integer divisor is controlled by above-mentioned clock control signal.
2. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned processor is a baseband processor.
3. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
4. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned signal source comprises:
One divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One variable integer divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector/charge pump, more above-mentioned reference frequency and above-mentioned incoming frequency;
One loop filter produces above-mentioned controlling signal according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency, and
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned controlling signal.
5. asynchronous first in first out interface as claimed in claim 1, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor and is stored in data volume in the above-mentioned impact damper with adjustment.
6. asynchronous first in first out interface as claimed in claim 5, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
7. asynchronous first in first out interface as claimed in claim 1, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
8. asynchronous first in first out interface as claimed in claim 1, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
9. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned second integer divisor is determined by above-mentioned processor.
10. interface operation method is used to operate and has an asynchronous interface that writes a clock and a readout clock, and above-mentioned asynchronous interface comprises an impact damper, and said method comprises:
Receive a digital signal to above-mentioned impact damper according to the above-mentioned clock that writes from an analog-digital converter;
Export digital signal to a processor according to above-mentioned readout clock from above-mentioned impact damper;
According to the data volume output clock system signal in a period of time that is stored in the above-mentioned impact damper;
One concussion frequency is provided;
With above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency;
With above-mentioned readout clock divided by one second integer divisor producing an incoming frequency, and
Adjust above-mentioned readout clock by more above-mentioned reference frequency and above-mentioned incoming frequency, wherein above-mentioned second integer divisor is controlled by above-mentioned clock control signal.
11. interface operation method as claimed in claim 10, wherein above-mentioned processor is a baseband processor.
12. interface operation method as claimed in claim 10, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
13. interface operation method as claimed in claim 10, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and said method also comprises:
Change above-mentioned second integer divisor and be stored in data volume in the above-mentioned impact damper with adjustment.
14. interface operation method as claimed in claim 13, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
15. interface operation method as claimed in claim 10, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and said method also comprises above-mentioned second integer divisor of change, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
16. interface operation method as claimed in claim 10, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and said method also comprises above-mentioned second integer divisor of change, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
17. interface operation method as claimed in claim 10, wherein above-mentioned second integer divisor is determined by above-mentioned processor.
18. an asynchronous first in first out interface has an asynchronous readout clock and and writes clock, comprising:
One impact damper receives a digital signal according to the above-mentioned clock that writes from an analog-digital converter, and exports digital signal to a processor according to above-mentioned readout clock;
One clock controller is exported one first group of control bit according to the data volume that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency;
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, export one second group of control bit by more above-mentioned reference frequency and above-mentioned incoming frequency, above-mentioned first group of control bit obtained an overhead control position mutually with above-mentioned second group of control bit, and the above-mentioned readout clock of being exported according to above-mentioned overhead control position adjustment.
19. asynchronous first in first out interface as claimed in claim 18, wherein above-mentioned processor is a baseband processor.
20. asynchronous first in first out interface as claimed in claim 18, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
21. asynchronous first in first out interface as claimed in claim 18, wherein above-mentioned signal source comprises:
One first divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One second divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector, more above-mentioned reference frequency and above-mentioned incoming frequency;
One digital loop wave filter produces above-mentioned second group of control bit according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency;
One totalizer is obtained an overhead control position with above-mentioned first group of control bit mutually with above-mentioned second group of control bit; And
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned overhead control position.
22. asynchronous first in first out interface as claimed in claim 18, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and the value that above-mentioned clock controller changes above-mentioned first group of control bit is stored in data volume in the above-mentioned impact damper with adjustment.
23. asynchronous first in first out interface as claimed in claim 22, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
24. asynchronous first in first out interface as claimed in claim 18, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and above-mentioned clock controller changes the value of above-mentioned first group of control bit, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
25. asynchronous first in first out interface as claimed in claim 18, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and above-mentioned clock controller changes the value of above-mentioned first group of control bit, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
26. asynchronous first in first out interface as claimed in claim 18, the value of wherein above-mentioned first group of control bit is determined by above-mentioned processor.
27. an interface operation method is used to operate and has an asynchronous interface that writes a clock and a readout clock, above-mentioned asynchronous interface comprises an impact damper, and said method comprises:
Receive a digital signal to above-mentioned impact damper according to the above-mentioned clock that writes from an analog-digital converter;
Export digital signal to a processor according to above-mentioned readout clock from above-mentioned impact damper;
Export one first group of control bit according to the data volume that is stored in the above-mentioned impact damper;
One concussion frequency is provided;
With above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency;
With above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency;
Export one second group of control bit by more above-mentioned reference frequency and above-mentioned incoming frequency;
Above-mentioned first group of control bit obtained an overhead control position mutually with above-mentioned second group of control bit; And
The above-mentioned readout clock of being exported according to above-mentioned overhead control position adjustment.
28. interface operation method as claimed in claim 27, wherein above-mentioned processor is a baseband processor.
29. interface operation method as claimed in claim 27, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
30. interface operation method as claimed in claim 27, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and said method comprises that also the value that changes above-mentioned first group of control bit is stored in data volume in the above-mentioned impact damper with adjustment.
31. interface operation method as claimed in claim 30, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
32. interface operation method as claimed in claim 27, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and said method also comprises the value that changes above-mentioned first group of control bit, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
33. interface operation method as claimed in claim 27, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and said method also comprises the value that changes above-mentioned first group of control bit, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
34. interface operation method as claimed in claim 27, the value of wherein above-mentioned first group of control bit is determined by above-mentioned processor.
35. an integrated receiver comprises:
One frequency synthesizer produces an output signal;
One clock system produces a mixed signal and according to above-mentioned output signal and writes clock;
One simulation RX path circuit produces a Low Medium Frequency signal according to above-mentioned mixed signal;
One Low Medium Frequency change-over circuit converts above-mentioned Low Medium Frequency signal to one first digital signal according to the above-mentioned clock that writes;
One processor is handled one second digital signal according to a readout clock; And
One asynchronous first in first out interface is coupled between above-mentioned Low Medium Frequency change-over circuit and the above-mentioned processor, and has asynchronous above-mentioned readout clock and the above-mentioned clock that writes, and comprising:
One impact damper receives above-mentioned first digital signal according to the above-mentioned clock that writes from above-mentioned digital conversion circuit, and exports above-mentioned second digital signal to above-mentioned processor according to above-mentioned readout clock;
One clock controller is according to the data volume output clock system signal in a period of time that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency; And
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, and export a control signal by more above-mentioned reference frequency and above-mentioned incoming frequency, in order to adjust the above-mentioned readout clock of being exported, wherein above-mentioned second integer divisor is controlled by above-mentioned clock control signal.
36. integrated receiver as claimed in claim 35, wherein above-mentioned processor is a Digital System Processor.
37. integrated receiver as claimed in claim 35, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
38. integrated receiver as claimed in claim 35, wherein above-mentioned signal source comprises:
One divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One variable integer divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector/charge pump, more above-mentioned reference frequency and above-mentioned incoming frequency;
One loop filter produces above-mentioned controlling signal according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency, and
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned controlling signal.
39. integrated receiver as claimed in claim 35, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor and is stored in data volume in the above-mentioned impact damper with adjustment.
40. integrated receiver as claimed in claim 39, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
41. integrated receiver as claimed in claim 35, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
42. integrated receiver as claimed in claim 35, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
43. integrated receiver as claimed in claim 35, wherein above-mentioned second integer divisor is determined by above-mentioned processor.
44. an integrated receiver comprises:
One frequency synthesizer produces an output signal;
One clock system produces a mixed signal and according to above-mentioned output signal and writes clock;
One simulation RX path circuit produces a Low Medium Frequency signal according to above-mentioned mixed signal;
One Low Medium Frequency change-over circuit converts above-mentioned Low Medium Frequency signal to one first digital signal according to the above-mentioned clock that writes;
One processor is handled one second digital signal according to a readout clock; And
One asynchronous first in first out interface is coupled between above-mentioned Low Medium Frequency change-over circuit and the above-mentioned processor, and has asynchronous above-mentioned readout clock and the above-mentioned clock that writes, and comprising:
One impact damper receives a digital signal according to the above-mentioned clock that writes from an analog-digital converter, and exports digital signal to a processor according to above-mentioned readout clock;
One clock controller is exported one first group of control bit according to the data volume that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency; And
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, export one second group of control bit by more above-mentioned reference frequency and above-mentioned incoming frequency, above-mentioned first group of control bit obtained an overhead control position mutually with above-mentioned second group of control bit, and the above-mentioned readout clock of being exported according to above-mentioned overhead control position adjustment.
45. integrated receiver as claimed in claim 44, wherein above-mentioned signal source comprises:
One first divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One second divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector, more above-mentioned reference frequency and above-mentioned incoming frequency;
One digital loop wave filter produces above-mentioned second group of control bit according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency;
One totalizer is obtained an overhead control position with above-mentioned first group of control bit mutually with above-mentioned second group of control bit; And
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned overhead control position.
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Publication number Priority date Publication date Assignee Title
CN110532117A (en) * 2018-05-25 2019-12-03 Arm有限公司 For the error checking for the main signal transmitted between the first and second clock domains

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US4896337A (en) * 1988-04-08 1990-01-23 Ampex Corporation Adjustable frequency signal generator system with incremental control
JP4251094B2 (en) * 2003-12-04 2009-04-08 ヤマハ株式会社 Asynchronous signal input device and sampling frequency converter
US7996704B2 (en) * 2007-08-21 2011-08-09 Richwave Technology Corp. Asynchronous first in first out interface and operation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110532117A (en) * 2018-05-25 2019-12-03 Arm有限公司 For the error checking for the main signal transmitted between the first and second clock domains
CN110532117B (en) * 2018-05-25 2023-11-03 Arm有限公司 Error checking for a master signal transmitted between a first and a second clock domain

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