CN102063283A - Asynchronous first-in first-out interface, operating method for interface and integrated receiver - Google Patents
Asynchronous first-in first-out interface, operating method for interface and integrated receiver Download PDFInfo
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- CN102063283A CN102063283A CN 200910221274 CN200910221274A CN102063283A CN 102063283 A CN102063283 A CN 102063283A CN 200910221274 CN200910221274 CN 200910221274 CN 200910221274 A CN200910221274 A CN 200910221274A CN 102063283 A CN102063283 A CN 102063283A
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Abstract
The invention relates to an asynchronous first-in first-out interface, which is provided with a read-out clock and a read-in clock. The asynchronous first-in first-out interface comprises a buffer, a clock controller, a reference source and a signal source, wherein the buffer receives a digital signal from an analog-digital converter according to the read-in clock and outputs a digital signal to a processor according to the read-out clock; the clock controller outputs a clock control signal according to data volume stored in the buffer; the reference source provides an oscillation frequency; and the signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read-out clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency so as to adjust the outputted read-out clock, wherein the second integer divisor is controlled by the clock control signal.
Description
Technical field
(first in first out, FIFO) interface particularly relate to radio frequency (radio frequency, RF) asynchronous FIFO interface in the device to the present invention relates to asynchronous first in first out.
Background technology
Along with popularizing of wireless telecommunications (mobile phone, wireless network), market to communication system more at a low price, more low power consuming and the radio frequency of low profile (form-factor) is arranged more (radio frequency, RF) demand of transceiver is ardent day by day.Recently, analog transceiver, digital processing unit and frequency generator have been integrated on the one chip to satisfy the demand.In the RF transceiver, mimic channel and digital circuit are different to the demand of frequency.For example, analog-digital converter (analog-to-digital converter, ADC) and digital analog converter (digital-to-analog converter DAC) needs low vibration (jitter) clock to increase the degree of accuracy of data-switching in mimic channel.Yet in digital circuit, digital processing unit but not necessarily needs the clock of low vibration.
Because this problem, the available circuit of Fig. 1 is independent with the clock between ADC and the digital processing unit.Fig. 1 has shown the calcspar that uses a receiver 100 of asynchronous first in first out interface 120.Receiver 100 comprises a radio-frequency front-end receiver 110, an analog-digital converter (ADC) 112, one first signal source 114, a fifo buffer 121, a clock controller 122, a variable integer divider 124, a baseband processor 130, a secondary signal source 132 and a reference source 140.
Radio-frequency front-end receiver 110 receives a radio frequency (RF) signal that is sent by transmitter (not being shown in drawing), and convert this RF signal down to an intermediate frequency (Intermediate Frequency, IF) signal according to the local signal that first signal source 114 is produced.This local signal be by first signal source, 114 generation of low vibration with increase signal to noise ratio (S/N ratio) (signal to noise ratio, SNR) and the adjacency channel blocking effect of reduction when frequency downconversion.ADC 112 converts intermediate frequency signal to data, and according to the variable frequency clock output data that local signal produced, in order to the use of avoiding extra low dither signal source and the demand that satisfies this low vibration clock.Baseband processor 130 is on these data, according to second signal operation signal processing capacity that is produced by secondary signal source 132, for example: transmission mode detection, time domain data processing, frequency domain data processing and chnnel coding etc.Secondary signal source 132 is a fixed frequency signal source, and a ring type oscillator for example is to reduce hardware cost.Second signal operates as a clock of baseband processor 130.Single reference source 140 can be shared with further reduction hardware cost in first signal source 114 and secondary signal source 132.
The clock that is provided to baseband processor 130 by secondary signal source 132 can be asynchronous with the clock of ADC that each signal source is provided to 112.Therefore in the available circuit of Fig. 1, adopted an asynchronous FIFO interface 120 to handle the transmission of ADC 112 and 130 these asynchronous datas of baseband processor.Asynchronous FIFO interface 120 comprises fifo buffer 121, clock controller 122 and variable integer divider 124.Fifo buffer 121 is coupled to 112 of baseband processor 130 and ADC, buffering data transfer between the two.Fifo buffer 121 according to one write clock (Write clock) from ADC 112 receive data and according to a readout clock (Read clock) output data to baseband processor 130.Write clock and be the clock of ADC 112 and readout clock is the clock of baseband processor 130.When ADC 112 write the readout clock of clock faster than baseband processor 130, can cause overflowing of fifo buffer 121 data, so clock controller 122 increases the divider value of variable integer divider 124, write the frequency of clock with reduction.On the contrary, ADC 112 writes the readout clock that clock is slower than baseband processor 130, can cause emptying of fifo buffer 121 data, so clock controller 122 reduces the divider value of variable integer divider 124, writes the frequency of clock with raising.
In the available circuit of Fig. 1, be to control the clock that writes of ADC 112, and then reach the data mode of control fifo buffer 121 by the divider value that clock controller 122 is adjusted variable integer divider 124.Yet the control of fifo buffer 121 data modes might not be adjusted by variable integer divider 124.
Summary of the invention
In view of this, one embodiment of the invention disclose a kind of asynchronous first in first out interface, have an asynchronous readout clock and and write clock, comprise a fifo buffer, a clock controller, a reference source and a signal source.Fifo buffer receives a digital signal according to writing clock from an analog-digital converter, and exports digital signal to a processor according to readout clock.Clock controller is according to the data volume output clock system signal in a period of time that is stored in the fifo buffer.Reference source provides a concussion frequency.Signal source will shake frequency divided by one first integer divisor with produce a reference frequency, with readout clock divided by one second integer divisor to produce an incoming frequency, and by relatively reference frequency and incoming frequency are exported a control signal, in order to adjust the readout clock of being exported, wherein second integer divisor is controlled by the clock control signal.
In addition, another embodiment of the present invention discloses a kind of interface operation method, is used to operate have an asynchronous interface that writes a clock and a readout clock, and above-mentioned asynchronous interface comprises a fifo buffer.Said method comprises that basis writes clock and receives a digital signal to fifo buffer from an analog-digital converter, export digital signal to a processor according to readout clock from fifo buffer, according to the data volume output clock system signal in a period of time that is stored in the fifo buffer, one concussion frequency is provided, to shake frequency divided by one first integer divisor to produce a reference frequency, with readout clock divided by one second integer divisor to produce an incoming frequency, and adjust readout clock by relatively reference frequency and incoming frequency, wherein second integer divisor is controlled by the clock control signal.
In addition, another embodiment of the present invention discloses a kind of asynchronous first in first out interface, has an asynchronous readout clock and and writes clock, comprises a fifo buffer, a clock controller, a reference source and a signal source.Fifo buffer receives a digital signal according to writing clock from an analog-digital converter, and exports digital signal to a processor according to readout clock.Clock controller is exported one first group of control bit according to the data volume that is stored in the fifo buffer.Reference source provides a concussion frequency.Signal source will shake frequency divided by one first integer divisor with produce a reference frequency, with readout clock divided by one second integer divisor producing an incoming frequency, to export one second group of control bit, first group of control bit obtained an overhead control position mutually with second group of control bit with incoming frequency by reference frequency relatively, and the readout clock of being exported according to the adjustment of overhead control position.
In addition, another embodiment of the present invention discloses a kind of interface operation method, is used to operate have an asynchronous interface that writes a clock and a readout clock, and above-mentioned asynchronous interface comprises a fifo buffer.Said method comprises that basis writes clock and receives a digital signal to fifo buffer from an analog-digital converter, export digital signal to a processor according to readout clock from fifo buffer, export one first group of control bit according to the data volume that is stored in the fifo buffer, one concussion frequency is provided, to shake frequency divided by one first integer divisor to produce a reference frequency, with readout clock divided by one second integer divisor to produce an incoming frequency, by relatively reference frequency and incoming frequency are exported one second group of control bit, first group of control bit obtained an overhead control position mutually with second group of control bit, and the readout clock of being exported according to the adjustment of overhead control position.
In addition, another embodiment of the present invention discloses a kind of integrated receiver, comprises a frequency synthesizer, a clock system, a simulation RX path circuit, a Low Medium Frequency change-over circuit, a processor and an asynchronous first in first out interface.Frequency synthesizer produces an output signal.Clock system produces a mixed signal and according to output signal and writes clock.Simulation RX path circuit produces a Low Medium Frequency signal according to mixed signal.The Low Medium Frequency change-over circuit converts the Low Medium Frequency signal to one first digital signal according to writing clock.Processor is handled one second digital signal according to a readout clock.Asynchronous first in first out interface is coupled between Low Medium Frequency change-over circuit and the processor, and has asynchronous readout clock and write clock, comprises an impact damper, a clock controller, a reference source and a signal source.Impact damper receives first digital signal according to writing clock from digital conversion circuit, and exports second digital signal to processor according to readout clock.Clock controller is according to the data volume output clock system signal in a period of time that is stored in the impact damper.Reference source provides a concussion frequency.Signal source will shake frequency divided by one first integer divisor to produce a reference frequency, with readout clock divided by one second integer divisor to produce an incoming frequency, and by relatively reference frequency and incoming frequency are exported a control signal, in order to adjust the readout clock of being exported, wherein second integer divisor is controlled by the clock control signal.
In addition, another embodiment of the present invention discloses a kind of integrated receiver, comprises a frequency synthesizer, a clock system, a simulation RX path circuit, a Low Medium Frequency change-over circuit, a processor and an asynchronous first in first out interface.Frequency synthesizer produces an output signal.Clock system produces a mixed signal and according to output signal and writes clock.Simulation RX path circuit produces a Low Medium Frequency signal according to mixed signal.The Low Medium Frequency change-over circuit converts the Low Medium Frequency signal to one first digital signal according to writing clock.Processor is handled one second digital signal according to a readout clock.Asynchronous first in first out interface is coupled between Low Medium Frequency change-over circuit and the processor, and has asynchronous readout clock and write clock, comprises an impact damper, a clock controller, a reference source and a signal source.Impact damper receives first digital signal according to writing clock from digital conversion circuit, and exports second digital signal to processor according to readout clock.Clock controller is exported one first group of control bit according to the data volume that is stored in the impact damper.Reference source provides a concussion frequency.Signal source will shake frequency divided by one first integer divisor to produce a reference frequency, with readout clock divided by one second integer divisor to produce an incoming frequency, by relatively reference frequency and incoming frequency are exported one second group of control bit, first group of control bit obtained an overhead control position mutually with second group of control bit, and the readout clock of being exported according to the adjustment of overhead control position.
Description of drawings
Fig. 1 shows the calcspar of a receiver that uses asynchronous first in first out interface;
Fig. 2 shows the calcspar according to a receiver of the described use asynchronous first in first out interface of one embodiment of the invention;
Fig. 3 A shows the calcspar according to the described secondary signal source of one embodiment of the invention;
Fig. 3 B shows the calcspar according to the described secondary signal of another embodiment of the present invention source;
Fig. 4 A shows the synoptic diagram that successively decreases according to data volume in the described fifo buffer of one embodiment of the invention;
Fig. 4 B shows the synoptic diagram that increases progressively according to data volume in the described fifo buffer of one embodiment of the invention;
Fig. 5 shows the described interface operation method of one embodiment of the invention;
Fig. 6 shows the described interface operation method of another embodiment of the present invention;
Fig. 7 shows according to the described receiver of one embodiment of the invention in the circuit diagram of practical application;
Fig. 8 A shows the circuit diagram of an integrated receiver; And
Fig. 8 B shows that asynchronous first in first out interface of the present invention is applied to the example of the integrated receiver of Fig. 8 A.
The reference numeral explanation
100,200～receiver, 102～low noise amplifier
104～mixer, 106～Low Medium Frequency change-over circuit
108～Digital System Processor, 110～radio-frequency front-end receiver
112～analog-digital converter, 113～radio-frequency (RF) signal
114,132,132A, 132B～signal source
116～Low Medium Frequency signal 121,221～fifo buffer
120,220～asynchronous FIFO interface
120A, 120B～digital signal 122～clock controller
124～variable integer divider, 130～baseband processor
132,204,1325～divider, 140～reference source
150～loudspeaker, 209～frequency synthesizer
The divider of 212～digital analog converter 224～fixedly
300～clock system
410,412,414,420,422,424～impact damper
800A, 800B～integrated receiver
1321～variable integer divider
1322～phase-frequency detector/charge pump
1323～loop filter, 1324～voltage control oscillator
CLK_BB1, CLK_BB2～clock frequency
f
OSCThe output frequency of～frequency synthesizer
f
Xtal～concussion frequency F
In1, F
In2～incoming frequency
F
Ref1, F
Ref2～reference frequency FIFO_R～reading of data
FIFO_W～write data
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Fig. 2 shows the calcspar according to a receiver 200 of the described use asynchronous first in first out interface of one embodiment of the invention.Receiver 200 comprises a radio-frequency front-end receiver 110, an analog-digital converter 112, one first signal source 114, a fifo buffer 121, a clock controller 122, a variable integer divider 124, a baseband processor 130, a secondary signal source 132 and a reference source 140.Identical with the existing framework of Fig. 1 is, has also adopted an asynchronous FIFO interface 220 to handle the asynchronous data transfer of 130 of ADC 112 and baseband processor in the present embodiment.Different with the existing framework of Fig. 1 is that asynchronous FIFO interface 220 comprises fifo buffer 121, clock controller 122, secondary signal source 132 and reference source 140.Fifo buffer 121 is coupled to 112 of baseband processor 130 and ADC, buffering data transfer between the two.Fifo buffer 121 according to one write clock from ADC 112 receive data and according to a readout clock output data to baseband processor 130.Write clock and be the clock of ADC112 and readout clock is the clock of baseband processor 130.Be slower than the clock that writes of ADC 112 when the readout clock of baseband processor 130, can cause overflowing of fifo buffer 121 data, therefore clock controller 122 increases the frequency of the readout clock of secondary signal source 132 outputs, so that increase the readout clock of baseband processor 130.On the contrary, when the readout clock of baseband processor 130 the clock that writes faster than ADC 112, can cause emptying of fifo buffer 121 data, so clock controller 122 is with the frequency reduction of the readout clock of secondary signal source 132 outputs, so that reduce the readout clock of baseband processor 130.By the mode of the output readout clock in control secondary signal source 132, can keep can not making the data of fifo buffer 121 to overflow or empty with the balance that writes clock of ADC 112.More than be the narration of summary of the present invention, its detailed implementation detail is described below.
Fig. 3 A shows the calcspar according to the described secondary signal of one embodiment of the invention source.Secondary signal source 132A can be a compositor (Synthesizer), comprise a variable integer divider 1321, one phase-frequency detector/charge pump (Phase Frequency Detector/Charge Pump, PFD/CP) 1322, one loop filter (loop filter), 1323, one voltage control oscillator (Voltage-ControlledOscillator, VCO) 1324 and one divider 1325.In Fig. 3 A, clock rate C LK_BB1 provides to the clock of baseband processor 130, and fifo buffer 121 is to baseband processor 130 according to this clock rate C LK_BB1 output data.Therefore, when the data mode imbalance in the fifo buffer 121 (data overfill or empty), can adjust the size of clock rate C LK_BB1.In Fig. 3 A, variable integer divider 1321 has the function divided by an integer M with the clock rate C LK_BB1 of baseband processor 130, and wherein the value of M is by clock controller 122 decisions.Divided by after the integer M, the frequency of being exported (CLK_BB1/M) is sent to PFD/CP 1322 as its incoming frequency f to variable integer divider 1321 with the clock rate C LK_BB1 of baseband processor 130
In1On the other hand, divider 1325 receives the concussion frequency f of reference source 140
Xtal, and with its divided by a round values N with output reference frequency f
Ref1The concussion frequency f of reference source 140
XtalCan be to produce by a crystal oscillator (Crystal).PFD/CP 1322 receives incoming frequency f
In1With reference frequency f
Ref1, detecting/more between the two measures of dispersion and send the result and give loop filter 1323, loop filter 1323 is sent controlling signal again and is given VCO 1324, makes VCO 1324 its clock rate C LK_BB1 that export of adjustment.When the frequency stabilization of clock frequency CLK_BB1, its value is reference source 140 concussion frequency f
Xtal(M/N) doubly.Clock controller 122 can be adjusted divider value (M) size of variable integer divider 1321 according to the clock data state of fifo buffer 121, and then adjusts the clock rate C LK_BB1 that VCO 1324 exports baseband processor 130 to.For instance, when the data volume in being stored in fifo buffer 121 is higher than a higher limit, represent data volume in the fifo buffer 121 may arrive the state of overfill, so divider value (M) size that clock controller 122 can be adjusted variable integer divider 1321 increase clock rate C LK_BB1.Thus, fifo buffer 121 just according to the clock rate C LK_BB1 output data that increases to baseband processor 130, promote the speed of baseband processor 130 from fifo buffer 121 reading of data.Wherein, the clock rate C LK_BB1 after the increase can write the speed of fifo buffer 121 greater than ADC 112, to solve the situation of data overfill in the fifo buffer 121.Similarly, when the data volume in being stored in fifo buffer 121 is lower than a lower limit, represent the data volume in the fifo buffer 121 may arrive the state of emptying, so divider value (M) size that clock controller 122 can be adjusted variable integer divider 1321 reduce clock rate C LK_BB1.Thus, fifo buffer 121 just according to the clock rate C LK_BB1 output data that reduces to baseband processor 130, reduce the speed of baseband processor 130 from fifo buffer 121 reading of data.Wherein, the clock rate C LK_BB1 after the reduction can write the speed of fifo buffer 121 less than ADC 112, to solve the situation that data empty in the fifo buffer 121.It should be noted that, though above embodiment mentions clock controller 122 is adjusted variable integer divider 1321 according to the data mode of fifo buffer 121 divider value (M) size, and then adjustment VCO 1324 exports the clock rate C LK_BB1 of baseband processor 130 to, yet, in another embodiment of the present invention, the divider value of variable integer divider 1321 (M) size also can be decided according to present data processing situation by baseband processor 130.That is baseband processor 130 also can be adjusted its clock frequency voluntarily by clock controller 122.
Fig. 3 B shows the calcspar according to the described secondary signal of another embodiment of the present invention source.Secondary signal source 132B can be a compositor (Synthesizer), comprise a divider 1421, a phase-frequency detector (Phase Frequency Detector, PFD) 1422, one digital loop wave filter 1423, a totalizer 1424, digital voltage control oscillator (Digital Voltage-Controlled Oscillator, DCO) 1425 and one divider 1426.Identical with the embodiment of Fig. 3 A, clock rate C LK_BB2 is the clock of baseband processor 130, and fifo buffer 121 is to baseband processor 130 according to this clock rate C LK_BB2 output data.Therefore, when the data mode imbalance in the fifo buffer 121 (data overfill or empty), can adjust the size of clock rate C LK_BB2.Yet different with the embodiment of Fig. 3 A is that the enforcement framework in Fig. 3 B secondary signal source belongs to digital mode, and is as described below.In Fig. 3 B, divider 1421 has the function with the clock rate C LK_BB2 frequency division of baseband processor 130, and the frequency of being exported is delivered to PFD 1422 as its incoming frequency f
In2In addition, divider 1426 receives the concussion frequency f of reference source 140
Xtal, and with its frequency division with output reference frequency f
Ref2The concussion frequency f of reference source 140
XtalCan be to produce by a crystal oscillator.PFD 1422 receives incoming frequency f
In2With reference frequency f
Ref2, detecting/more between the two measures of dispersion and send the result and give digital loop wave filter 1423, digital loop wave filter 1423 is sent one group of control bit (control bits) again to totalizer 1424.Totalizer 1424 is another group control bit of being exported of receive clock controller 122 also, and an overhead control position is exported in two groups of control bit additions give DCO 1425, makes DCO 1425 adjust it and exports the clock rate C LK_BB2 of baseband processor 130 to.For instance, when the data volume in being stored in fifo buffer 121 is higher than a higher limit, represent data volume in the fifo buffer 121 may arrive the state of overfill, so the value (for example giving the value of bigger control bit) that clock controller 122 can be adjusted the control bit of its output increase clock rate C LK_BB2.Thus, fifo buffer 121 just according to the clock rate C LK_BB2 output data that increases to baseband processor 130, promote the speed of baseband processor 130 from fifo buffer 121 reading of data.Wherein, the clock rate C LK_BB2 after the increase can write the speed of fifo buffer 121 greater than ADC 112, to solve the situation of data overfill in the fifo buffer 121.Similarly, when the data volume in being stored in fifo buffer 121 is lower than a lower limit, represent the data volume in the fifo buffer 121 may arrive the state of emptying, so the value (for example giving the value of less control bit) that clock controller 122 can be adjusted the control bit of its output reduce clock rate C LK_BB2.Thus, fifo buffer 121 just according to the clock rate C LK_BB2 output data that reduces to baseband processor 130, reduce the speed of baseband processor 130 from fifo buffer 121 reading of data.Wherein, the clock rate C LK_BB2 after the reduction can write the speed of fifo buffer 121 less than ADC 112, to solve the situation that data empty in the fifo buffer 121.Identical with the embodiment of Fig. 3 A, the value of the control bit that clock controller 122 is exported also can be decided according to present data processing situation by baseband processor 130.That is baseband processor 130 also can be adjusted its clock frequency voluntarily by clock controller 122.Must be noted that in this embodiment, only when the circuit original state, just need use the output valve of digital loop wave filter 1423, and after operation in the value breech lock of digital loop wave filter 1423 is lived no longer change.Get and generation be that clock controller 122 is adjusted the value of its control bit of exporting according to the data mode of fifo buffer 121, and then adjusts the value of overhead control position.Thus, DCO 1425 can dynamically adjust the clock rate C LK_BB2 that it exports baseband processor 130 to according to the overhead control position.More particularly, when the data mode of fifo buffer 121 when overflowing (data surpass higher limit) near data, the value of exportable positive second control bit of clock controller 122, make the bigger overhead control position of totalizer 1424 outputs give DCO 1425, and then make DCO 1425 improve the clock rate C LK_BB2 of its output.On the contrary, when the data mode of fifo buffer 121 when emptying (data are lower than lower limit) near data, the value of exportable negative second control bit of clock controller 122, make the less overhead control position of totalizer 1424 outputs give DCO 1425, and then make DCO 1425 reduce the clock rate C LK_BB2 of its output.In above two embodiment, the situation of having mentioned data overfill in the fifo buffer 121 or having emptied below is narrated the state of data increasing or decreasing in the fifo buffer 121 with summary.
Fig. 4 A represents that the data volume in this fifo buffer 121 successively decreases.For example, the frequency that writes clock is 4/T and the frequency of readout clock is 5/T.The reading speed of this fifo buffer than this fifo buffer 121 to write clock fast, so this data volume all can be successively decreased in during each T.With reference to figure 4A, FIFO_R represents this fifo buffer 121 in this regional sensed data, and FIFO_W represents that this fifo buffer 121 writes data in this zone, and stain represents that this data storing is in impact damper.410 are shown in t
oThe time this fifo buffer 121,412 be shown in t
oThis fifo buffer 121 during+T, and 414 be shown in t
oFifo buffer 121 during+2T.When this data volume is reduced to following time of lower limit, then the empty signal of fifo buffer can be drawn high and sent " making a mistake " (errorhappened) message during next.
Fig. 4 B represents that the data volume in this fifo buffer 121 increases progressively.For example, the frequency that writes clock is that the frequency of 6/T readout clock is 5/T.This data volume all can increase progressively in during each T.With reference to Fig. 4 B, 420 are shown in t
1The time this fifo buffer 121,422 be shown in t
1This fifo buffer 121 during+T, and 424 be shown in t
1Fifo buffer 121 during+4T.When this data volume exceeded the upper limit last, then the full signal of fifo buffer can be drawn high and sent " making a mistake " message during next.
As mentioned above, to write clock asynchronous when this readout clock and this, and this fifo buffer can suffer from overfill or empty excessively problem and cause data transfer error.Yet the mode of the frequency of its available this readout clock of control is avoided.Fig. 5 shows the described interface operation method of one embodiment of the invention, is used to operate shown in Figure 2 have one and write the asynchronous FIFO interface 220 of a clock and a readout clock, and is used in combination the described secondary signal of Fig. 3 A source 132A.At first, in step S50, receive a digital signal to fifo buffer 121 from ADC 112 according to writing clock.In step S51, export a digital signal to baseband processor 130 from fifo buffer 121 according to readout clock.In step S52, provide a concussion frequency f by reference source 140
XtalIn step S53, the divider 1325 among Fig. 3 A will shake frequency divided by the first integer divisor N to produce a reference frequency f
Ref1In step S54, the variable integer divider 1321 among Fig. 3 A with readout clock divided by one second integer divisor M to produce an incoming frequency f
In1In step S55, phase-frequency detector/charge pump 1322 is reference frequency f relatively
Ref1With incoming frequency f
In1, and loop filter 1323 is exported a controlling signal according to comparative result.In step S56, voltage control oscillator 1324 readout clock that adjustment is exported according to controlling signal among Fig. 3 A.In the process flow diagram of Fig. 5, the second integer divisor M is controlled by the clock control signal, that is, when readout clock is low excessively when causing asynchronous FIFO interface 220 data overfill, promptly adjust the value of the second integer divisor M, so that increase the frequency of readout clock, vice versa.
Fig. 6 shows the described interface operation method of another embodiment of the present invention, is used to operate shown in Figure 2 have one and write the asynchronous FIFO interface 220 of a clock and a readout clock, and is used in combination the described secondary signal of Fig. 3 B source 132B.At first, in step S60, receive a digital signal to fifo buffer 121 from ADC 112 according to writing clock.In step S61, export digital signal to a baseband processor 130 from fifo buffer 121 according to readout clock.In step S62, export first group of control bit according to the data volume that is stored in the fifo buffer 121.In step S63, provide a concussion frequency f by reference source
XtalIn step S64, the divider 1426 of Fig. 3 B will shake frequency f
XtalDivided by one first integer divisor to produce a reference frequency f
Ref2In step S65, the divider 1421 of Fig. 3 B with readout clock divided by one second integer divisor to produce an incoming frequency f
In2In step S66, compare reference frequency f
Ref2With incoming frequency f
In2In step S67, export one second group of control bit according to comparative result.In step S68, the totalizer 1424 of Fig. 3 B is obtained an overhead control position with first group of control bit mutually with second group of control bit.In step S69, the readout clock that the digital voltage of Fig. 3 B control oscillator 1425 will be exported according to the adjustment of overhead control position.Or rather, when state that fifo buffer 121 empties near data, first group of control bit being exported among the step S62 can be negative, makes overhead control position after the addition diminish and reduces the readout clock of being exported.On the contrary, when state that fifo buffer 121 overflows near data, first group of control bit being exported among the step S62 just can be, and makes that the overhead control position after the addition becomes big and increases the readout clock of being exported.
In addition, though what disclose in the embodiments of the invention is according to the data volume state in the fifo buffer 121, make clock controller 122 do corresponding adjustment action, yet, in another embodiment of the present invention, the action of clock controller 122 can be decided by baseband processor 130.That is baseband processor 130 can inform that clock controller 122 needs to increase or reduce present clock frequency according to present processing condition data.
Fig. 7 shows according to the described receiver 200 of one embodiment of the invention in the circuit diagram of practical application.In Fig. 7,, output terminal digital analog converter (digital-to-analog converter, DAC) loudspeaker of 212 rear ends (speaker) 150 have also been comprised except establishing the frequency front-end receiver 110 of ADC 112 front ends.Wherein, asynchronous FIFO interface 220 has also comprised the fifo buffer 221 of output terminal.Identical with above-mentioned principle, fifo buffer 221 receives data according to the clock of baseband processor 130 from baseband processor 130, and according to by readout clock output data that fixedly divider 224 removed out to DAC 212, DAC 212 also is sent to loudspeaker 150 with relevant message data.
In addition, the present invention also can be applicable to integrated receiver.Fig. 8 A shows the representative graph according to the described integrated receiver 800A of the embodiment of the invention, and wherein (low noiseamplifier, LNA) 102 belong to a part of simulating the RX path circuit to low noise amplifier.LNA 102 gives mixer (mixer) 104 according to radio-frequency (RF) signal 113 output signals that received.Mixer 104 produces Low Medium Frequency (low-IF) signal 116 according to a mixed signal 118 and gives Low Medium Frequency change-over circuit (low-IF conversioncircuitry) 106.With Low Medium Frequency signal 116 digitizings that received, and output digital signal 120 is given Digital System Processor (DigitalSignal Processor, DSP) 108 to Low Medium Frequency change-over circuit 106 according to a digital sampling clock signal 205.DSP 108 handles digital signal 120 according to a dagital clock signal (also be signal 205, but then be not signal 205 in the application of Fig. 8 B that narrates after a while) in this figure.In the circuit of Fig. 8 A figure, mixed signal 118, digital sampling clock signal 205 (belonging to Low Medium Frequency change-over circuit 106), dagital clock signal 205 (belonging to DSP 108) are to be produced by a clock system 300, and wherein this clock system 300 comprises divider 132,202 and 204.Clock system 300 receives the frequency f that is produced by frequency synthesizer 209
OSC, and utilize above-mentioned divider 132,204 and 202 to produce mixed signal 118, digital sampling clock signal 205, dagital clock signal 205.Asynchronous first in first out interface 220 of the present invention can be applicable between Low Medium Frequency change-over circuit 106 and the DSP 108, shown in Fig. 8 B figure.
Use in the example of asynchronous first in first out interface 220 of the present invention at Fig. 8 B, fifo buffer 121 in the asynchronous first in first out interface 220 receives digital signal 120A and exports digital signal 120B to DSP 108 according to readout clock from Low Medium Frequency change-over circuit 106 according to writing clock, and according to the data mode of fifo buffer 121 buffering Low Medium Frequency change-over circuit 106 and DSP 108 reading and writing data between the two, therefore principle of operation wherein and foregoing are all identical, at this repeated description no longer.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting scope of the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (45)
1. an asynchronous first in first out interface has an asynchronous readout clock and and writes clock, comprising:
One impact damper receives a digital signal according to the above-mentioned clock that writes from an analog-digital converter, and exports digital signal to a processor according to above-mentioned readout clock;
One clock controller is according to the data volume output clock system signal in a period of time that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency; And
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, and export a control signal by more above-mentioned reference frequency and above-mentioned incoming frequency, in order to adjust the above-mentioned readout clock of being exported, wherein above-mentioned second integer divisor is controlled by above-mentioned clock control signal.
2. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned processor is a baseband processor.
3. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
4. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned signal source comprises:
One divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One variable integer divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector/charge pump, more above-mentioned reference frequency and above-mentioned incoming frequency;
One loop filter produces above-mentioned controlling signal according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency, and
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned controlling signal.
5. asynchronous first in first out interface as claimed in claim 1, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor and is stored in data volume in the above-mentioned impact damper with adjustment.
6. asynchronous first in first out interface as claimed in claim 5, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
7. asynchronous first in first out interface as claimed in claim 1, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
8. asynchronous first in first out interface as claimed in claim 1, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
9. asynchronous first in first out interface as claimed in claim 1, wherein above-mentioned second integer divisor is determined by above-mentioned processor.
10. interface operation method is used to operate and has an asynchronous interface that writes a clock and a readout clock, and above-mentioned asynchronous interface comprises an impact damper, and said method comprises:
Receive a digital signal to above-mentioned impact damper according to the above-mentioned clock that writes from an analog-digital converter;
Export digital signal to a processor according to above-mentioned readout clock from above-mentioned impact damper;
According to the data volume output clock system signal in a period of time that is stored in the above-mentioned impact damper;
One concussion frequency is provided;
With above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency;
With above-mentioned readout clock divided by one second integer divisor producing an incoming frequency, and
Adjust above-mentioned readout clock by more above-mentioned reference frequency and above-mentioned incoming frequency, wherein above-mentioned second integer divisor is controlled by above-mentioned clock control signal.
11. interface operation method as claimed in claim 10, wherein above-mentioned processor is a baseband processor.
12. interface operation method as claimed in claim 10, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
13. interface operation method as claimed in claim 10, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and said method also comprises:
Change above-mentioned second integer divisor and be stored in data volume in the above-mentioned impact damper with adjustment.
14. interface operation method as claimed in claim 13, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
15. interface operation method as claimed in claim 10, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and said method also comprises above-mentioned second integer divisor of change, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
16. interface operation method as claimed in claim 10, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and said method also comprises above-mentioned second integer divisor of change, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
17. interface operation method as claimed in claim 10, wherein above-mentioned second integer divisor is determined by above-mentioned processor.
18. an asynchronous first in first out interface has an asynchronous readout clock and and writes clock, comprising:
One impact damper receives a digital signal according to the above-mentioned clock that writes from an analog-digital converter, and exports digital signal to a processor according to above-mentioned readout clock;
One clock controller is exported one first group of control bit according to the data volume that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency;
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, export one second group of control bit by more above-mentioned reference frequency and above-mentioned incoming frequency, above-mentioned first group of control bit obtained an overhead control position mutually with above-mentioned second group of control bit, and the above-mentioned readout clock of being exported according to above-mentioned overhead control position adjustment.
19. asynchronous first in first out interface as claimed in claim 18, wherein above-mentioned processor is a baseband processor.
20. asynchronous first in first out interface as claimed in claim 18, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
21. asynchronous first in first out interface as claimed in claim 18, wherein above-mentioned signal source comprises:
One first divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One second divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector, more above-mentioned reference frequency and above-mentioned incoming frequency;
One digital loop wave filter produces above-mentioned second group of control bit according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency;
One totalizer is obtained an overhead control position with above-mentioned first group of control bit mutually with above-mentioned second group of control bit; And
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned overhead control position.
22. asynchronous first in first out interface as claimed in claim 18, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and the value that above-mentioned clock controller changes above-mentioned first group of control bit is stored in data volume in the above-mentioned impact damper with adjustment.
23. asynchronous first in first out interface as claimed in claim 22, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
24. asynchronous first in first out interface as claimed in claim 18, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and above-mentioned clock controller changes the value of above-mentioned first group of control bit, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
25. asynchronous first in first out interface as claimed in claim 18, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and above-mentioned clock controller changes the value of above-mentioned first group of control bit, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
26. asynchronous first in first out interface as claimed in claim 18, the value of wherein above-mentioned first group of control bit is determined by above-mentioned processor.
27. an interface operation method is used to operate and has an asynchronous interface that writes a clock and a readout clock, above-mentioned asynchronous interface comprises an impact damper, and said method comprises:
Receive a digital signal to above-mentioned impact damper according to the above-mentioned clock that writes from an analog-digital converter;
Export digital signal to a processor according to above-mentioned readout clock from above-mentioned impact damper;
Export one first group of control bit according to the data volume that is stored in the above-mentioned impact damper;
One concussion frequency is provided;
With above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency;
With above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency;
Export one second group of control bit by more above-mentioned reference frequency and above-mentioned incoming frequency;
Above-mentioned first group of control bit obtained an overhead control position mutually with above-mentioned second group of control bit; And
The above-mentioned readout clock of being exported according to above-mentioned overhead control position adjustment.
28. interface operation method as claimed in claim 27, wherein above-mentioned processor is a baseband processor.
29. interface operation method as claimed in claim 27, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
30. interface operation method as claimed in claim 27, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and said method comprises that also the value that changes above-mentioned first group of control bit is stored in data volume in the above-mentioned impact damper with adjustment.
31. interface operation method as claimed in claim 30, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
32. interface operation method as claimed in claim 27, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and said method also comprises the value that changes above-mentioned first group of control bit, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
33. interface operation method as claimed in claim 27, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and said method also comprises the value that changes above-mentioned first group of control bit, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
34. interface operation method as claimed in claim 27, the value of wherein above-mentioned first group of control bit is determined by above-mentioned processor.
35. an integrated receiver comprises:
One frequency synthesizer produces an output signal;
One clock system produces a mixed signal and according to above-mentioned output signal and writes clock;
One simulation RX path circuit produces a Low Medium Frequency signal according to above-mentioned mixed signal;
One Low Medium Frequency change-over circuit converts above-mentioned Low Medium Frequency signal to one first digital signal according to the above-mentioned clock that writes;
One processor is handled one second digital signal according to a readout clock; And
One asynchronous first in first out interface is coupled between above-mentioned Low Medium Frequency change-over circuit and the above-mentioned processor, and has asynchronous above-mentioned readout clock and the above-mentioned clock that writes, and comprising:
One impact damper receives above-mentioned first digital signal according to the above-mentioned clock that writes from above-mentioned digital conversion circuit, and exports above-mentioned second digital signal to above-mentioned processor according to above-mentioned readout clock;
One clock controller is according to the data volume output clock system signal in a period of time that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency; And
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, and export a control signal by more above-mentioned reference frequency and above-mentioned incoming frequency, in order to adjust the above-mentioned readout clock of being exported, wherein above-mentioned second integer divisor is controlled by above-mentioned clock control signal.
36. integrated receiver as claimed in claim 35, wherein above-mentioned processor is a Digital System Processor.
37. integrated receiver as claimed in claim 35, wherein above-mentioned concussion frequency is provided by a crystal oscillator.
38. integrated receiver as claimed in claim 35, wherein above-mentioned signal source comprises:
One divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One variable integer divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector/charge pump, more above-mentioned reference frequency and above-mentioned incoming frequency;
One loop filter produces above-mentioned controlling signal according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency, and
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned controlling signal.
39. integrated receiver as claimed in claim 35, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit or is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor and is stored in data volume in the above-mentioned impact damper with adjustment.
40. integrated receiver as claimed in claim 39, wherein above-mentioned higher limit representative data overflows signal, and above-mentioned lower limit representative data empties signal.
41. integrated receiver as claimed in claim 35, the data volume that wherein ought be stored in the above-mentioned impact damper is higher than a higher limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be lower than above-mentioned readout clock.
42. integrated receiver as claimed in claim 35, the data volume that wherein ought be stored in the above-mentioned impact damper is lower than a lower limit, and above-mentioned clock controller changes above-mentioned second integer divisor, makes the above-mentioned clock that writes be higher than above-mentioned readout clock.
43. integrated receiver as claimed in claim 35, wherein above-mentioned second integer divisor is determined by above-mentioned processor.
44. an integrated receiver comprises:
One frequency synthesizer produces an output signal;
One clock system produces a mixed signal and according to above-mentioned output signal and writes clock;
One simulation RX path circuit produces a Low Medium Frequency signal according to above-mentioned mixed signal;
One Low Medium Frequency change-over circuit converts above-mentioned Low Medium Frequency signal to one first digital signal according to the above-mentioned clock that writes;
One processor is handled one second digital signal according to a readout clock; And
One asynchronous first in first out interface is coupled between above-mentioned Low Medium Frequency change-over circuit and the above-mentioned processor, and has asynchronous above-mentioned readout clock and the above-mentioned clock that writes, and comprising:
One impact damper receives a digital signal according to the above-mentioned clock that writes from an analog-digital converter, and exports digital signal to a processor according to above-mentioned readout clock;
One clock controller is exported one first group of control bit according to the data volume that is stored in the above-mentioned impact damper;
One reference source provides a concussion frequency; And
One signal source, with above-mentioned concussion frequency divided by one first integer divisor to produce a reference frequency, with above-mentioned readout clock divided by one second integer divisor to produce an incoming frequency, export one second group of control bit by more above-mentioned reference frequency and above-mentioned incoming frequency, above-mentioned first group of control bit obtained an overhead control position mutually with above-mentioned second group of control bit, and the above-mentioned readout clock of being exported according to above-mentioned overhead control position adjustment.
45. integrated receiver as claimed in claim 44, wherein above-mentioned signal source comprises:
One first divider, with above-mentioned concussion frequency divided by above-mentioned first integer divisor to produce above-mentioned reference frequency;
One second divider, with above-mentioned readout clock divided by above-mentioned second integer divisor to produce above-mentioned incoming frequency;
One phase-frequency detector, more above-mentioned reference frequency and above-mentioned incoming frequency;
One digital loop wave filter produces above-mentioned second group of control bit according to the comparative result of above-mentioned reference frequency and above-mentioned incoming frequency;
One totalizer is obtained an overhead control position with above-mentioned first group of control bit mutually with above-mentioned second group of control bit; And
One voltage control oscillator is exported above-mentioned readout clock, and adjusts above-mentioned readout clock according to above-mentioned overhead control position.
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| JP4251094B2 (en) * | 2003-12-04 | 2009-04-08 | ヤマハ株式会社 | Asynchronous signal input device and sampling frequency converter |
| US7996704B2 (en) * | 2007-08-21 | 2011-08-09 | Richwave Technology Corp. | Asynchronous first in first out interface and operation method thereof |
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| CN110532117A (en) * | 2018-05-25 | 2019-12-03 | Arm有限公司 | For the error checking for the main signal transmitted between the first and second clock domains |
| CN110532117B (en) * | 2018-05-25 | 2023-11-03 | Arm有限公司 | Error checking for a master signal transmitted between a first and a second clock domain |
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