TWI385924B - Asynchronous first in first out interface method for operating an interface and integrated receiver - Google Patents

Description

Non-synchronous FIFO interface, interface operation method and integrated receiver

The present invention relates to a non-synchronous first in first out (FIFO) interface, and more particularly to a non-synchronous FIFO interface in a radio frequency (RF) device.

With the popularity of wireless communication (mobile phones, wireless networks), the market demand for lower cost, lower power consumption and smaller form-factor radio frequency (RF) transceivers. Increasingly eager. Recently, analog transceivers, digital processor and pulse generators have been integrated onto a single chip to meet these needs. In RF transceivers, the analog and digital circuits have different clock requirements. For example, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) require a low jitter clock to increase data conversion in analog circuits. Accuracy. However, in digital circuits, digital processors do not necessarily require low jitter clocks.

In view of this problem, the conventional circuit of Figure 1 separates the clock between the ADC and the digital processor. Figure 1 shows a block diagram of a receiver 100 using one of the asynchronous first in first out interfaces 120. The receiver 100 includes a radio frequency front end receiver 110, an analog digital converter (ADC) 112, a first signal source 114, a FIFO buffer 121, a clock controller 122, a variable integer divider 124, and a baseband. The processor 130, a second signal source 132, and a reference source 140.

The RF front end receiver 110 receives a radio frequency (RF) signal transmitted by a transmitter (not shown) and is produced in accordance with the first signal source 114. The local signal is down-converted into an intermediate frequency (IF) signal. The local signal is generated by the low jitter first signal source 114 to increase the signal to noise ratio (SNR) and to reduce adjacent channel blocking effects when down converting. The ADC 112 converts the intermediate frequency signal into data and outputs the data according to the variable frequency clock generated by the local signal to avoid the use of an additional low jitter source and to satisfy the low jitter clock. The baseband processor 130 operates the signal processing functions according to the second signal generated by the second signal source 132 on the data, for example, transmission mode detection, time domain data processing, frequency domain data processing, and channel coding. The second signal source 132 is a fixed frequency signal source, such as a ring oscillator, to reduce hardware cost. The second signal operates as a clock of the baseband processor 130. The first signal source 114 and the second signal source 132 can share a single reference source 140 to further reduce hardware cost.

The clock provided by the second source 132 to the baseband processor 130 may be asynchronous with the clock provided by the respective source to the ADC 112. Therefore, a non-synchronous FIFO interface 120 is employed in the conventional circuit of FIG. 1 to handle the transfer of the asynchronous data between the ADC 112 and the baseband processor 130. The asynchronous FIFO interface 120 includes a FIFO buffer 121, a clock controller 122, and a variable integer divider 124. The FIFO buffer 121 is coupled between the baseband processor 130 and the ADC 112 to buffer data transfer between the two. The FIFO buffer 121 receives data from the ADC 112 in accordance with a write clock and outputs data to the baseband processor 130 in accordance with a read clock. The write clock is the clock of the ADC 112 and the read clock is the clock of the baseband processor 130. When the write clock of the ADC 112 is faster than the read clock of the baseband processor 130, the data overflow of the FIFO buffer 121 is caused. The clock controller 122 therefore increments the divisor value of the variable integer divider 124 to reduce the frequency of the write clock. Conversely, the write clock of the ADC 112 is slower than the read clock of the baseband processor 130, which causes the FIFO buffer 121 to clear the data, so the clock controller 122 reduces the divisor value of the variable integer divider 124. To increase the frequency of the write clock.

In the conventional circuit of FIG. 1, the divide-by-value of the variable integer divider 124 is adjusted by the clock controller 122 to control the write clock of the ADC 112, thereby controlling the data state of the FIFO buffer 121. However, the control of the data state of the FIFO buffer 121 does not necessarily have to be adjusted by the variable integer divider 124.

In view of this, an embodiment of the present invention discloses a non-synchronous FIFO interface having a non-synchronized read clock and a write clock, including a FIFO buffer, a clock controller, a reference source, and A signal source. The FIFO buffer receives a digital signal from an analog-to-digital converter according to the write clock, and outputs a digital signal to a processor according to the read clock. The clock controller outputs a clock control signal based on the amount of data stored in the FIFO buffer. The reference source provides an oscillating frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a comparison frequency by comparing the reference frequency and the input frequency. The control signal is used to adjust the output read clock, wherein the second integer divisor is controlled by the clock control signal.

In addition, another embodiment of the present invention discloses an interface operation method for operating a non-synchronous interface having a write clock and a read clock, the non-synchronous interface including a FIFO buffer. The method includes receiving a digital signal from a class analog converter to a FIFO buffer according to a write clock. And outputting a digital signal from the FIFO buffer to a processor according to the read clock, outputting a clock control signal according to the amount of data stored in the FIFO buffer, providing an oscillation frequency, dividing the oscillation frequency by a first integer Divisor to generate a reference frequency, divide the read clock by a second integer divisor to produce an input frequency, and adjust the read clock by comparing the reference frequency and the input frequency, wherein the second integer divisor Controlled by the clock control signal.

In addition, another embodiment of the present invention discloses a non-synchronous first-in first-out interface, having a non-synchronized read clock and a write clock, including a FIFO buffer, a clock controller, a reference source, and a signal source. The FIFO buffer receives a digital signal from an analog-to-digital converter according to the write clock, and outputs a digital signal to a processor according to the read clock. The clock controller outputs a first set of control bits based on the amount of data stored in the FIFO buffer. The reference source provides an oscillating frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a first by comparing the reference frequency and the input frequency. The two sets of control bits add the first set of control bits and the second set of control bits to obtain a total control bit, and adjust the output read clock according to the total control bit.

In addition, another embodiment of the present invention discloses an interface operation method for operating a non-synchronous interface having a write clock and a read clock, the non-synchronous interface including a FIFO buffer. The method includes receiving a digital signal from a class analog converter according to a write clock to a FIFO buffer, and outputting a digital signal from the FIFO buffer to a processor according to the read clock, according to the data stored in the FIFO buffer. The quantity outputs a first set of control bits, provides an oscillation frequency, divides the oscillation frequency by a first integer divisor to generate a reference frequency, and divides the read clock by a second integer divisor. Generating an input frequency, outputting a second set of control bits by comparing the reference frequency and the input frequency, adding the first set of control bits to the second set of control bits to obtain a total control bit, and according to the overall control The bit adjusts the read clock output.

In addition, another embodiment of the present invention discloses an integrated receiver including a frequency synthesizer, a clock system, an analog receive path circuit, a low intermediate frequency conversion circuit, a processor, and an asynchronous first in first out interface. . The frequency synthesizer produces an output signal. The clock system generates a mixed signal and a write clock based on the output signal. The analog receive path circuit generates a low intermediate frequency signal based on the mixed signal. The low intermediate frequency conversion circuit converts the low intermediate frequency signal into a first digital signal according to the write clock. The processor processes a second digital signal according to a read clock. The asynchronous first-in first-out interface is coupled between the low intermediate frequency conversion circuit and the processor, and has an asynchronous read clock and a write clock, including a buffer, a clock controller, a reference source, and a signal source. The buffer receives the first digital signal from the digital conversion circuit according to the write clock, and outputs the second digital signal to the processor according to the read clock. The clock controller outputs a clock control signal based on the amount of data stored in the buffer. The reference source provides an oscillating frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a comparison frequency by comparing the reference frequency and the input frequency. The control signal is used to adjust the output read clock, wherein the second integer divisor is controlled by the clock control signal.

In addition, another embodiment of the present invention discloses an integrated receiver including a frequency synthesizer, a clock system, an analog receive path circuit, a low intermediate frequency conversion circuit, a processor, and an asynchronous first in first out interface. . The frequency synthesizer produces an output signal. The clock system generates based on the output signal A mixed signal and a write clock. The analog receive path circuit generates a low intermediate frequency signal based on the mixed signal. The low intermediate frequency conversion circuit converts the low intermediate frequency signal into a first digital signal according to the write clock. The processor processes a second digital signal according to a read clock. The asynchronous first-in first-out interface is coupled between the low intermediate frequency conversion circuit and the processor, and has an asynchronous read clock and a write clock, including a buffer, a clock controller, a reference source, and a signal source. The buffer receives the first digital signal from the digital conversion circuit according to the write clock, and outputs the second digital signal to the processor according to the read clock. The clock controller outputs a first set of control bits based on the amount of data stored in the buffer. The reference source provides an oscillating frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the read clock by a second integer divisor to generate an input frequency, and outputs a first by comparing the reference frequency and the input frequency. The two sets of control bits add the first set of control bits to the second set of control bits to obtain a total control bit, and adjust the output read clock according to the total control bit.

The above described objects, features, and advantages of the present invention will become more apparent from the aspects of the preferred embodiments illustrated herein A block diagram of one of the receivers 200 of the non-synchronous first-in first-out interface is used. The receiver 200 includes a radio frequency front end receiver 110, an analog digital converter 112, a first signal source 114, a FIFO buffer 121, a clock controller 122, a variable integer divider 124, and a baseband processor 130. a second signal source 132 and a reference source 140. Similar to the conventional architecture of FIG. 1, an asynchronous FIFO interface 220 is also used in this embodiment to process asynchronous data transfer between the ADC 112 and the baseband processor 130. a conventional architecture with Figure 1 The difference is that the non-synchronous FIFO interface 220 includes a FIFO buffer 121, a clock controller 122, a second signal source 132, and a reference source 140. The FIFO buffer 121 is coupled between the baseband processor 130 and the ADC 112 to buffer data transfer between the two. The FIFO buffer 121 receives data from the ADC 112 in accordance with a write clock and outputs data to the baseband processor 130 in accordance with a read clock. The write clock is the clock of the ADC 112 and the read clock is the clock of the baseband processor 130. When the read clock of the baseband processor 130 is slower than the write clock of the ADC 112, the data of the FIFO buffer 121 is overflowed, so the clock controller 122 outputs the frequency of the read clock of the second signal source 132. Increased to increase the read clock of the baseband processor 130. Conversely, when the read clock of the baseband processor 130 is faster than the write clock of the ADC 112, the data of the FIFO buffer 121 is cleared. Therefore, the clock controller 122 outputs the output of the second signal source 132. The frequency of the pulses is reduced to reduce the read clock of the baseband processor 130. By controlling the output of the second source 132 to read the clock, the balance of the write clock with the ADC 112 can be maintained without overflowing or emptying the data of the FIFO buffer 121. The above is a brief description of the invention, and detailed implementation details thereof are described below.

FIG. 3A is a block diagram showing a second signal source according to an embodiment of the invention. The second signal source 132A can be a synthesizer, including a variable integer divider 1321, a phase frequency detector/Phase Frequency Detector/Charge Pump (PFD/CP) 1322, and a loop filter. A loop filter 1323, a Voltage-Controlled Oscillator (VCO) 1324, and a divider 1325. In FIG. 3A, the clock frequency CLK_BB1 is supplied to the clock of the baseband processor 130, and the FIFO buffer 121 outputs data to the baseband processor 130 in accordance with the clock frequency CLK_BB1. Therefore, when the data state in the FIFO buffer 121 is unbalanced (the data is too full or empty), the magnitude of the clock frequency CLK_BB1 can be adjusted. In FIG. 3A, the variable integer divider 1321 has a function of dividing the clock frequency CLK_BB1 of the baseband processor 130 by an integer M, wherein the value of M is determined by the clock controller 122. After the variable integer divider 1321 divides the clock frequency CLK_BB1 of the baseband processor 130 by the integer M, the output frequency (CLK_BB1/M) is transmitted to the PFD/CP 1322 as its input frequency f _in1 . On the other hand, the divider 1325 receives the oscillation frequency f _{xta1 of the} reference source 140 and divides it by an integer value N to output the reference frequency f _ref1 . The oscillating frequency f _{xta1 of the} reference source 140 can be generated by a crystal oscillator (Crystal). The PFD/CP 1322 receives the input frequency f _in1 and the reference frequency f _ref1 , detects/compares the difference between the two and sends the result to the loop filter 1323. The loop filter 1323 sends a control signal to the VCO 1324, so that the VCO 1324 Adjust the clock frequency CLK_BB1 that it outputs. When the frequency of the pulse frequency CLK_BB1 is stable, the value is (M/N) times the reference source 140 oscillation frequency f _xta1 . The clock controller 122 can adjust the divisor value (M) of the variable integer divider 1321 according to the data state of the FIFO buffer 121, thereby adjusting the clock frequency CLK_BB1 of the VCO 1324 output to the baseband processor 130. For example, when the amount of data stored in the FIFO buffer 121 is higher than an upper limit value, it means that the amount of data in the FIFO buffer 121 may reach an overfull state, so the clock controller 122 can adjust the variable integer. The divide value (M) of the divider 1321 is increased in magnitude to increase the clock frequency CLK_BB1. In this way, the FIFO buffer 121 outputs the data to the baseband processor 130 according to the increased clock frequency CLK_BB1, and the speed at which the baseband processor 130 reads the data from the FIFO buffer 121 is raised. The increased clock frequency CLK_BB1 may be greater than the speed at which the ADC 112 writes to the FIFO buffer 121 to solve the problem that the data in the FIFO buffer 121 is too full. Similarly, when the amount of data stored in the FIFO buffer 121 is lower than the lower limit value, the amount of data in the FIFO buffer 121 may reach the over-empty state, so the clock controller 122 can adjust the variable integer divider 1321. Divide the value (M) to reduce the clock frequency CLK_BB1. In this way, the FIFO buffer 121 outputs the data to the baseband processor 130 according to the reduced clock frequency CLK_BB1, reducing the speed at which the baseband processor 130 reads data from the FIFO buffer 121. The reduced clock frequency CLK_BB1 may be smaller than the speed at which the ADC 112 writes to the FIFO buffer 121 to solve the situation in which the data in the FIFO buffer 121 is cleared. It should be noted that although the above embodiment refers to the clock controller 122 adjusting the divisor value (M) of the variable integer divider 131 according to the data state of the FIFO buffer 121, the VCO 1324 output is adjusted to the baseband processor 130. The clock frequency CLK_BB1, however, in another embodiment of the present invention, the divisor value (M) size of the variable integer divider 1321 may also be determined by the baseband processor 130 based on current data processing conditions. That is, the baseband processor 130 can also adjust its clock frequency by the clock controller 122.

Figure 3B is a block diagram showing a second signal source in accordance with another embodiment of the present invention. The second signal source 132B can be a synthesizer, including a divider 1421, a Phase Frequency Detector (PFD) 1422, a digital loop filter 1423, an adder 1424, and a digital voltage. A Digital Voltage-Controlled Oscillator (DCO) 1425 and a divider 1426 are provided. As in the embodiment of FIG. 3A, the clock frequency CLK_BB2 is the clock of the baseband processor 130, and the FIFO buffer 121 outputs the data to the baseband processor 130 in accordance with the clock frequency CLK_BB2. Therefore, when the data status in the FIFO buffer 121 is unbalanced (data is too full or empty), the size of the clock frequency CLK_BB2 can be adjusted. However, unlike the embodiment of FIG. 3A, the implementation architecture of the second signal source of FIG. 3B is a digital bit, as described below. In FIG. 3B, the divider 1421 has a function of dividing the clock frequency CLK_BB2 of the baseband processor 130, and sends the output frequency to the PFD 1422 as its input frequency f _in2 . Further, the divider 1426 receives the oscillation frequency f _{xta1 of the} reference source 140 and divides it to output the reference frequency f _ref2 . The oscillating frequency f _{xta1 of the} reference source 140 can be generated by a crystal oscillator. The PFD 1422 receives the input frequency f _in2 and the reference frequency f _ref2 , detects/compares the difference between the two and sends the result to the digital loop filter 1423, and the digital loop filter 1423 sends a set of control bits. The adder 1424 is provided. The adder 1424 also receives another set of control bits output by the clock controller 122, and adds the two sets of control bits to a total control bit to the DCO 1425, such that the DCO 1425 adjusts its output to the baseband processor 130. The clock frequency is CLK_BB2. For example, when the amount of data stored in the FIFO buffer 121 is higher than an upper limit value, it means that the amount of data in the FIFO buffer 121 may reach an overfull state, so the clock controller 122 can adjust its output. The value of the control bit (eg, the value given to the larger control bit) is added to increase the clock frequency CLK_BB2. In this way, the FIFO buffer 121 outputs the data to the baseband processor 130 according to the increased clock frequency CLK_BB2, and the speed at which the baseband processor 130 reads the data from the FIFO buffer 121 is raised. The increased clock frequency CLK_BB2 may be greater than the speed at which the ADC 112 writes to the FIFO buffer 121 to solve the problem that the data in the FIFO buffer 121 is too full. Similarly, when the amount of data stored in the FIFO buffer 121 is lower than the lower limit value, the amount of data representing the FIFO buffer 121 may have reached an empty state, so the clock controller 122 can adjust the control bit of its output. The value (eg, the value given to the smaller control bit) is used to reduce the clock frequency CLK_BB2. In this way, the FIFO buffer 121 outputs the data to the baseband processor 130 according to the reduced clock frequency CLK_BB2, reducing the speed at which the baseband processor 130 reads data from the FIFO buffer 121. The reduced clock frequency CLK_BB2 may be smaller than the speed at which the ADC 112 writes to the FIFO buffer 121 to solve the situation in which the data in the FIFO buffer 121 is cleared. As with the embodiment of FIG. 3A, the value of the control bit output by the clock controller 122 can also be determined by the baseband processor 130 based on the current data processing conditions. That is, the baseband processor 130 can also adjust its clock frequency by the clock controller 122. It must be noted that in this embodiment, the output value to the digital loop filter 1423 is required only in the initial state of the circuit, and the value of the digital loop filter 1423 is latched in the subsequent operation and no longer changes. . Instead, the clock controller 122 adjusts the value of the control bit that it outputs based on the data state of the FIFO buffer 121, thereby adjusting the value of the total control bit. As such, the DCO 1425 can dynamically adjust its output to the clock frequency CLK_BB2 of the baseband processor 130 based on the total control bits. More specifically, when the data status of the FIFO buffer 121 is close to the data overflow (the data exceeds the upper limit value), the clock controller 122 can output the value of the positive second control bit, so that the output of the adder 1424 is larger. The total control bit is given to the DCO 1425, which in turn causes the DCO 1425 to increase the clock frequency CLK_BB2 of its output. Conversely, when the data status of the FIFO buffer 121 is close to data clear (data below the lower limit), the clock controller 122 may output a value of the negative second control bit such that the adder 1424 outputs a smaller value. The total control bit is applied to the DCO 1425, which in turn causes the DCO 1425 to decrease the clock frequency CLK_BB2 of its output. In the above two embodiments, the case where the data in the FIFO buffer 121 is overfilled or emptied is mentioned. The state in which the data in the FIFO buffer 121 is incremented or decremented will be briefly described below.

Fig. 4A shows the amount of data decrementing in the FIFO buffer 121. For example, the frequency of the write clock is 4/T and the frequency of the read clock is 5/T. The read speed of the FIFO buffer is faster than the write clock of the FIFO buffer 121, so the amount of data is decremented during each T period. Referring to FIG. 4A, FIFO_R indicates that the FIFO buffer 121 reads data in this area, FIFO_W indicates that the FIFO buffer 121 writes data in this area, and black dots indicate that the data is stored in the buffer. 410 represents the time t _o to the FIFO buffer shown in 121,412 t _o + T when the FIFO buffer 121, and 414 at t _o + represents a FIFO buffer 121 at the time of 2T. When the amount of data falls below the lower limit, the empty signal of the FIFO buffer will be pulled high and the "error happened" message will be sent in the next period.

Fig. 4B shows the amount of data in the FIFO buffer 121 incremented. For example, the frequency of the write clock is 6/T and the frequency of the read clock is 5/T. The amount of data will increase during each T period. Referring to Figure 4B, shown in the FIFO buffer 420 to ₁ 121,422 t of _{t. 1} shown in the FIFO buffer 121 at the time of T + _{t. 1} and 424 shown in FIFO buffer 121 when the 4T +. When the amount of data exceeds the upper limit, the full signal of the FIFO buffer will be pulled high and an "error occurred" message will be sent in the next period.

As described above, when the read clock and the write clock are not synchronized, the FIFO buffer may encounter a problem of over- or over-empty resulting in a data transfer error. However, it can be avoided by controlling the frequency of the read clock. FIG. 5 is a diagram showing an interface operation method according to an embodiment of the present invention for operating a non-synchronous FIFO interface 220 having a write clock and a read clock as shown in FIG. 2, and using FIG. 3A together. The second signal source 132A. First, in step S50, a digital signal is received from the ADC 112 to the FIFO buffer 121 in accordance with the write clock. In step S51, a digital signal is output from the FIFO buffer 121 to the baseband processor 130 based on the read clock. In step S52, an oscillation frequency f _{xta1 is} provided by the reference source 140. In step S53, the divider 1325 in Fig. 3A divides the oscillation frequency by the first integer divisor N to generate a reference frequency f _ref1 . In step S54, the variable integer divider 1321 in Fig. 3A divides the read clock by a second integer divisor M to generate an input frequency f _in1 . In step S55, the phase frequency detector/charge pump 1322 compares the reference frequency f _ref1 with the input frequency f _in1 , and the loop filter 1323 outputs a control signal according to the comparison result. In step S56, the voltage controlled oscillator 1324 in Fig. 3A adjusts the output read clock according to the control signal. In the flowchart of FIG. 5, the second integer divisor M is controlled by the clock control signal, that is, when the read clock is too low, causing the asynchronous FIFO interface 220 to be oversized, the second integer is adjusted. Divide the value of M to increase the frequency of the read clock and vice versa.

FIG. 6 is a diagram showing an interface operation method according to another embodiment of the present invention, for operating the non-synchronous FIFO interface 220 having a write clock and a read clock as shown in FIG. 2, and using the third BB. The second signal source 132B is illustrated. First, in step S60, a digital signal is received from the ADC 112 to the FIFO buffer 121 in accordance with the write clock. In step S61, a digital signal is output from the FIFO buffer 121 to a baseband processor 130 based on the read clock. In step S62, the first group of control bits is output based on the amount of data stored in the FIFO buffer 121. In step S63, an oscillation frequency f _{xta1 is} supplied from the reference source. In step S64, the divider 1426 of Fig. 3B divides the oscillation frequency f _xta1 by a first integer divisor to generate a reference frequency f _ref2 . In step S65, the divider 1421 of Fig. 3B divides the read clock by a second integer divisor to produce an input frequency f _in2 . In step S66, the reference frequency f _ref2 and the input frequency f _{in2 are} compared. In step S67, a second set of control bits is output based on the comparison result. In step S68, the adder 1424 of FIG. 3B adds the first set of control bits to the second set of control bits to obtain a total control bit. In step S69, the digital voltage controlled oscillator 1425 of Fig. 3B will adjust the output read clock according to the total control bit. More precisely, when the FIFO buffer 121 is close to the state in which the data is cleared, the first group of control bits outputted in step S62 can be negative, so that the added total control bits become smaller and the output read is lowered. Out of the clock. Conversely, when the FIFO buffer 121 is close to the state in which the data overflows, the first group of control bits outputted in step S62 can be positive, so that the added total control bits become larger and the output readout is increased. pulse.

In addition, although disclosed in the embodiment of the present invention, the clock controller 122 performs the corresponding adjustment action according to the data amount state in the FIFO buffer 121. However, in another embodiment of the present invention, the clock control The action of the device 122 can be determined by the baseband processor 130. That is, the baseband processor 130 can inform the clock controller 122 to increase or decrease the current clock frequency according to the current data processing situation.

FIG. 7 is a circuit diagram showing the actual application of the receiver 200 according to an embodiment of the invention. In Fig. 7, in addition to the set front end receiver 110 of the front end of the ADC 112, a speaker 150 at the rear end of the digital-to-analog converter (DAC) 212 is further included. The non-synchronous FIFO interface 220 further includes a FIFO buffer 221 at the output. Same principle as above, FIFO buffer The 221 receives data from the baseband processor 130 according to the clock of the baseband processor 130, and outputs the data to the DAC 212 according to the readout clock output by the fixed divider 224, and transmits the related audio data to the horn. 150.

Furthermore, the invention is also applicable to integrated receivers. Figure 8A shows a representative diagram of an integrated receiver 800A in accordance with an embodiment of the invention, wherein a low noise amplifier (LNA) 102 is part of an analog receive path circuit. The LNA 102 outputs a signal to the mixer 104 based on the received RF signal 113. The mixer 104 generates a low intermediate frequency (low-IF) signal 116 to the low-IF conversion circuitry 106 based on a mixed signal 118. The low intermediate frequency conversion circuit 106 digitizes the received low intermediate frequency signal 116 according to a digital sampling clock signal 205, and outputs the digital signal 120 to a digital signal processor (DSP) 108. The DSP 108 processes the digital signal 120 based on a digital clock signal (which is also signal 205 in this figure, but not in the application of the 800B picture described later). In the circuit of FIG. 800A, the mixed signal 118, the digital sampling clock signal 205 (belonging to the low intermediate frequency converting circuit 106), and the digital clock signal 205 (belonging to the DSP 108) are generated by a clock system 300, wherein the clock is generated. System 300 includes dividers 132, 202, and 204. The clock system 300 receives the frequency f _OSC generated by the frequency synthesizer 209 and uses the dividers 132, 204, and 202 to generate the mixed signal 118, the digital sample clock signal 205, and the digital clock signal 205. The asynchronous first in first out interface 220 of the present invention can be applied between the low intermediate frequency conversion circuit 106 and the DSP 108 as shown in FIG. 800B.

In the example of applying the asynchronous first in first out interface 220 of the present invention in FIG. 800B, the FIFO buffer 121 in the asynchronous first in first out interface 220 Receiving the digital signal 120A from the low intermediate frequency conversion circuit 106 according to the write clock and outputting the digital signal 120B to the DSP 108 according to the read clock, and buffering the low intermediate frequency conversion circuit 106 and the DSP 108 according to the data state of the FIFO buffer 121. The reading and writing of data between the two, the operating principle is exactly the same as the above, so the description will not be repeated here.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ Receiver

102‧‧‧Low noise amplifier

104‧‧‧Mixer

106‧‧‧Low intermediate frequency conversion circuit

108‧‧‧Digital Signal Processor

110‧‧‧RF front-end receiver

112‧‧‧ Analog Digital Converter

113‧‧‧RF signal

114, 132, 132A, 132B‧‧‧ signal source

116‧‧‧Low IF signal

121, 221‧‧‧ FIFO buffer

120, 220‧‧‧ Non-synchronous FIFO interface

120A, 120B‧‧‧ digital signal

122‧‧‧clock controller

124‧‧‧Variable integer divider

130‧‧‧baseband processor

132, 204, 1325‧‧‧ divider

140‧‧‧Reference source

150‧‧‧ Horn

209‧‧‧ frequency synthesizer

212‧‧‧Digital Analog Converter

224‧‧‧Fixed divider

300‧‧‧ clock system

410, 412, 414, 420, 422, 424‧‧ ‧ buffers

800A, 800B‧‧‧ integrated receiver

1321‧‧‧Variable integer divider

1322‧‧‧ phase frequency detector / charge pump

1323‧‧‧ Loop Filter

1324‧‧‧Voltage Control Oscillator

CLK_BB1, CLK_BB2‧‧‧ clock frequency

f _OSC ‧‧‧frequency synthesizer output frequency

f _xta1 ‧‧‧ oscillation frequency

F _in1 , F _in2 ‧‧‧ input frequency

F _ref1 , F _ref2 ‧‧‧reference frequency

FIFO_R‧‧‧ reading data

FIFO_W‧‧‧Write data

1 is a block diagram showing a receiver using a non-synchronous first-in first-out interface; and FIG. 2 is a block diagram showing a receiver using an asynchronous first-in first-out interface according to an embodiment of the invention; A block diagram of a second signal source according to an embodiment of the invention is shown; FIG. 3B is a block diagram showing a second signal source according to another embodiment of the present invention; and FIG. 4A is a diagram showing an embodiment of the present invention. FIG. 4B is a schematic diagram showing an increase in data amount in a FIFO buffer according to an embodiment of the present invention; FIG. 5 is a view showing an interface according to an embodiment of the present invention; 6 shows a circuit operation method according to another embodiment of the present invention; FIG. 7 shows a circuit diagram of a receiver according to an embodiment of the present invention; and FIG. 8A shows an integrated receiver The circuit diagram; and FIG. 8B shows an example in which the non-synchronous first-in first-out interface of the present invention is applied to the integrated receiver of FIG. 8A.

200‧‧‧ Receiver

110‧‧‧RF front-end receiver

112‧‧‧ Analog Digital Converter

114, 132‧‧‧ Signal source

121‧‧‧FIFO buffer

122‧‧‧clock controller

124‧‧‧Variable integer divider

130‧‧‧baseband processor

140‧‧‧Reference source

220‧‧‧ Non-synchronous FIFO interface

Claims (36)

An asynchronous first in first out interface having a non-synchronized read clock and a write clock, comprising: a buffer for receiving a digital signal from an analog converter according to the write clock, and according to the above The read clock outputs a digital signal to a processor; a clock controller outputs a clock control signal according to the amount of data stored in the buffer; a reference source provides an oscillation frequency; and a signal source, The oscillating frequency is divided by a first integer divisor to generate a reference frequency, the read clock is divided by a second integer divisor to generate an input frequency, and the output is output by comparing the reference frequency with the input frequency a control signal for adjusting the output read clock, wherein the second integer divisor is controlled by the clock control signal, wherein the signal source comprises: a divider, dividing the oscillation frequency by the first An integer divisor to generate the reference frequency; a variable integer divider controlled by the clock control signal to divide the readout clock by the second integer Divising to generate the above input frequency; a phase frequency detector/charge pump comparing the reference frequency and the input frequency; and a loop filter generating the control signal according to a comparison result between the reference frequency and the input frequency, and A voltage controlled oscillator outputs the read clock and adjusts the read clock according to the control signal. As described in the scope of patent application, the non-synchronous advanced first-out media The above processor is a base band processor. The non-synchronous first-in first-out interface as described in claim 1 wherein the oscillating frequency is provided by a crystal oscillator. The non-synchronous first-in first-out interface as described in claim 1, wherein the clock controller changes the second when the amount of data stored in the buffer is higher than an upper limit or lower than a lower limit The integer divisor is used to adjust the amount of data stored in the buffer. For example, the non-synchronous first-in first-out interface described in claim 4, wherein the upper limit value represents a data overflow signal, and the lower limit value represents a data clear signal. The non-synchronous first-in first-out interface as described in claim 1, wherein when the amount of data stored in the buffer is higher than an upper limit, the clock controller changes the second integer divisor such that The write clock is lower than the above read clock. The non-synchronous first-in first-out interface as described in claim 1, wherein when the amount of data stored in the buffer is lower than a lower limit, the clock controller changes the second integer divisor to cause the writing The incoming clock is higher than the above read clock. An interface operation method for operating a non-synchronous interface having a write clock and a read clock, the non-synchronous interface including a buffer, the method comprising: converting from an analog to digital according to the write clock Receiving a digital signal to the buffer; outputting a digital signal from the buffer to a processor according to the read clock; outputting a clock control according to the amount of data stored in the buffer a frequency; providing a oscillating frequency; dividing the oscillating frequency by a first integer divisor by a divider to generate a reference frequency; and using a variable integer divider controlled by the clock control signal The read clock is divided by a second integer divisor to generate an input frequency, and the read clock is adjusted by comparing the reference frequency with the input frequency, wherein the read frequency is adjusted by comparing the reference frequency with the input frequency The step of reading the clock includes: comparing the reference frequency and the input frequency by a phase frequency detector/charge pump; generating a comparison result between the reference frequency and the input frequency by using a loop filter The control signal is outputted by the voltage control oscillator, and the read clock is output, and the read clock is adjusted according to the control signal. The interface operation method of claim 8, wherein the processor is a baseband processor. The interface operation method of claim 8, wherein the oscillation frequency is provided by a crystal oscillator. The interface operation method of claim 8, wherein the method further comprises: changing the second integer divisor when the amount of data stored in the buffer is higher than an upper limit or lower than a lower limit To adjust the amount of data stored in the buffer. An interface operation method as described in claim 11 of the patent application, The above upper limit value represents a data overflow signal, and the above lower limit value represents a data clear signal. The interface operation method of claim 8, wherein when the amount of data stored in the buffer is higher than an upper limit, the method further comprises changing the second integer divisor such that the write clock is Below the readout clock. The interface operation method of claim 8, wherein when the amount of data stored in the buffer is lower than a lower limit, the method further comprises changing the second integer divisor such that the write clock is high. Read the clock at the above. An asynchronous first in first out interface having a non-synchronized read clock and a write clock, comprising: a buffer for receiving a digital signal from an analog converter according to the write clock, and according to the above The read clock outputs a digital signal to a processor; a clock controller outputs a first set of control bits according to the amount of data stored in the buffer; a reference source provides an oscillation frequency; a signal source, Dividing the oscillation frequency by a first integer divisor to generate a reference frequency, dividing the readout clock by a second integer divisor to generate an input frequency, and outputting by comparing the reference frequency and the input frequency a second group of control bits, the first group of control bits are added to the second group of control bits to obtain a total control bit, and the output read clock is adjusted according to the total control bit. Wherein the signal source comprises: a first divider, dividing the oscillation frequency by the first integer division And generating a reference frequency; a second divider dividing the read clock by the second integer divisor to generate the input frequency; and a phase frequency detector comparing the reference frequency and the input frequency; a digital loop filter, generating the second group of control bits according to the comparison result of the reference frequency and the input frequency; and an adder, adding the first group of control bits to the second group of control bits to obtain the total a control bit; and a voltage controlled oscillator that outputs the read clock and adjusts the read clock according to the total control bit. The non-synchronous first-in first-out interface as described in claim 15 wherein the processor is a baseband processor. The non-synchronous first-in first-out interface as described in claim 15 wherein the oscillation frequency is provided by a crystal oscillator. The non-synchronous first-in first-out interface according to claim 15 , wherein the clock controller changes the first when the amount of data stored in the buffer is higher than an upper limit or lower than a lower limit The group controls the value of the bit to adjust the amount of data stored in the buffer. For example, the non-synchronous first-in first-out interface described in claim 18, wherein the upper limit value represents a data overflow signal, and the lower limit value represents a data clear signal. The non-synchronous first-in first-out interface as described in claim 15 wherein the clock controller changes the value of the first group of control bits when the amount of data stored in the buffer is higher than an upper limit value. So that the above write clock is lower than the above read clock. The non-synchronous first-in first-out interface according to claim 15 , wherein when the amount of data stored in the buffer is lower than a lower limit, the clock controller changes the value of the first group of control bits, The write clock is made higher than the read clock. An interface operation method for operating a non-synchronous interface having a write clock and a read clock, the non-synchronous interface including a buffer, the method comprising: converting from an analog to digital according to the write clock Receiving a digital signal to the buffer; outputting a digital signal from the buffer to a processor according to the read clock; outputting a first group of control bits according to the amount of data stored in the buffer; providing a An oscillating frequency; dividing the oscillating frequency by a first integer divisor by a first divider to generate a reference frequency; dividing the read clock by a second integer by a second divider Generating an input frequency; comparing a reference frequency and the input frequency to output a second set of control bits by a phase frequency detector and a digital loop filter; and using the adder, the first The group control bit is added to the second group of control bits to obtain a total control bit; and the output is read by the voltage control oscillator according to the total control bit Pulse. The interface operation method of claim 22, wherein the processor is a baseband processor. The interface operation method of claim 22, wherein the oscillation frequency is provided by a crystal oscillator. The interface operation method of claim 22, wherein the method further comprises changing the first group of control bits when the amount of data stored in the buffer is higher than an upper limit or lower than a lower limit. The value of the data is adjusted to be stored in the buffer. The interface operation method as described in claim 25, wherein the upper limit value represents a data overflow signal, and the lower limit value represents a data clear signal. The interface operation method of claim 22, wherein when the amount of data stored in the buffer is higher than an upper limit, the method further comprises changing a value of the first group of control bits to cause the writing The incoming clock is lower than the above read clock. The interface operation method of claim 22, wherein when the amount of data stored in the buffer is lower than a lower limit, the method further comprises changing a value of the first group of control bits to cause the writing The clock is higher than the above read clock. An integrated receiver comprising: a frequency synthesizer for generating an output signal; a clock system for generating a mixed signal and a write clock according to the output signal; and an analog receiving path circuit for generating a low according to the mixed signal An intermediate frequency signal; a low intermediate frequency conversion circuit that converts the low intermediate frequency signal into a first digital signal according to the writing clock; and a processor that processes a second digital signal according to a read clock; And an asynchronous first-in first-out interface coupled between the low-IF conversion circuit and the processor, and having the asynchronous read clock and the write clock, including: a buffer, according to the foregoing The write clock receives the first digital signal from the low intermediate frequency conversion circuit, and outputs the second digital signal to the processor according to the read clock; a clock controller, according to the data stored in the buffer Outputting a clock control signal; a reference source providing an oscillation frequency; and a signal source dividing the oscillation frequency by a first integer divisor to generate a reference frequency, dividing the readout clock by a second An integer divisor to generate an input frequency, and outputting a control signal for comparing the output read clock by comparing the reference frequency with the input frequency, wherein the second integer divisor is the clock Controlled by the control signal, wherein the signal source comprises: a divider, dividing the oscillation frequency by the first integer divisor to generate the reference frequency; a divider controlled by the clock control signal for dividing the readout clock by the second integer divisor to generate the input frequency; a phase frequency detector/charge pump for comparing the reference frequency and The input frequency; the first loop filter generates the control signal according to the comparison result between the reference frequency and the input frequency, and a voltage controlled oscillator, outputs the read clock, and according to the above The control signal adjusts the above read clock. The integrated receiver of claim 29, wherein the processor is a digital signal processor. The integrated receiver of claim 29, wherein the oscillating frequency is provided by a crystal oscillator. The integrated receiver of claim 29, wherein the clock controller changes the second integer division when the amount of data stored in the buffer is higher than an upper limit value or lower than a lower limit value The number is used to adjust the amount of data stored in the buffer. The integrated receiver according to claim 32, wherein the upper limit value represents a data overflow signal, and the lower limit value represents a data clear signal. The integrated receiver of claim 29, wherein when the amount of data stored in the buffer is higher than an upper limit, the clock controller changes the second integer divisor to cause the writing The clock is lower than the above read clock. The integrated receiver of claim 29, wherein when the amount of data stored in the buffer is lower than a lower limit, the clock controller changes the second integer divisor such that the writing is performed The pulse is higher than the above read clock. An integrated receiver comprising: a frequency synthesizer for generating an output signal; a clock system for generating a mixed signal and a write clock according to the output signal; and an analog receiving path circuit for generating a low according to the mixed signal IF signal; a low intermediate frequency conversion circuit for converting the low intermediate frequency signal into a first digital signal according to the writing clock; a processor for processing a second digital signal according to a read clock; and an asynchronous first in first out The interface is coupled between the low intermediate frequency conversion circuit and the processor, and has a non-synchronized read clock and the write clock, and includes: a buffer, according to the write clock from the low The intermediate frequency conversion circuit receives a digital signal, and outputs a digital signal to the processor according to the read clock; the clock controller outputs a first set of control bits according to the amount of data stored in the buffer; a reference source providing an oscillating frequency; and a signal source dividing the oscillating frequency by a first integer divisor to generate a reference frequency, dividing the read clock by a second integer divisor to generate an input frequency And outputting a second group of control bits by comparing the reference frequency and the input frequency, and adding the first group of control bits to the second group of control bits to obtain a total control bit And adjusting the output read clock according to the total control bit, wherein the signal source comprises: a first divider, dividing the oscillation frequency by the first integer divisor to generate the reference frequency; a second divider dividing the read clock by the second integer divisor to generate the input frequency; a phase frequency detector comparing the reference frequency and the input frequency; a digital loop filter, generating the second group of control bits according to the comparison result of the reference frequency and the input frequency; and an adder, adding the first group of control bits to the second group of control bits to obtain the above a total control bit; and a voltage controlled oscillator that outputs the read clock and adjusts the read clock according to the total control bit.