CN102054864A - LDMOS (laterally diffused metal oxide semiconductor) and manufacturing method thereof - Google Patents

LDMOS (laterally diffused metal oxide semiconductor) and manufacturing method thereof Download PDF

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CN102054864A
CN102054864A CN2009102017538A CN200910201753A CN102054864A CN 102054864 A CN102054864 A CN 102054864A CN 2009102017538 A CN2009102017538 A CN 2009102017538A CN 200910201753 A CN200910201753 A CN 200910201753A CN 102054864 A CN102054864 A CN 102054864A
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trap
doping
type
ldmos
groove
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CN102054864B (en
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张帅
戚丽娜
吕赵鸿
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

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Abstract

The invention discloses a LDMOS. Based on the traditional LDMOS (laterally diffused metal oxide semiconductor) structure, a light dope area (30) is arranged on the side wall and the bottom close to a groove (13) in a well (12). The doping types of the light dope area (30) and the well (12) are the same and the doping density of the light dope area (30) is lower. The invention also discloses a manufacturing method of an LDMOS. The shifting area of the traditional LDMOS is the well (12) but the shifting area of the LDMOS provided by the invention is the well (12) and the light dope area (30), so that the electric field along vertical and horizontal directions of the groove in the LDMOS provided by the invention is conveniently reduced, therefore reducing the electron collision strength in the shifting area, restraining the hot carrier injection effect, and increasing the safety working area and reliability of the LDMOS device.

Description

LDMOS and manufacture method thereof
Technical field
The present invention relates to a kind of electronic device and manufacture method thereof, particularly relate to a kind of LDMOS and manufacture method thereof.
Background technology
LDMOS (laterally diffused MOSFET, laterally diffused MOS transistor) is widely used in the power amplifier of radio frequency, microwave regime.
See also Fig. 1, this is the existing structure schematic diagram of the n type LDMOS of a kind of BCD (bipolar, CMOS and DMOS) of using technology manufacturing.Respectively p type epitaxial loayer 11 and n trap 12 on p type silicon substrate 10.The thickness of n trap 12 for example is 4～5 μ m.Have groove 13, p trap 16 and n type heavy doping drain region 22 in the n trap 12.P trap 16 and n type heavy doping drain region 22 do not coincide in the both sides of groove 13 and all respectively (promptly all with groove 13 at a distance of certain distance) with groove 13.The sidewall of groove 13 and bottom have cushion oxide layer 14, are filled with shallow groove isolation structure 15 in the groove 13.Have n type heavy doping source region 21 and n type light doping section 19 in the p trap 16, the doping content in n type heavy doping source region 21 is greater than the doping content of n type light doping section 19.The doping content in n type heavy doping drain region 22 is greater than the doping content of n trap 12.Be respectively gate oxide 17 and polysilicon gate 18 on the n trap 12, a side of polysilicon gate 18 is above shallow groove isolation structure 15, and opposite side is above p trap 16.The both sides of polysilicon gate 18 have side wall 20a, and the top has medium 20b, and side wall 20a, medium 20b constitute the isolation structure of polysilicon gate 18 with gate oxide 17.The drift region of this LDMOS is a n trap 12.
The existing structure of p type LDMOS is identical with n type LDMOS, and just the doping type of each several part is opposite.
The manufacture method of above-mentioned LDMOS comprises the steps, is example with n type LDMOS:
In the 1st step, see also Fig. 2 a, epitaxial growth one deck p type epitaxial loayer 11 on p type substrate 10, in p type epitaxial loayer 11, inject n type impurity again, thereby the surface at p type epitaxial loayer 11 forms the high n trap 12 of doping content, and ion carries out high annealing after injecting, and n trap 12 final thickness are about 4～5 μ m.Usually after ion implantation technology, all can carry out high temperature furnace annealing or rapid thermal annealing (RTA) technology, will indicate annealing process no longer especially after other ion implantation technologies in the present specification.
The 2nd step, see also Fig. 2 b, earlier etch a groove 13 with shallow-trench isolation (STI) technology on n trap 12 surfaces, sidewall and bottom oxidation growth one deck cushion oxide layer 14 at groove 13, again with chemical vapor deposition (CVD) technology at silicon chip surface deposit one deck silica, this layer silica to major general's groove 13 is filled full, is ground to and n trap 12 upper surface flush with the silica of chemico-mechanical polishing (CMP) technology with institute's deposit at last, has formed shallow groove isolation structure 15 this moment in groove 13.
Carry out p type ion and inject, form p trap 16 in n trap 12, p trap 16 is in a side of shallow groove isolation structure 15 and have certain distance between the two.
The 3rd step saw also Fig. 2 c, earlier at silicon chip surface growth one deck silica, and deposit one deck polysilicon on silica again, thus this layer of etching polysilicon and silica form polysilicon gate 18 and gate oxide 17.One side of polysilicon gate 18 is on shallow groove isolation structure 15, and opposite side is on p trap 16.The lightly doped drain that carries out n type impurity near a side of p trap 16 at polysilicon gate 18 injects (LDD), thereby forms n type light doping section 19 in p trap 16.
At silicon chip surface deposit one deck medium, this layer medium is higher than the upper surface of polysilicon gate 18.Anti-carve this layer medium, form side wall 20a in the both sides of polysilicon gate 18, form medium 20b above polysilicon gate 18, side wall 20a and medium 20b are connected as a single entity.The side of side wall 20a is on shallow groove isolation structure 15, and opposite side is on p trap 16.
The 4th step saw also Fig. 1, and the heavy-doped source that carries out n type impurity near a side of p trap 16 at side wall 20a injects, thereby formed n type heavy doping source region 21 in p trap 16, and the doping content in n type heavy doping source region 21 is greater than the doping content of n type light doping section 10.Leak injection in the heavy doping that shallow groove isolation structure 15 carries out n type impurity away from a side of p trap 16, thereby in n trap 12, form n type heavy doping drain region 22, the doping content in n type heavy doping drain region 22 has certain distance greater than the doping content of n trap 12 between n type heavy doping drain region 22 and the shallow groove isolation structure 15.
The drift region of above-mentioned LDMOS is a n trap 12, the source end also comprises n type light doping section 19 except n type heavy doping source region 21, n type heavy doping drain region 22 is arranged in n trap 12, and these structures all help to improve the hot carrier injection effect (Hot Carrier Injection Effect) of LDMOS.When the drain terminal voltage of above-mentioned LDMOS device is higher, the charge carrier of channel region (electronics and hole) is still than being easier to obtain kinetic energy, thereby be injected in the top gate oxide, the threshold voltage shift, mutual conductance reduction, driving force that causes the LDMOS device descend can performance parameter decline.
Summary of the invention
Technical problem to be solved by this invention provides a kind of LDMOS device, can effectively improve the hot carrier injection effect problem of existing LDMOS device.The present invention provides the manufacture method of described LDMOS device in addition for this reason.
For solving the problems of the technologies described above, LDMOS of the present invention comprises substrate 10, epitaxial loayer 11 and trap 12 from bottom to top respectively, and epitaxial loayer 11 is identical with the doping type of substrate 10, and trap 12 is opposite with the doping type of epitaxial loayer 11;
Have groove 13, trap 16 and heavy doping drain region 22 in the trap 12, trap 16 and heavy doping drain region 22 do not coincide with groove 13 in the both sides of groove 13 and all respectively;
The sidewall of groove 13 and bottom have cushion oxide layer 14, are filled with shallow groove isolation structure 15 in the groove 13;
Trap 16 is opposite with the doping type of trap 12, the thickness of trap 16 is less than the thickness of trap 12, have heavy doping source region 21 and light doping section 19 in the trap 16, heavy doping source region 21 is opposite with the doping type of trap 16, and the doping type of heavy doping source region 21 and light doping section 19 is identical and doping content heavy doping source region 21 is bigger;
The doping type of heavy doping drain region 22 and trap 12 is identical and doping content heavy doping drain region 22 is bigger;
Be respectively gate oxide 17 and polysilicon gate 18 on the trap 12, a side of polysilicon gate 18 is above shallow groove isolation structure 15, and opposite side is above p trap 16;
The both sides of polysilicon gate 18 have side wall 20a, and the top of polysilicon gate 18 has medium 20b;
Have light doping section 30 near the sidewall of groove 13 and place, bottom in the described trap 12, the doping type of light doping section 30 and trap 12 is identical and doping content light doping section 30 is littler.
The manufacture method of above-mentioned LDMOS comprises the steps:
In the 1st step, epitaxial growth one deck epitaxial loayer 11 identical with the doping type of substrate 10 on substrate 10 carries out ion and injects in epitaxial loayer 11, thereby forms the trap 12 opposite with epitaxial loayer 11 doping types on epitaxial loayer 11 surfaces;
The 2nd step, go out a groove 13 in trap 12 surface etch, sidewall and bottom oxidation growth one deck cushion oxide layer 14 at groove 13, again at silicon chip surface deposit one deck medium, this layer medium to major general's groove 13 is filled full, again with the medium milling of institute's deposit to trap 12 upper surface flush, in groove 13, formed shallow groove isolation structure 15 this moment;
Carry out ion and inject form trap 16 in trap 12, trap 16 does not overlap in a side of shallow groove isolation structure 15 and both, and the doping type of trap 16 is opposite with trap 12;
The 3rd step, at silicon chip surface growth one deck silica, deposit one deck polysilicon again, thus this layer of etching polysilicon and silica form polysilicon gate 18 and gate oxide 17; One side of polysilicon gate 18 is on shallow groove isolation structure 15, and opposite side is on trap 16;
Carry out lightly doped drain at polysilicon gate 18 near a side of trap 16 and inject, thereby in trap 16, form the light doping section 19 opposite with trap 16 doping types;
At silicon chip surface deposit one deck medium, this layer silica is higher than the upper surface of polysilicon gate 18; Anti-carve this layer medium, form side wall 20a, above polysilicon gate 18, form medium 20b in the both sides of polysilicon gate 18;
In the 4th step, carry out heavy-doped source at side wall 20a near a side of trap 16 and inject, thereby in trap 16, form the heavy doping source region 21 opposite with trap 16 doping types; Carry out heavy doping at shallow groove isolation structure 15 away from a side of trap 16 and leak injection, thereby form the heavy doping drain region 22 identical with trap 12 doping types, that doping content is higher in trap 12, heavy doping drain region 22 does not overlap with shallow groove isolation structure 15;
Described method is in the 2nd step, etching groove 13 and between the sidewall of groove 13 and bottom grow liners oxide layer 14, also comprising: ion is being carried out in the sidewall of groove 13 and bottom inject, it is opposite with trap 12 that ion injects type, thereby sidewall and place, bottom at the close groove 13 of trap 12 form light doping section 30, and the doping type of light doping section 30 and trap 12 is identical and doping content light doping section 30 is littler.
As shown in Figure 1, the drift region of traditional LDMOS device is a trap 12; As shown in Figure 3, the drift region of LDMOS device of the present invention is trap 12 and light doping section 30, and the doping type of light doping section 30 and trap 12 is identical but doping content is lower.So just, can reduce the electric field of raceway groove on vertical and horizontal direction, thereby reduce the electron collision intensity of drift region, hot carrier injection effect is inhibited, improve the safety operation area and the reliability of LDMOS device.
Description of drawings
Fig. 1 is the structural representation of existing LDMOS;
Fig. 2 a, Fig. 2 b, Fig. 2 c are the schematic diagrames of each step of manufacture method of existing LDMOS;
Fig. 3 is the structural representation of LDMOS of the present invention;
Fig. 4 a, Fig. 4 b are the schematic diagrames of each step of manufacture method of LDMOS of the present invention;
Fig. 5 is the ion distribution figure of the n type impurity of traditional LDMOS and LDMOS of the present invention;
Fig. 6 is the raceway groove vertical electric field distribution map of traditional LDMOS and LDMOS of the present invention;
Fig. 7 is the raceway groove horizontal component of electric field distribution map of traditional LDMOS and LDMOS of the present invention.
Description of reference numerals among the figure:
10 is substrate; 11 is epitaxial loayer; 12 is trap; 13 is groove; 14 is cushion oxide layer; 15 is shallow groove isolation structure; 16 is trap; 17 is gate oxide; 18 is polysilicon gate; 19 is light doping section; 20a is a side wall; 20b is a medium; 21 doping source regions of attaching most importance to; 22 doped drain of attaching most importance to; 20 is light doping section; A, B, C are cutting line.
Embodiment
Being example with a n type LDMOS below describes the structure of LDMOS device of the present invention.
See also Fig. 3, n type LDMOS of the present invention comprises p type substrate 10, p type epitaxial loayer 11 and n trap 12 from bottom to top respectively.The thickness of n trap 12 is generally 4～5 μ m, is also referred to as " dark n trap " sometimes.Have groove 13, p trap 16 and n type heavy doping drain region 22 in the n trap 12, p trap 16 and n type heavy doping drain region 22 do not coincide in the both sides of groove 13 and all respectively (promptly all with groove 13 at a distance of certain distance) with groove 13.The sidewall of groove 13 and bottom have cushion oxide layer 14, are filled with shallow groove isolation structure 15 (normally dielectric materials such as silica, silicon nitride, silicon oxynitride) in the groove 13.Sidewall and place, bottom near groove 13 in the n trap 12 have n type light doping section 30, and the doping content of n type light doping section 30 is less than the doping content of n trap 12.P trap 16 for example is " a low pressure p trap ", and the thickness of p trap 16 has n type heavy doping source region 21 and n type light doping section 19 less than the thickness of n trap 12 in the p trap 16, and the doping content in n type heavy doping source region 21 is greater than the doping content of n type light doping section 19.The doping content in n type heavy doping drain region 22 is greater than the doping content of n trap 12.Be respectively gate oxide 17 and polysilicon gate 18 on the n trap 12, a side of polysilicon gate 18 is above shallow groove isolation structure 15, and opposite side is above p trap 16.The both sides of polysilicon gate 18 have side wall 20a, and the top of polysilicon gate 18 has medium 20b, and side wall 20a and medium 20b are generally dielectric materials such as silica, silicon nitride, silicon oxynitride.
N type LDMOS is compared to p type LDMOS, and the influence that is subjected to hot carrier injection effect is more obvious.The structure of LDMOS of the present invention is equally applicable to p type LDMOS, and just the doping type of each several part is opposite with n type LDMOS.
See also Fig. 5, this is the ion distribution figure of the n type impurity of that dotted line A in Fig. 1 and Fig. 3 dissects, traditional LDMOS and LDMOS of the present invention.Dotted line is represented traditional LDMOS among the figure, and solid line is represented LDMOS of the present invention.Obviously LDMOS of the present invention has lower n type foreign ion distribution in certain position of Y-axis coordinate, and this expression LDMOS of the present invention has formed the lower n type light doping section 30 of doping content in this position.
See also Fig. 6, this is the raceway groove vertical electric field distribution map of that dotted line B in Fig. 1 and Fig. 3 dissects, traditional LDMOS and LDMOS of the present invention.Dotted line is represented traditional LDMOS among the figure, and solid line is represented LDMOS of the present invention.Obviously the raceway groove place of LDMOS of the present invention below gate oxide 17 has lower vertical direction (vertically) Electric Field Distribution, and declines by a big margin, and this is that light doping section 30 brings.
See also Fig. 7, this is the raceway groove horizontal component of electric field distribution map of that dotted line C in Fig. 1 and Fig. 3 dissects, traditional LDMOS and LDMOS of the present invention.Dotted line is represented traditional LDMOS among the figure, and solid line is represented LDMOS of the present invention.Obviously the raceway groove place of LDMOS of the present invention below gate oxide 17 has lower horizontal direction (laterally) Electric Field Distribution, and fall is not very big, and this also is that light doping section 30 brings.
From Fig. 5, Fig. 6, Fig. 7 as can be known, because LDMOS device of the present invention has increased light doping section 30, the drift region of LDMOS device is made of jointly trap 12 and light doping section 30 like this.The light doping section 30 that doping content is lower can significantly reduce the Electric Field Distribution of raceway groove in vertical direction, and suitably reduces raceway groove Electric Field Distribution in the horizontal direction, thereby improves the adverse effect that hot carrier injection effect brings the LDMOS device.
The manufacture method of LDMOS of the present invention comprises the steps, is example with n type LDMOS:
In the 1st step, see also Fig. 2 a, epitaxial growth one deck p type epitaxial loayer 11 on p type substrate 10.The ion that carries out n type impurity again in p type epitaxial loayer 11 injects, and n type impurity is generally phosphorus, arsenic, antimony etc., forms n trap 12 on the top (near the upper surface place) of p type epitaxial loayer 11.The degree of depth of n trap 12 for example is 4～5 μ m after the annealed technology.
The 2nd step saw also Fig. 4 a, went out a groove 13 in n trap 12 surface etch, for example adopted shallow-trench isolation (STI) technology.The ion that p type impurity is carried out in the sidewall and the bottom of groove 13 injects, and p type impurity is generally boron etc., at the sidewall and place, the bottom formation n type light doping section 30 of close the groove 13 of n trap 12.The sidewall of groove 13 and bottom are being carried out ion when injecting, can be on the barrier layer of media such as the part deposit capping oxidation silicon of silicon chip surface except that groove 13, silicon nitride, silicon oxynitride as the ion injection.Owing in n trap 12, inject the n type light doping section 30 that p type ion forms, so the doping content of n type light doping section 30 is less than the doping content of n trap 12.
Follow sidewall and bottom oxidation growth or deposit one deck cushion oxide layer 14 at groove 13, again silicon chip surface deposit (for example being HDPCVD technology) one deck medium (for example being silica, silicon nitride, silicon oxynitride etc.), this layer medium to major general's groove 13 is filled full, again with the medium milling (for example being CMP technology) of institute's deposit to trap 12 upper surface flush, in groove 13, formed shallow groove isolation structure 15 this moment.
Carry out p type ion and inject form p trap 16 in n trap 12, p trap 16 does not overlap (promptly apart certain distance) in a side of shallow groove isolation structure 15 and both.
The 3rd step saw also Fig. 4 b, at silicon chip surface growth one deck silica, and deposit one deck polysilicon on silica, thus this layer of etching polysilicon and silica form polysilicon gate 18 and gate oxide 17.One side of polysilicon gate 18 is on shallow groove isolation structure 15, and opposite side is on p trap 16.Then the lightly doped drain that carries out n type impurity near a side of p trap 16 at polysilicon gate 18 injects, thereby forms n type light doping section 19 in p trap 16.At silicon chip surface deposit one deck medium, this layer medium is higher than the upper surface of polysilicon gate 18.Anti-carve this layer medium, form side wall 20a, above polysilicon gate 18, form medium 20b simultaneously in the both sides of polysilicon gate 18.Side wall 20a and medium 20b are connected as a single entity, and are generally dielectric materials such as silica, silicon nitride, silicon oxynitride.The side of side wall 20a is on shallow groove isolation structure 15 at this moment, and opposite side is on p trap 16.
The 4th step saw also Fig. 3, and the heavy-doped source that carries out n type impurity near a side of p trap 16 at side wall 20a injects, thereby formed n type heavy doping source region 21 in p trap 16, and the doping content in n type heavy doping source region 21 is greater than the doping content of n type light doping section 19.Leak injection in the heavy doping that shallow groove isolation structure 15 carries out n type impurity away from a side of p trap 16, thereby form the n type heavy doping drain region 22 higher than the doping content of n trap 12 in n trap 12, n type heavy doping drain region 22 does not overlap (promptly at a distance of certain distance) with shallow groove isolation structure 15.
The manufacture method of said n type LDMOS is equally applicable to make p type LDMOS of the present invention, and just the doping type of the dopant type of each step ion injection, each several part structure is opposite with n type LDMOS.
Said method carries out the ion injection to the sidewall and the bottom of groove 13 in the 2nd step, can be boron (B) atom or boron oxide (BF 2+) ion.
Said method carries out the ion injection to the sidewall and the bottom of groove 13 in the 2nd step, and dosage for example is 1 * 10 11～1 * 10 12Atom per square centimeter (or ion every square centimeter), energy for example is 10～20keV.
In sum, the present invention forms light doping section by trenched side-wall and the bottom at LDMOS, reduced the electric field of groove in vertical and horizontal direction, thus the adverse effect that less hot carrier injection effect brings LDMOS, safety operation area and the reliability of raising LDMOS.

Claims (5)

1. a LDMOS comprises substrate (10), epitaxial loayer (11) and trap (12) from bottom to top respectively, and epitaxial loayer (11) is identical with the doping type of substrate (10), and trap (12) is opposite with the doping type of epitaxial loayer (11);
Have groove (13), trap (16) and heavy doping drain region (22) in the trap (12), trap (16) and heavy doping drain region (22) do not coincide with groove (13) in the both sides of groove (13) and all respectively;
The sidewall of groove (13) and bottom have cushion oxide layer (14), are filled with shallow groove isolation structure (15) in the groove (13);
Trap (16) is opposite with the doping type of trap (12), the degree of depth of trap (16) is less than the degree of depth of trap (12), have heavy doping source region (21) and light doping section (19) in the trap (16), heavy doping source region (21) is opposite with the doping type of trap (16), and the doping type of heavy doping source region (21) and light doping section (19) is identical and doping contents heavy doping source region (21) are bigger;
The doping type of heavy doping drain region (22) and trap (12) identical and but the doping content of heavy doping drain region (22) is bigger;
Be respectively gate oxide (17) and polysilicon gate (18) on the trap (12), a side of polysilicon gate (18) is in the top of shallow groove isolation structure (15), and opposite side is in the top of trap (16);
The both sides of polysilicon gate (18) have side wall (20a), and the top of polysilicon gate (18) has medium (20b);
It is characterized in that: have light doping section (30) near the sidewall of groove (13) and place, bottom in the described trap (12), the doping type of light doping section (30) and trap (12) is identical and doping content light doping section (30) is littler.
2. LDMOS according to claim 1 is characterized in that:
When described LDMOS was n type LDMOS, substrate (10), epitaxial loayer (11), trap (16) were the p type; Trap (12), light doping section (19), heavy doping source region (21), heavy doping drain region (22) are the n type;
When described LDMOS was p type LDMOS, substrate (10), epitaxial loayer (11), trap (16) were the n type; Trap (12), light doping section (19), heavy doping source region (21), heavy doping drain region (22) are the p type.
3. the manufacture method of LDMOS as claimed in claim 1 comprises the steps:
The 1st step, go up epitaxial growth one deck epitaxial loayer (11) identical at substrate (10) with substrate (10) doping type, in epitaxial loayer (11), carry out ion again and inject and high annealing, form the trap (12) opposite with epitaxial loayer (11) doping type on the surface of epitaxial loayer (11);
The 2nd step, go out a groove (13) in trap (12) surface etch, sidewall and bottom oxidation growth one deck cushion oxide layer (14) at groove (13), again at silicon chip surface deposit one deck medium, this layer medium to major general's groove (13) is filled full, again with the medium milling of institute's deposit to trap (12) upper surface flush, in groove (13), formed shallow groove isolation structure (15) this moment;
Carry out ion and inject form trap (16) in trap (12), the doping type of trap (16) is opposite with trap (12), and trap (16) does not overlap in a side of shallow groove isolation structure (15) and both;
The 3rd step, at silicon chip surface growth one deck silica, deposit one deck polysilicon again, thus this layer of etching polysilicon and silica form polysilicon gate (18) and gate oxide (17); One side of polysilicon gate (18) is on shallow groove isolation structure (15), and opposite side is on trap (16);
Carry out lightly doped drain at polysilicon gate (18) near a side of trap (16) and inject, thereby in trap (16), form the light doping section (19) opposite with trap (16) doping type;
At silicon chip surface deposit one deck medium, this layer medium is higher than the upper surface of polysilicon gate (18); Anti-carve this layer medium, form side wall (20a), form medium (20b) in the top of polysilicon gate (18) in the both sides of polysilicon gate (18);
In the 4th step, carry out heavy-doped source at side wall (20a) near a side of trap (16) and inject, thereby in trap (16), form the heavy doping source region (21) opposite with trap (16) doping type; Carry out heavy doping at shallow groove isolation structure (15) away from a side of trap (16) and leak injection, thereby form the heavy doping drain region (22) identical with trap (12) doping type, that doping content is higher in trap (12), heavy doping drain region (22) do not overlap with shallow groove isolation structure (15);
It is characterized in that, described method is in the 2nd step, etching groove (13) and between the sidewall of groove (13) and bottom grow liners oxide layer (14), also comprising: ion is being carried out in the sidewall of groove (13) and bottom inject, it is opposite with the dopant type of trap (12) that ion injects type, thereby sidewall and place, bottom at the close groove (13) of trap (12) form light doping section (30), and the doping type of light doping section (30) and trap (12) is identical and doping content light doping section (30) is littler.
4. the manufacture method of LDMOS according to claim 3 is characterized in that, when described LDMOS was n type LDMOS, described method was carried out the injection of boron atom or boron oxide ion to the sidewall and the bottom of groove (13) in the 2nd step.
5. the manufacture method of LDMOS according to claim 3 is characterized in that, the dosage that during described method the 2nd goes on foot the ion injection is carried out in the sidewall and the bottom of groove (13) is 1 * 10 11～1 * 10 12Atom per square centimeter, energy are 10～20keV.
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