CN102054809B - Re-distribution mechanism - Google Patents
Re-distribution mechanism Download PDFInfo
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- CN102054809B CN102054809B CN 200910198066 CN200910198066A CN102054809B CN 102054809 B CN102054809 B CN 102054809B CN 200910198066 CN200910198066 CN 200910198066 CN 200910198066 A CN200910198066 A CN 200910198066A CN 102054809 B CN102054809 B CN 102054809B
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- oxide layer
- reroutes
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- random asccess
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a re-distribution mechanism. A re-distribution layer is arranged at an opening hole of a test bonding pad, and a second oxide layer is formed on a nitriding layer, so that a random access memory is easy to encapsulate; and metal wires on the top layer cannot be damaged in the test process of a chip probe, so the yield of a wafer in which the random access memory is positioned cannot be reduced greatly.
Description
Technical field
The present invention relates to the random asccess memory field, particularly a kind of mechanism that reroutes of random asccess memory.
Background technology
Along with developing rapidly of chip technology, rerouting, (Re-Distribution Layer RDL) has been widely used in the chip manufacturing field to layer.
But in the random asccess memory field, the layer that reroutes never is used widely.Because after random asccess memory being carried out chip probe test (circuit probing test, CP test), the top layer metallic layer that is connected with the layer that reroutes can suffer very big destruction, can reduce the yield of random asccess memory largely.
Figure 1A is the profile of the test lead structure of existing random asccess memory.Shown in Figure 1A, said test lead structure comprises: substrate 100; Be positioned at testing weld pad 102 and top wire 106 on the said substrate, between said testing weld pad 102 and the top wire 106, be formed with bedding void 104 between the different testing weld pad 102 and between the different top wire 106; On said bedding void 104, testing weld pad 102 and top wire 106, be formed with first oxide layer 108 and nitration case 110 successively.In order to realize test function, corresponding said testing weld pad 102 has perforate 114 in said first oxide layer 108 and the nitration case 110, and said perforate 114 is exposed said testing weld pad 102.Because the depth-to-width ratio of bedding void 104 is bigger, so when forming said first oxide layer 108, said first oxide layer 108 can not be filled into bedding void 104.
When carrying out the chip probe test, thereby being contacted with said testing weld pad 102, probe realizes test, still; Because the layer that reroutes is not set, and the design attitude of testing weld pad 102 is fixed, so; If change packaged type or package position, just need the design attitude of changed test pad 102, so just need change the mask plate of each step; And mask plate is very expensive, so this can increase the manufacturing cost of semiconductor chip greatly.
Figure 1B is the profile of the test lead structure of existing another kind of random asccess memory.Be with the difference of the test lead structure shown in Figure 1A, in perforate 114, be formed with the layer 115 that reroutes.Though be provided with the layer 115 that reroutes; But; When probe contact with the layer 115 that reroutes and carries out chip probe when test, probe tilts to prick to reroute on the layer 115 at a certain angle, owing to the existence of bedding void 104; The pressure of probe can make top wire 106 deform and damage, and makes to be short-circuited between the different top wires or the top wire disconnection.The damage of said top wire 106 can have a strong impact on the yield of semiconductor chip.
Summary of the invention
In order to solve in the prior art; Top wire is damaged by probe easily; Thereby reduce the yield problem of random asccess memory place wafer, the present invention provides a kind of mechanism that reroutes, and can well protect top wire; Make the yield loss of the wafer that comprises random asccess memory of the present invention, can sharply not increase with the increase of chip probe testing time.
The present invention provides a kind of mechanism that reroutes to comprise: substrate; Be positioned at testing weld pad and top wire on the said substrate, between said testing weld pad and the top wire, be formed with bedding void between the different testing weld pad and between the different top wire; On said bedding void, testing weld pad and top wire, be formed with first oxide layer, nitration case and second oxide layer successively; Corresponding said testing weld pad is formed with perforate in said first oxide layer, nitration case and second oxide layer, in said perforate, be formed with the layer that reroutes, and the said layer that reroutes extends on said second oxide layer.
Optional, said first oxide layer and said second oxide layer utilize high density plasma chemical vapor deposition to form.
Preferably, said first oxide layer and said second oxide layer utilize plasma enhanced chemical vapor deposition to form.
Optional, the said material that reroutes layer is copper or aluminium.
Preferably, said second thickness of oxide layer is greater than said first thickness of oxide layer.
Optional, the material of said first oxide layer and said second oxide layer can be silica, the material of said nitration case can be silicon nitride.
Further, the said first thickness of oxide layer scope is 1500 dust to 2000 dusts, and the said second thickness of oxide layer scope is 9000 dust to 10000 dusts.
Further, the thickness range of said nitration case is 2500 dust to 3500 dusts.
Because in the mechanism that reroutes of the present invention, increased by second oxide layer, said second oxide layer has good voltage endurance capability, make the top layer metallic layer can be, and damaged with the increase of chip probe testing time.Thereby make and comprise and reroute the present invention the yield of random asccess memory wafer of mechanism is stable, leakage current changes very little.
Description of drawings
Figure 1A is the profile of the test lead structure of existing random asccess memory;
Figure 1B is the profile of the test lead structure of existing another kind of random asccess memory;
Fig. 2 is the profile of the mechanism that reroutes of the embodiment of the invention;
Fig. 3 is the random asccess memory wafer yield loss comparison diagram through seven chip probe tests;
Fig. 4 is for carrying out the situation of change of leakage current in seven chip probe test processs respectively to each random asccess memory wafer.
Embodiment
In order to make content of the present invention and protection range clearer, understandable, content of the present invention is elaborated below in conjunction with accompanying drawing.
Core concept of the present invention is; Tapping setting through in the testing weld pad district is rerouted, and on nitration case, forms second oxide layer, and random asccess memory is encapsulated easily; And in the chip probe test process; Can not destroy top wire, thereby the yield of random asccess memory place wafer can not reduce significantly.
Fig. 2 is the profile of the mechanism that reroutes of the embodiment of the invention.With reference to shown in Figure 2, the mechanism that reroutes of present embodiment comprises: substrate 200; Be positioned at testing weld pad 202 and top wire 206 on the said substrate 200, between said testing weld pad 202 and the top wire 206, be formed with bedding void 204 between the different testing weld pad 202 and between the different top wire 206; On said bedding void 206, testing weld pad 202 and top wire 206, be formed with first oxide layer 208, nitration case 210 and second oxide layer 212 (first oxide layer 208, nitration case 210 and second oxide layer 212 constitute the ONO structures) successively; Corresponding said testing weld pad 202 is formed with perforate in said first oxide layer 208, nitration case 210 and second oxide layer 212, in said perforate, be formed with the layer 214 that reroutes, and the said layer 214 that reroutes extends on said second oxide layer 212.
Optional, said first oxide layer 208 utilizes high density plasma chemical vapor deposition (HDP CVD) to form with said second oxide layer 212.
Preferably, said first oxide layer 208 utilizes plasma enhanced chemical vapor deposition (PECVD) to form with said second oxide layer 212.Utilize said plasma enhanced chemical vapor deposition method, said first oxide layer 208 of formation has good voltage endurance capability with said second oxide layer 212, can not damage through repeatedly probe contact.
Optional, the said material that reroutes layer 214 is copper or aluminium.
Wherein, the material of said first oxide layer 208 and said second oxide layer 212 can be silica, and the material of said nitration case can be silicon nitride.
Preferably, the thickness of said second oxide layer 212 is greater than the thickness of said first oxide layer 208.Like this, said second oxide layer 212 can well play withstand voltage effect, and promptly said second oxide layer 212 is not easy to damage because of the contact of probe, thereby can well protect top wire 206.
Preferably, the thickness range of said first oxide layer 208 is 1500 dust to 2000 dusts, and the thickness range of said nitration case 210 is 2500 dust to 3500 dusts, and the thickness range of said second oxide layer 212 is 9000 dust to 10000 dusts.
Fig. 3 is the random asccess memory wafer yield loss comparison diagram through seven chip probe tests.As shown in Figure 3, seven wafer yield loss figure of the first row ONO are to comprise the reroute yield loss figure of random asccess memory wafer of mechanism of the present invention, measure number of times and from left to right increase progressively successively; The second row BL is the random asccess memory wafer yield loss figure that comprises existing test lead structure, measures number of times and from left to right increases progressively successively.
Can know by Fig. 3, in seven chip probe test processs, comprise the reroute yield loss of random asccess memory wafer of mechanism of the present invention, be starkly lower than the random asccess memory wafer yield that comprises existing test lead structure and decrease; And along with the increase of measuring number of times; Comprise that the reroute yield loss of random asccess memory wafer of mechanism of the present invention changes very little; That is, comprise that the reroute random asccess memory of mechanism of the present invention receives the influence of probe contact very little, that is to say; The mechanism's voltage endurance capability that reroutes of the present invention is very strong, can not damage top wire because of the contact of probe.
Fig. 4 is for carrying out the situation of change of leakage current in seven chip probe test processs respectively to each random asccess memory wafer.With reference to shown in Figure 4; Wherein 11......17 representes first random asccess memory wafer is carried out seven chip probe tests; 21......27 expression is carried out seven chip probe tests to second random asccess memory wafer; 31......37 expression is carried out seven chip probe tests to the 3rd random asccess memory wafer; 41......47 expression is carried out seven chip probe tests to the 4th random asccess memory wafer, 51......57 representes the 5th random asccess memory wafer carried out seven chip probe tests, and 61......67 representes the 6th random asccess memory wafer carried out seven chip probe tests.Wherein, the 5th random asccess memory wafer is the random asccess memory wafer that comprises existing test lead structure, and other five brilliant random asccess memory wafers are to comprise the reroute random asccess memory wafer of mechanism of the present invention.
The random asccess memory wafer that comprises existing test lead structure, with the increase of chip probe testing time, its leakage current increases rapidly; Comprise the reroute random asccess memory wafer of mechanism of the present invention, with the increase of chip probe testing time, its leakage current changes very little.So, comprising the reroute random asccess memory wafer of mechanism of the present invention, it is electrically stable, and is very little with the variation of chip probe testing time.
Claims (3)
1. the mechanism that reroutes comprises: substrate; Be positioned at testing weld pad and top wire on the said substrate, between said testing weld pad and the top wire, be formed with bedding void between the different testing weld pad and between the different top wire; On said bedding void, testing weld pad and top wire; Be formed with first oxide layer, nitration case and second oxide layer successively; The material of said first oxide layer and said second oxide layer is a silica, and the material of said nitration case is a silicon nitride, and the said first thickness of oxide layer scope is 1500 dust to 2000 dusts; The said second thickness of oxide layer scope is 9000 dust to 10000 dusts, and the thickness range of said nitration case is 2500 dust to 3500 dusts; Corresponding said testing weld pad is formed with perforate in said first oxide layer, nitration case and second oxide layer, in said perforate, be formed with the layer that reroutes, and the said layer that reroutes extends on said second oxide layer.
2. the mechanism that reroutes as claimed in claim 1 is characterized in that, said first oxide layer and said second oxide layer utilize high density plasma chemical vapor deposition to form.
3. the mechanism that reroutes as claimed in claim 1 is characterized in that, said first oxide layer and said second oxide layer utilize plasma enhanced chemical vapor deposition to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910198066 CN102054809B (en) | 2009-10-30 | 2009-10-30 | Re-distribution mechanism |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910198066 CN102054809B (en) | 2009-10-30 | 2009-10-30 | Re-distribution mechanism |
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| Publication Number | Publication Date |
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| CN102054809A CN102054809A (en) | 2011-05-11 |
| CN102054809B true CN102054809B (en) | 2012-12-12 |
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| CN 200910198066 Active CN102054809B (en) | 2009-10-30 | 2009-10-30 | Re-distribution mechanism |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339816A (en) * | 2011-09-30 | 2012-02-01 | 上海宏力半导体制造有限公司 | Wafer test key structure and wafer test method |
| US10079218B1 (en) * | 2017-06-12 | 2018-09-18 | Powertech Technology Inc. | Test method for a redistribution layer |
| CN113097168A (en) * | 2021-03-26 | 2021-07-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
| CN116344478A (en) | 2021-12-24 | 2023-06-27 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410967A (en) * | 2006-05-16 | 2009-04-15 | 国际商业机器公司 | Dual wired integrated circuit chips |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410967A (en) * | 2006-05-16 | 2009-04-15 | 国际商业机器公司 | Dual wired integrated circuit chips |
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| CN102054809A (en) | 2011-05-11 |
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