TWI774125B - Semiconductor detecting device and detecting method - Google Patents

Abstract

A semiconductor detecting device includes a semiconductor substrate, a first interconnect structure, a second interconnect structure, a connecting metal layer, a redistribution layer (RDL) structure, a first terminal and a second terminal. The first and second interconnect structures are disposed over and electrically isolated from the semiconductor substrate. The connecting metal layer electrically connects the first interconnect structure to the second interconnect structure. The RDL structure is disposed over and is electrically connected to the first interconnect and the second interconnect structure. The first terminal is electrically connected to the first interconnect structure through the RDL structure, and the second terminal is electrically connected to the second interconnect structure through the RDL structure.

Description

Semiconductor test element and test method

Embodiments of the present invention relate to a semiconductor testing device and a testing method, and more particularly, to a semiconductor testing device for testing electrical over stress (EOS) and a testing method for electrical overload.

Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic equipment. Generally speaking, semiconductor devices can form various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) on a wafer by a front-end-of-line (FEOL) process, and use Interconnect structures that provide electrical connections between these electronic components are formed by back-end-of-line (BEOL) processes to fabricate many integrated circuits on a wafer. And by sawing between the integrated circuits along the dicing line, the individual dies on the wafer are singulated, and the individual dies can be packaged into multi-die modules or other types. package. The semiconductor industry continues to increase the integration density of various electronic components by continuously reducing the minimum feature size, which enables more components to be integrated into a given area. In some applications, these smaller electronic components also require smaller packages that utilize less area than packages of the past.

The package structure is provided with conductive terminals, such as power terminals, ground terminals and signal terminals, to draw power required for operation, or to exchange signals with other external circuits. However, since these endpoints are all conductive materials, electrical overload (or excessive electrical stress) (EOS) may eventually occur due to the accumulation of charges during the process, which may damage the internal structure of the integrated circuit.

As mentioned above, electrical overloading may occur at any point in the entire process, but current semiconductor package structures can only be measured after the entire package structure is fabricated. At this time, it is only possible to find out whether the electrical overload has occurred, but it is impossible to know which process site has the electrical overload.

Therefore, there is still a need for a semiconductor testing device for testing electrical overload and a method for testing electrical overload, so as to timely find a process site where electrical overload occurs.

According to an embodiment of the present invention, a semiconductor testing device is provided, comprising: a semiconductor substrate, a first internal interconnection structure, a second internal interconnection structure, a connection metal layer, and a redistribution layer (redistribution layer, RDL) structure, a first endpoint, and a second endpoint. The first internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The connection metal layer is electrically connected to the first internal interconnection structure and the second internal interconnection structure, and is electrically isolated from the semiconductor substrate. The redistribution layer structure is disposed on the first internal interconnection structure and the second internal interconnection structure, and is electrically connected with the first internal interconnection structure and the second internal interconnection structure. The first terminal is electrically connected to the first internal interconnection structure through the redistribution layer structure, and the second terminal is electrically connected to the second internal interconnection structure through the redistribution layer structure.

According to an embodiment of the present invention, a semiconductor test element is further provided, comprising: a semiconductor substrate, a first internal interconnection structure, a second internal interconnection structure, a third internal interconnection structure, and a redistribution layer structure , a first endpoint and a second endpoint. The first internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate and the first internal interconnection structure. The third internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate, the first internal interconnection structure and the second internal interconnection structure. The redistribution layer structure is disposed on the first internal interconnection structure, the second internal interconnection structure and the third internal interconnection structure, and is electrically connected to the first internal interconnection structure and the second internal interconnection structure sexual connection. The first terminal is electrically connected to the first internal interconnection structure through the redistribution layer structure, and the second terminal is electrically connected to the second internal interconnection structure through the redistribution layer structure.

According to an embodiment of the present invention, another testing method is provided. The testing method includes: receiving a semiconductor structure, the semiconductor structure including a semiconductor substrate, a first semiconductor testing element and a second semiconductor testing element. The first semiconductor test element is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second semiconductor testing element is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate and the first semiconductor testing element. A first pass/break test is performed on the first semiconductor test element. A second pass/break test is performed on the second semiconductor test element. When the result of the first pass/open test is open circuit, it is determined that a metal electric overload has occurred. When the result of the second pass/disconnect test is pass, it is determined that a dielectric breakdown electrical overload occurs.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, "forming a first member over a second member or on a second member" may include embodiments in which the first member and the second member are formed in direct contact, and may also Embodiments are included in which additional members may be formed between the first member and the second member such that the first member and the second member may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is intended for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for convenience of description, spatially relative terms (such as "below," "below," "under," "over," "on," "above," and the like may be used herein to describe an element or component relationship to another element(s) or components as depicted in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

As used herein, terms such as "first", "second", and "third" describe various elements, components, regions, layers and/or sections, such elements, components, regions, layers and/or Sections should not be limited by these terms. These terms may only be used to distinguish an element, component, region, layer or section from one another. Terms such as "first," "second," and "third," when used herein do not imply a sequence or order unless the context clearly dictates otherwise.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Furthermore, as used herein, the terms "substantially," "approximately," or "about" generally mean within a value or range that can be considered by one of ordinary skill. Alternatively, the terms "substantially", "approximately" or "about" mean within an acceptable standard deviation of the mean as considered by those of ordinary skill. Those of ordinary skill will appreciate that the acceptable standard deviation may vary from technique to technique. Except in operating/working examples or unless expressly stated otherwise, all numerical ranges, quantities, values and percentages disclosed herein (such as material quantities, durations, temperatures, operating conditions, quantity ratios and the like) Numerical ranges, amounts, values and percentages) should be understood to be modified in all instances by the terms "substantially", "approximately" or "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in this disclosure and the accompanying claims are approximations that can vary depending on expectations. Finally, each numerical parameter should at least be interpreted in light of the reported significant digits and by applying ordinary rounding techniques. A range may be expressed herein as from one endpoint to the other or between the two endpoints. All ranges disclosed herein are inclusive of the endpoints unless otherwise indicated.

Conductive terminals in the package structure, such as terminals formed in back-end-of-line (BEOL) and far-back-end-of-line (FBEOL), may be The continuous accumulation of electric charges results in electrical overload, which causes damage to the internal structure of the integrated circuit, for example, damage to the internal interconnect structure formed by the back-end process. Generally speaking, electrical overloading can be classified into two types: metal burn-out electrical overloading and dielectric breakdown electrical overloading. As the width and thickness of the metal layers in the internal interconnect structure shrink, the possibility of the occurrence of electrical overloading of the metal melt increases. In addition, since the internal interconnect structure often uses ultra-low-k (ULK) dielectric materials or extremely low-k (extremely low-k, ELK) dielectric materials, the dielectric layer collapses even more. Increased likelihood of sexual overload occurring. However, there is still no test structure that can simultaneously detect which electrical overload is.

In addition, as mentioned above, the accumulation of charges occurs gradually during the process, and there is currently no test structure that can be used to detect whether the problem of electrical overload occurs in the current station process during the process.

Therefore, the present disclosure provides a semiconductor testing device and a testing method. The semiconductor testing device can be integrated in the back-end process and the remote back-end process to determine whether an electrical overload occurs through a simple on/off test. In some embodiments, an on/off test is performed on the semiconductor test element used to test the electrical overload of the metal, and when the test result is an open circuit, it can be determined that the electrical overload of the metal has occurred. In some embodiments, an on/off test is performed on the semiconductor test element used to test the dielectric collapse electrical overload, and when the test result is an on, it is determined that the dielectric collapse electrical overload occurs. In addition, as mentioned above, since the semiconductor testing device can be integrated in the back-end process and the remote back-end process, it can be tested for the endpoints of different layers after the back-end process is completed and during the remote back-end process to achieve The purpose of finding out in time which part of the process occurs the above-mentioned electrical overload problem.

Please refer to FIG. 1 , which is a partial schematic diagram of a semiconductor wafer provided by the present disclosure. According to the embodiments provided by the present disclosure, semiconductor test elements may be disposed on a semiconductor wafer 100 . As shown in FIG. 1 , the semiconductor wafer 100 includes a plurality of scribe line regions 102 and a plurality of die regions 104 defined by the scribe line regions 102 . In some embodiments, the die regions 104 are separated from each other by intersecting scribe regions 102 and arranged in an array. During die sigulation, the semiconductor wafer 100 is divided along the scribe line regions 102 to separate the respective die regions 104 to obtain a plurality of die.

See Figure 1. In some embodiments, the semiconductor wafer 100 includes silicon or other semiconductor materials, such as Group III-V (III-V) semiconductor materials. As will be appreciated by those skilled in the art, various components such as transistors, memory or power components, capacitors, resistors, diodes, photodiodes, sensors or fuses Combinations of these elements, and the like, may be formed within each die region 104 . For example, the aforementioned elements can be formed using a front-end process, and the combination of these elements can form an integrated circuit within each die region 104 . After the front-end process is completed, a middle-end-of-line (MEOL) process can also be used to form a plurality of contact plugs in each die region 104, but the embodiment is not limited to this. . After the front-end process and the middle-end process are completed, a plurality of internal interconnect structures can be formed in each die region 104 by the back-end process. For example, a plurality of dielectric layers may be formed in each die region 104 , and conductive layers may be formed in the dielectric layers, and conductive vias electrically connected to the conductive layers may be formed. The multi-layer structures such as dielectric layers, conductive layers, and conductive plugs can form a plurality of internal interconnect structures in the die area 104 to electrically connect the components formed in the previous process and provide them with external circuits. pipeline.

In some embodiments of the present disclosure, a semiconductor testing device 200 a is provided, which can be disposed in the die region 104 , as shown in FIGS. 1 and 2 . FIG. 2 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . As shown in FIG. 2 , the semiconductor test element 200 a may include a semiconductor substrate 202 , and in the semiconductor substrate 202 , various types of elements and combinations thereof formed by the aforementioned front-end process may be included. The semiconductor testing device 200 a includes a first internal interconnection structure 210 - 1 and a second internal interconnection structure 210 - 2 , which are disposed on the semiconductor substrate 202 . The first internal interconnection structure 210-1 and the second internal interconnection structure 210-2 are electrically isolated from the semiconductor substrate 202, respectively. In some embodiments, the first internal interconnect structure 210 - 1 and the second internal interconnect structure 210 - 2 are further physically isolated from the semiconductor substrate 202 . The semiconductor testing device 200a includes a connecting metal layer 220 that is electrically connected to the first internal interconnection structure 210-1 and the second internal interconnection structure 210-2, but the connecting metal layer 220 is also electrically isolated from the semiconductor substrate 202. The semiconductor testing device 200a further includes a first terminal 230-1 and a second terminal 230-2, the first terminal 230-1 is electrically connected to the first internal interconnection structure 210-1, and the second terminal 230-2 is electrically connected to the second internal interconnection structure 210-2.

In some embodiments, the semiconductor test device 200a further includes a dummy internal interconnect structure 240 . The dummy interconnect structure 240 is disposed on the semiconductor substrate 202 and is electrically isolated from the semiconductor substrate 202 . In addition, the dummy inner interconnection structure 240 is disposed between the first inner interconnection structure 210-1 and the second inner interconnection structure 210-2, and is interconnected with the first inner interconnection structure 210-1 and the second inner interconnection structure 210-1. The structures 210-2 are all electrically isolated.

In some embodiments, the semiconductor testing device 200 a further includes a third internal interconnection structure 250 disposed on the semiconductor substrate 202 . The third inner interconnection structure 250 is electrically isolated from the first inner interconnection structure 210 - 1 , the second inner interconnection structure 210 - 2 , the dummy inner interconnection structure 240 and the connection metal layer 220 . In other words, the first internal interconnection structure 210-1, the second internal interconnection structure 210-2, the connection metal layer 220 and the dummy internal interconnection structure 240 are electrically floating structures. Different from the above-mentioned electrically floating structure, the third internal interconnection structure 250 is electrically connected to the semiconductor substrate 202 . For example, the third internal interconnection structure 250 can be electrically connected to various elements in the semiconductor substrate 202 through contact plugs formed by performing a mid-stage process, so as to provide electrical connection of these elements.

As shown in FIG. 2 , the first inter-connection structure 210-1, the second inter-interconnect structure 210-2, the dummy inter-interconnect structure 240, and the third inter-interconnect structure 250 may include a plurality of dielectric layers, which are The dielectric layers may form a dielectric layer stack 204 . The first internal interconnection structure 210-1, the second internal interconnection structure 210-2, the dummy internal interconnection structure 240 and the third internal interconnection structure 250 further include a plurality of conductive layers 206 and a plurality of electrically connected conductive layers Conductive plug 208 of 206 . The dielectric layer stack 204 , the conductive layer 206 , and the conductive plugs 208 can be formed on the semiconductor substrate 202 by performing the latter process as described above. In some embodiments, the dummy internal interconnection structure 240 does not provide any effective connection electrically, but the dummy internal interconnection structure 240 can avoid the first internal interconnection structure 210-1 and the first internal interconnection structure 210-1 in the back-end process. Problems such as dishing occur between the two internal interconnect structures 210 - 2 during the planarization process in the back-end process. In addition, the dummy inner interconnect structure 240 may also provide mechanical strength between the first inner interconnect structure 210-1 and the second inner interconnect structure 210-2.

Please continue to refer to Figure 2. The conductive layer 206 of the third internal interconnection structure 250 includes a lowermost conductive layer. The lowermost conductive layer is the conductive line or metal line closest to the semiconductor substrate 202, and can be regarded as the zeroth metal layer (M0). In some embodiments, the connection metal layer 220 and the lowermost conductive layer M0 of the third internal interconnection structure 250 are disposed at the same level, but the present disclosure is not limited thereto.

In some embodiments, when the back-end process is completed, a conductive bump or a conductive pad can be respectively formed on the first internal interconnection structure 210-1 and the second internal interconnection structure 210-2 to serve as the first terminal Point 230-1 and second endpoint 230-2. The first terminal 230-1, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 may form a via, and the first terminal 230-1 and the second terminal 230-2 are used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether the manufacturing site of the back-end process is electrically overloaded. The semiconductor test of the latter-stage process will be Details will follow.

See Figure 2. In some embodiments, after semiconductor testing is performed, the above-mentioned first terminal 230-1 and second terminal 230-2 may be damaged by stress. Therefore, during subsequent remote back-end process, the first terminal 230- 1 and the second terminal 230-2 can no longer form other connection layers. For example, after semiconductor testing, die singulation may be performed, followed by forming a molding compound 260 surrounding the die (or semiconductor substrate 202). Next, a remote back-end process is performed to form a redistribution layer (RDL) structure 270 and contact terminals 280 on the semiconductor substrate 202 and the molding material 260 . As shown in FIG. 2 , the redistribution layer structure 270 may have a plurality of redistribution layers, and the redistribution layers respectively include an insulating layer, a plurality of connecting portions 274 disposed in the insulating layer, and plugs electrically connected to the connecting portions 274 . Section 276. In some embodiments, the insulating layers of the redistribution layers can be regarded as an insulating layer stack 272 . In addition, a contact terminal 280 may be disposed on the RDL structure 270 , and the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the RDL structure 270 and the third internal interconnection structure 250 . In some embodiments, the above-mentioned remote back-end process can form the above-mentioned insulating layer stack 272 on the first inter-interconnect structure 210-1, the second inter-interconnect structure 210-2 and the dummy inter-interconnect structure 240, and the insulating layer stack 272 is insulated. The layer stack 272 may cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. 2 . However, in other embodiments, a plurality of connection portions 274 and a plurality of connection portions 274 may also be formed in the insulating layers on the first inter-connection structure 210-1, the second inter-interconnect structure 210-2 and the dummy inter-connection structure 240. The plug portion 276, but the connecting portions 274 and the plug portion 276 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2 and the dummy internal interconnect structure 240 are not provided with contact terminals ; or the connecting portion 274 and the plug portion 276 are electrically isolated from the first terminal 230-1 and the second terminal 230-2. Therefore, the first internal interconnection structure 210-1, the second internal interconnection structure 210-2, and the connecting metal layer 220 are still electrically isolated from other elements or structures by the dielectric layer stack 204 and the insulating layer stack 272, so as to maintain electrical Sexual Float.

Please refer to FIG. 3 . FIG. 3 is a cross-sectional view of another semiconductor testing device 200 b provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA′ tangent line in FIG. 1 . It should be noted that, in the semiconductor test element 200b and the semiconductor test element 200a, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 200b is provided, which can be disposed in the die region 104, as shown in FIG. 1 and FIG. 3 . In addition, the semiconductor test element 200b may include a semiconductor substrate 202, a first internal interconnection structure 210-1, a second internal interconnection structure 210-2, a connection metal layer 220, a dummy internal interconnection structure 240, and A third internal interconnect structure 250 . The relative relationship and connection of the semiconductor substrate 202 , the first internal interconnection structure 210 - 1 , the second internal interconnection structure 210 - 2 , the connection metal layer 220 , the dummy internal interconnection structure 240 , and the third internal interconnection structure 250 The relationship can be the same as that of the semiconductor test device 200a, so it will not be repeated here.

Please continue to refer to Figure 3. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 260 is formed. Then, a remote back-end process is performed to form a redistribution layer structure on the semiconductor substrate 202 and the molding material 260 . As previously mentioned, the RDL structure may include a plurality of RDLs. In some embodiments, a first redistribution layer 270 - 1 may be formed on the semiconductor substrate 202 and the molding material 260 . The first redistribution layer 270-1 includes an insulating layer 272-1, a plurality of connecting portions 274-1 disposed in the insulating layer 272-1, and a plurality of electrically connecting the third internal interconnection structure 250 and the connecting portions 274- 1 of the plug portion 276-1. As shown in FIG. 3 , the first redistribution layer 270 - 1 may be electrically connected to the third internal interconnection structure 250 . When the first redistribution layer 270-1 is formed, the insulating layer 272-1, the connecting portion 274-1 and the interposer can be simultaneously formed on the first internal interconnection structure 210-1 and the second internal interconnection structure 210-2. Plug section 276-1. In some embodiments, a portion of the connecting portion 274-1 on the first interconnect structure 210-1 and the second interconnect structure 210-2 serves as a first terminal 230-1 and a second terminal 230 -2, and the first terminal 230-1 is electrically connected to the first internal interconnection structure 210-1 through the plug portion 276-1, and the second terminal 230-2 is electrically connected to the first internal interconnection structure 210-1 through the plug portion 276-1 The second internal interconnect structure 210-2 is electrically connected. In other words, the first terminal 230-1 and the second terminal 230-2 and the connecting portion 274-1 in the first redistribution layer 270-1 are disposed on the same horizontal layer. It should be noted that the first terminal 230-1, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 may form a via, And the first terminal 230-1 and the second terminal 230-2 are used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether an electrical property occurs at the manufacturing site of the first redistribution layer 270-1. Overload, semiconductor testing at this site will be detailed later.

In some embodiments, after the semiconductor testing of the first RDL 270-1 at the process site is completed, the fabrication of multiple RDLs on the first RDL 270-1 may be continued to complete the process. The RDL structure 270 is shown in FIG. 3 . In addition, after the fabrication of the RDL structure 270 is completed, a contact terminal 280 can be further disposed on the RDL structure 270 . As shown in FIG. 3 , the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnection structure 250 . In some embodiments, the above-mentioned remote back-end process can form the above-mentioned insulating layer stack 272 on the first inter-interconnect structure 210-1, the second inter-interconnect structure 210-2 and the dummy inter-interconnect structure 240, and the insulating layer stack 272 is insulated. The layer stack 272 may cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. 3 . However, in other embodiments, a plurality of connecting portions and a plurality of connecting portions and a plurality of plug part, but no contact terminals are provided on these connection parts and plug parts on the first internal interconnection structure 210-1, the second internal interconnection structure 210-2 and the dummy internal interconnection structure 240; or these The connection part and the plug part are electrically isolated from the first terminal 230-1 and the second terminal 230-2. Therefore, the first internal interconnection structure 210-1, the second internal interconnection structure 210-2, and the connecting metal layer 330 are still electrically isolated from other elements or structures by the dielectric layer stack 204 and the insulating layer stack 272 to maintain Electrically floating.

Please refer to FIG. 4 . FIG. 4 is a cross-sectional view of another semiconductor testing device 200 c provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA′ tangent line in FIG. 1 . It should be noted that, in the semiconductor test element 200c and the semiconductor test element 200b, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 200c is provided, which can be disposed in the die region 104, as shown in FIG. 1 and FIG. 4 . The semiconductor test element 200c may include a semiconductor substrate 202, a first internal interconnection structure 210-1, a second internal interconnection structure 210-2, a connection metal layer 220, a dummy internal interconnection structure 240, and a first internal interconnection structure 240. Three internal interconnect structures 250 . The relative relationship and connection of the semiconductor substrate 202 , the first internal interconnection structure 210 - 1 , the second internal interconnection structure 210 - 2 , the connection metal layer 220 , the dummy internal interconnection structure 240 , and the third internal interconnection structure 250 The relationship is the same as that of the semiconductor test element 200b, so it will not be repeated here.

Please continue to refer to Figure 4. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 260 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 270 on the semiconductor substrate 202 and the molding material 260 . As previously mentioned, the RDL structure 270 may include a plurality of RDLs. In some embodiments, a first redistribution layer 270 - 1 may be formed on the semiconductor substrate 202 and the molding material 260 . As mentioned above, the first redistribution layer 270-1 includes an insulating layer 272-1, a plurality of connecting portions 274-1 and a plurality of plug portions 276-1. After the first redistribution layer 270-1 is formed, a second redistribution layer 270-2 can be formed on the first redistribution layer 270-1. The second redistribution layer 270-2 may include an insulating layer 272-2, a plurality of connecting portions 274-2 disposed in the insulating layer 272-2, and a plurality of electrically connecting the connecting portions 274-1 and the connecting portions 274-2 The plug portion 276-2. As shown in FIG. 4 , the first RDL 270 - 1 and the second RDL 270 - 2 can be electrically connected to the third internal interconnection structure 250 .

In addition, when the first redistribution layer 270-1 and the second redistribution layer 270-2 are fabricated, the first redistribution layer is simultaneously formed on the first internal interconnection structure 210-1 and the second internal interconnection structure 210-2. The cloth layer 270-1 and the second redistribution layer 270-2. In some embodiments, part of the connecting portion 274-2 on the second internal interconnect structure 210-2 serves as a first terminal 230-1 and a second terminal 230-2, and the first terminal 230- 1 is electrically connected to the first internal interconnection structure 210-1, and the second terminal 230-2 is electrically connected to the second internal interconnection structure 210-2. In other words, the first terminal 230-1 and the second terminal 230-2 and the connecting portion 274-2 in the second redistribution layer 270-2 are disposed on the same horizontal layer. It is worth noting that the first terminal 230-1, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 form a via, And the first terminal 230-1 and the second terminal 230-2 are used as test terminals when a semiconductor test is performed, and the semiconductor test system can be used to test whether the manufacturing site of the second redistribution layer 270-2 is powered or not. Sexual overload, semiconductor testing at this site will be detailed later.

In some embodiments, after the semiconductor testing of the second redistribution layer 270-2 at this process site is completed, the fabrication of a plurality of redistribution layers on the second redistribution layer 270-2 may be continued, so as to complete the following steps: The RDL structure 270 shown in FIG. 4 . In addition, after the fabrication of the RDL structure 270 is completed, a contact terminal 280 can be further disposed on the RDL structure 270 . As shown in FIG. 4 , the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnection structure 250 . In some embodiments, the above-mentioned remote back-end process can form the above-mentioned insulating layer stack 272 on the first inter-interconnect structure 210-1, the second inter-interconnect structure 210-2 and the dummy inter-interconnect structure 240, and the insulating layer stack 272 is insulated. The layer stack 272 may cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. 4 . However, in other embodiments, a plurality of connecting portions and a plurality of connecting portions and a plurality of a plug portion, but no contact terminals are provided on these connection portions and the plug portions on the first internal interconnection structure 210-1, the second internal interconnection structure 210-2 and the dummy internal interconnection structure 240; or These connection parts and plug parts are electrically isolated from the first terminal 230-1 and the second terminal 230-2. Therefore, the first internal interconnection structure 210-1, the second internal interconnection structure 210-2, and the connecting metal layer 330 are still electrically isolated from other elements or structures by the dielectric layer stack 204 and the insulating layer stack 272 to maintain Electrically floating.

Please refer to FIG. 5 . FIG. 5 is a cross-sectional view of another semiconductor testing device 200 d provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA′ tangent line in FIG. 1 . It should be noted that, in the semiconductor test element 200d and the semiconductor test element 200c, similar elements are described with the same symbols, so the related details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 200 d is provided, which can be disposed in the die region 104 , as shown in FIGS. 1 and 5 . The semiconductor testing device 200d may include a semiconductor substrate 202, a first internal interconnection structure 210-1, a second internal interconnection structure 210-2, a connection metal layer 220, a dummy internal interconnection structure 240, and a first internal interconnection structure 240. Three internal interconnect structures 250 . The relative relationship and connection of the semiconductor substrate 202 , the first internal interconnection structure 210 - 1 , the second internal interconnection structure 210 - 2 , the connection metal layer 220 , the dummy internal interconnection structure 240 , and the third internal interconnection structure 250 The relationship is the same as that of the semiconductor test element 200c, so it will not be repeated here.

Please continue to refer to Figure 5. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 260 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 270 on the semiconductor substrate 202 and the molding material 260 . As previously mentioned, the RDL structure 270 may include a plurality of RDLs. In some embodiments, a first RDL 270 - 1 and a second RDL 270 - 2 may be formed on the semiconductor substrate 202 and the molding material 260 . As mentioned above, the first redistribution layer 270-1 includes an insulating layer 272-1, a plurality of connecting portions 274-1 and a plurality of plug portions 276-1; the second redistribution layer 270-2 includes an insulating layer 272-2, a plurality of connecting portions 274-2, and a plurality of plug portions 276-2. After the second redistribution layer 270-2 is formed, a third redistribution layer 270-3 can be formed on the second redistribution layer 270-2. The third redistribution layer 270-3 may include an insulating layer 272-3, a plurality of connecting portions 274-3 disposed in the insulating layer 272-3, and a plurality of electrically connecting the connecting portions 274-2 and the connecting portions 274-3 The plug portion 276-3. As shown in FIG. 5 , the first redistribution layer 270 - 1 , the second redistribution layer 270 - 2 and the third redistribution layer 270 - 3 may be electrically connected to the third internal interconnection structure 250 .

In addition, when the above-mentioned three-layer redistribution layers 270-1, 270-2 and 270-3 are fabricated, three-layer redistribution layers are simultaneously formed on the first internal interconnection structure 210-1 and the second internal interconnection structure 210-2. Cloth layers 270-1, 270-2 and 270-3. In some embodiments, the partial connecting portion 274-3 of the third redistribution layer 270-3 serves as a first terminal 230-1 and a second terminal 230-2, and the first terminal 230-1 and The first internal interconnection structure 210-1 is electrically connected, and the second terminal 230-2 is electrically connected with the second internal interconnection structure 210-2. In other words, the first terminal 230-1 and the second terminal 230-2 can be disposed on the same horizontal layer as the connecting portion 274-3 in the third redistribution layer 270-3. As shown in FIG. 5 , the first terminal 230-1, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 may form a via, and the first terminal 230-1 and the second terminal 230-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test system can be used to test the manufacturing site of the third redistribution layer 270-3 Whether electrical overloading occurs, semiconductor testing at this site will be explained in detail later.

In some embodiments, after the semiconductor testing of the process site of the third RDL 270-3 is completed, the fabrication of multiple RDLs on the third RDL 270-3 can be continued to complete the redistribution layer. Fabrication of the cloth layer structure 270 . Alternatively, a contact terminal 280 is directly disposed on the third RDL 270 - 3 (ie, the RDL structure 270 ). As shown in FIG. 5 , the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnection structure 250 . In some embodiments, the above-mentioned remote back-end process can form the above-mentioned insulating layer stack 272 on the first inter-interconnect structure 210-1, the second inter-interconnect structure 210-2 and the dummy inter-interconnect structure 240, and the insulating layer stack 272 is insulated. The layer stack 272 may cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. 5 . Therefore, the first internal interconnection structure 210-1, the second internal interconnection structure 210-2, and the connecting metal layer 230 are still electrically isolated from other elements or structures by the dielectric layer stack 204 and the insulating layer stack 272, maintaining Electrically floating.

Please refer to FIG. 6 . FIG. 6 is a cross-sectional view of another semiconductor testing device 200e provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . It should be noted that, in the semiconductor test element 200e and the semiconductor test element 200d, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 200e is provided, which can be disposed in the die region 104, as shown in FIG. 1 and FIG. 6 . The semiconductor test element 200e may include a semiconductor substrate 202, a first internal interconnection structure 210-1, a second internal interconnection structure 210-2, a connection metal layer 220, a dummy internal interconnection structure 240, and a first internal interconnection structure 240. Three internal interconnect structures 250 . The relative relationship and connection of the semiconductor substrate 202 , the first internal interconnection structure 210 - 1 , the second internal interconnection structure 210 - 2 , the connection metal layer 220 , the dummy internal interconnection structure 240 , and the third internal interconnection structure 250 The relationship is the same as that of the semiconductor test element 200d, so it will not be repeated here.

Please continue to refer to Figure 6. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 260 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 270 on the semiconductor substrate 202 and the molding material 260 . As mentioned above, the RDL structure 270 may include a plurality of RDLs, such as the aforementioned first RDL 270-1, second RDL 270-2 and third RDL 270-3. In some embodiments, the RDL structure 270 may contain more RDLs. Each of the redistribution layers 270 - 1 , 270 - 2 , and 270 - 3 includes an insulating layer, and the insulating layer can be regarded as an insulating layer stack 272 . Each of the redistribution layers 270-1, 270-2, and 270-3 further includes a plurality of connecting portions 274 disposed in the insulating layers, and a plurality of electrically connecting the connecting portions 274 in the insulating layers and the third internal interconnection structure. Plug portion 276 of 250. After the RDL structure 270 is formed, a forming contact terminal 280 may be disposed on the RDL structure 270 . As shown in FIG. 6 , the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnection structure 250 . When forming the contact terminal 280, a first terminal 230-1 can be formed on the first internal interconnection structure 210-1, and a second terminal 230 can be formed on the second internal interconnection structure 210-2 at the same time -2, and the first terminal 230-1 is electrically connected to the first internal interconnection structure 210-1, and the second terminal 230-2 is electrically connected to the second internal interconnection structure 210-2. In other words, the first terminal 230-1 and the second terminal 230-2 and the contact terminal 280 can be disposed on the same horizontal layer. It should be noted that the first terminal 230-1, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 can form a via , and the first terminal 230-1 and the second terminal 230-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test system can be used to test whether the manufacturing site contacting the terminal 280 is electrically overloaded , the semiconductor testing of this site will be explained in detail later.

In some embodiments, since the first terminal 230-1 and the second terminal 230-2 can be used for semiconductor testing, in the subsequent process, the first terminal 230-1 and the second terminal 230-2 may not be Electrically connected to other circuits or structures. Therefore, the first internal interconnection structure 210-1, the second internal interconnection structure 210-2, and the connection metal layer 220 can remain electrically floating except during semiconductor testing.

According to the above description, it can be seen that a plurality of semiconductor test elements 200a, 200b, 200c, 200d, and 200e can be disposed in the die region 104 . Different semiconductor test devices can be used to test whether the electrical overload problem occurs at different process sites. In some embodiments, the semiconductor test elements 200a, 200b, 200c, 200d, and 200e are further used to detect whether there is a problem of electrical overloading of metal ionization at different process sites. These test sites and semiconductor testing will be described in detail later. . In addition, since the semiconductor test is performed through the contact between the probe and the first terminal 230-1 and the second terminal 230-2, the first terminal 230-1 and the second terminal 230 may be caused to -2 is damaged and replaced by stress. Therefore, the first terminal 230-1 and the second terminal 230-2 will not participate in the construction of any electrical connection in the future. As mentioned above, the first terminal 230-1 or the second terminal 230-2 can be covered by the insulating layer stack 272; The circuit is electrically connected. That is, the first endpoint 230-1 and the second endpoint 230-2 can be regarded as sacrificial endpoints, but the present disclosure is not limited thereto.

See also Figure 7. The sensitivity of the semiconductor test element provided by the present disclosure can be adjusted by the location of the connection metal layer 220 . Generally speaking, in the internal interconnection structure, the thickness of the conductive layer is smaller as it is closer to the semiconductor substrate 202 . For example, the thicknesses of the M0 conductive layer, the M1 conductive layer, and the M2 conductive layer may be smaller than the thicknesses of the M3 conductive layer and the conductive layer thereon. The fabrication of the wiring metal layer 220 can be performed simultaneously with the fabrication of any conductive layer. Therefore, when the connection metal layer 220 is disposed at the same position as these lower conductive layers (ie, in the same horizontal layer), of course, it also has the same thickness. The sensitivity of the semiconductor test element is inversely proportional to the thickness of the connecting metal layer. That is to say, when the connection metal layer 220 of the semiconductor test element is located at the same level as these lower conductive layers, its sensitivity is greater than that of the semiconductor test element whose connection metal layer 220 is located at the same level as the higher conductive layer. test element. As shown in FIG. 7 , in some embodiments, the connection metal layer 220 of the semiconductor test element 200f may be at the same level as a higher-level conductive layer, such as an M3 wire layer. Therefore, the sensitivity of the semiconductor test element 200f may be lower than that of the semiconductor test elements 200a, 200b, 200c, 200d, and 200e. In addition, it should be noted that, in order to avoid the problem of CMP recess and provide sufficient mechanical strength, in some embodiments, the semiconductor test element 200f not only includes the first internal interconnection structure 210-1 and the second internal interconnection The dummy internal interconnection structure 240-1 between the structures 210-2 further includes a dummy internal interconnection structure 210-1, a second internal interconnection structure 210-2, a dummy internal interconnection structure 240-1 and a The dummy internal interconnect structure 240 - 2 under the metal layer 220 is connected. The dummy internal interconnection structure 240 - 2 is electrically isolated from the first internal interconnection structure 210 - 1 , the second internal interconnection structure 210 - 2 , the dummy internal interconnection structure 240 - 1 and the connection metal layer 220 .

It should also be noted that, although the arrangement positions of the first terminal 230-1 and the second terminal 230-2 of the semiconductor test element 200f disclosed in FIG. 7 are the same as those of the semiconductor test element 200e, the third The positions of the first terminal 230-1 and the second terminal 230-2 can also be the same as those of the semiconductor test elements 200a, 200b, 200c, and 200d. In other words, in the semiconductor test device provided by the present disclosure, the connection metal layer 220 can be disposed at different conductive layer levels according to different sensitivity requirements. In addition, it is still possible to provide semiconductor test elements for different process sites by the arrangement of different terminal layers.

Besides, the sensitivity of the semiconductor test element can be adjusted not only by the setting position of the connection metal layer 220 but also by the width of the connection metal layer 220 . Since the thickness of the connection metal layer 220 is the same as the thickness of the conductive layer of the same level, after the fabrication level of the connection metal layer 220 is determined, the sensitivity of the semiconductor test element can be adjusted by adjusting the width of the connection metal layer 220. Adjustment. For example, when the connection metal layer 220 is disposed at the level of the M0 conductive layer, the larger width of the connection metal layer 220 enables the semiconductor test element to have higher sensitivity. Therefore, in some embodiments, the width of the connection metal layer 220 can be increased or decreased to obtain higher or lower sensitivity according to the requirements of the sensitivity of the semiconductor test element.

Next, please refer to FIG. 8 . FIG. 8 is a cross-sectional view of another semiconductor testing device 300 a provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA′ tangent in FIG. 1 . In some embodiments of the present disclosure, a semiconductor testing device 300a is provided. As previously indicated, the semiconductor test element 300a may be disposed on a semiconductor wafer 100 as shown in FIG. 1 , which may be disposed within the die area 104 . As shown in FIG. 8 , the semiconductor test element 300 a may include a semiconductor substrate 302 , and in the semiconductor substrate 302 , various types of elements and combinations thereof formed by the aforementioned front-end process may be included. The semiconductor testing device 300 a includes a first internal interconnection structure 310 - 1 , a second internal interconnection structure 310 - 2 and a third internal interconnection structure 310 - 3 , which are disposed on the semiconductor substrate 302 . The first internal interconnection structure 310-1, the second internal interconnection structure 310-2, and the third internal interconnection structure 310-3 are electrically isolated from the semiconductor substrate 302, respectively. In some embodiments, the first interconnect structure 310 - 1 , the second interconnect structure 310 - 2 and the third interconnect structure 310 - 3 are further physically isolated from the semiconductor substrate 302 . As shown in FIG. 8 , the third inner interconnection structure 310-3 is disposed between the first inner interconnection structure 310-1 and the second inner interconnection structure 310-2. Furthermore, it is more important that the first inner interconnection structure 310-1, the second inner interconnection structure 310-2 and the third inner interconnection structure 310-3 are electrically isolated from each other. In some embodiments, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3 are more physically isolated from each other, as shown in FIG. 8 . The semiconductor testing device 300a further includes a first terminal 330-1 and a second terminal 330-2, the first terminal 330-1 is electrically connected with the first internal interconnection structure 310-1, and the second terminal 330-2 is electrically connected to the second internal interconnection structure 310-2.

In some embodiments, the semiconductor testing device 300 a further includes a fourth internal interconnection structure 350 disposed on the semiconductor substrate 302 . The fourth inner interconnection structure 350 is electrically isolated from the first inner interconnection structure 310-1, the second inner interconnection structure 310-2, and the third inner interconnection structure 310-3. In other words, the first internal interconnection structure 330-1, the second internal interconnection structure 330-2, and the third internal interconnection structure 330-3 are electrically floating structures. Different from the above-mentioned electrically floating structure, the fourth internal interconnection structure 350 is electrically connected to the semiconductor substrate 302 . For example, the fourth internal interconnection structure 350 can be electrically connected to various elements in the semiconductor substrate 302 through the contact plugs formed by the mid-stage process, so as to provide electrical connection of these elements.

As shown in FIG. 8 , the first inner interconnection structure 310-1, the second inner interconnection structure 310-2, the third inner interconnection structure 310-3 and the fourth inner interconnection structure 350 may include a plurality of dielectric layers , the dielectric layers can form a dielectric layer stack 304 . The first internal interconnection structure 310-1, the second internal interconnection structure 310-2, the third internal interconnection structure 310-3, and the fourth internal interconnection structure 350 further include a plurality of conductive layers 306, and a plurality of electrical properties The conductive plugs 308 of the conductive layer 306 are connected. The dielectric layer stack 304 , the conductive layer 306 , and the conductive plugs 308 can be formed on the semiconductor substrate 302 by performing the latter process as described above.

In some embodiments, the conductive layer of the first internal interconnection structure 310-1 includes at least one lowermost conductive layer M0-1, and the conductive layer of the second internal interconnection structure 310-2 includes at least one lowermost conductive layer M0- 2. The conductive layer of the third internal interconnection structure 310-3 includes at least one lowermost conductive layer M0-3. As shown in FIG. 8 , there is a gap G1 between the bottommost conductive layer M0-1 and the bottommost conductive layer M0-2, and a gap G2 between the bottommost conductive layer M0-2 and the bottommost conductive layer M0-3. In some embodiments, the widths of the interval G1 and the interval G2 are equal, but the present disclosure is not limited thereto. In addition, the first internal interconnection structure 310-1 and the third internal interconnection structure 310-3 can be physically and electrically isolated by the gap G1; and the second internal interconnection structure 310-2 and the third internal interconnection structure 310 -3 can be physically and electrically isolated by spacing G2.

In some embodiments, when the back-end process is completed, a conductive bump or a conductive pad may be formed on the first internal interconnection structure 310-1 and the second internal interconnection structure 310-2, respectively, to serve as the first The endpoint 330-1 and the second endpoint 330-2. The first terminal 330-1 is electrically connected to the first internal interconnection structure 310-1, and the second terminal 330-2 is electrically connected to the second internal interconnection structure 310-2. The first terminal 330-1 and the second terminal 330-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether the manufacturing site of the back-end process is electrically overloaded. Semiconductor testing will be detailed later.

See Figure 8. In some embodiments, after the semiconductor test is performed, the above-mentioned first terminal 330-1 and second terminal 330-2 may be damaged by stress. Therefore, in the subsequent remote back-end process, the first terminal 330- No other connection layers may be formed on 1 and the second terminal 330-2. For example, after semiconductor testing, die singulation may be performed, followed by forming a molding compound 360 . Then, a remote back-end process is performed to form a redistribution layer structure 370 and contact terminals 380 on the semiconductor substrate 302 and the molding material 360 , as shown in FIG. 8 . The redistribution layer structure 370 may have a plurality of redistribution layers, and the redistribution layers respectively include an insulating layer, a plurality of connecting portions 374 disposed in the insulating layer, and a plurality of plug portions 376 electrically connected to the connecting portions 374 . In some embodiments, the insulating layers of the redistribution layers can be regarded as an insulating layer stack 372 . In addition, a contact terminal 380 may be disposed on the RDL structure 370 , and the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the RDL structure 370 and the fourth internal interconnection structure 350 .

In some embodiments, the above-mentioned remote back-end process may form the above-mentioned insulating layer stack 372 on the first inter-connection structure 310-1, the second inter-interconnect structure 310-2, and the third inter-interconnect structure 310-3 , and the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. 8 . However, in other embodiments, a plurality of connections may also be formed in the insulating layer stack 372 on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 portion 374 and a plurality of plug portions 376, but these connecting portions 374 and plug portions on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2 and the third internal interconnect structure 310-3 Contact terminals are not provided on 376, or these connecting portions 374 and plug portions 376 are electrically isolated from the first terminal 330-1 and the second terminal 330-2. Therefore, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 are still connected to other elements or structures through the dielectric layer stack 304 and the insulating layer stack 372 Electrical isolation, maintaining electrical floating.

Please refer to FIG. 9 . FIG. 9 is a cross-sectional view of another semiconductor testing device 300 b provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA′ tangent line in FIG. 1 . . It should be noted that, among the semiconductor test element 300b and the semiconductor test element 300a, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 300b is provided, which can be disposed in the die region 104, as shown in FIG. 1 and FIG. 9 . The semiconductor test element 300b may include a semiconductor substrate 302, a first interconnect structure 310-1, a second interconnect structure 310-2, a third interconnect structure 310-3, and a fourth interconnect structure Structure 350. Composition, structure and relative relationship of the aforementioned semiconductor substrate 302 , the first internal interconnection structure 310 - 1 , the second internal interconnection structure 310 - 2 , the third internal interconnection structure 310 - 3 and the fourth internal interconnection structure 350 It is the same as the semiconductor test element 300a, so it is not repeated here.

Please continue to refer to Figure 9. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 360 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360 . As previously mentioned, the RDL structure may include a plurality of RDLs. In some embodiments, a first redistribution layer 370 - 1 may be formed on the semiconductor substrate 302 and the molding material 360 . The first redistribution layer 370-1 includes an insulating layer 372-1, a plurality of connecting portions 374-1 disposed in the insulating layer 372-1, and a plurality of electrically connecting the fourth internal interconnection structure 350 and the connecting portions 374- 1 of the plug portion 376-1. As shown in FIG. 9 , the first redistribution layer 370 - 1 may be electrically connected to the fourth internal interconnection structure 350 .

When forming the first redistribution layer 370-1, an insulating layer 372 may be formed on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 at the same time -1. The connecting portion 374-1 and the plug portion 376-1. In some embodiments, part of the connecting portion 374-1 on the first internal interconnect structure 310-1 and the second internal interconnect structure 310-2 serves as a first terminal 330-1 and a second terminal 330 -2, and the first terminal 330-1 is electrically connected to the first internal interconnection structure 310-1 through the plug portion 376-1, and the second terminal 330-2 is electrically connected to the first internal interconnection structure 310-1 through the plug portion 376-1 The second internal interconnect structure 310-2 is electrically connected. In other words, the first terminal 330-1 and the second terminal 330-2 and the connecting portion 374-1 in the first redistribution layer 370-1 are disposed on the same horizontal layer. The first terminal 330-1 and the second terminal 330-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether the manufacturing site of the back-end process is electrically overloaded. The semiconductor testing of , will be explained in detail later.

In some embodiments, after the semiconductor testing of the first redistribution layer 370-1 at the process site is completed, the fabrication of a plurality of redistribution layers on the first redistribution layer 370-1 may continue to complete the process. The RDL structure 370 is shown in FIG. 9 . In addition, after the fabrication of the RDL structure 370 is completed, a contact terminal 380 can be further disposed on the RDL structure 370 . As shown in FIG. 9 , the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the redistribution layer structure 370 and the fourth internal interconnection structure 350 . In some embodiments, the above-mentioned remote back-end process may form the above-mentioned insulating layer stack 372 on the first inter-connection structure 310-1, the second inter-interconnect structure 310-2, and the third inter-interconnect structure 310-3 , and the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. 9 . However, in other embodiments, a plurality of connecting portions may also be formed in the insulating layer 372 on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 and a plurality of plug parts, but these connection parts and plug parts on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 are not provided Contact terminal; or these connection parts and plug parts are electrically isolated from the first terminal 330-1 and the second terminal 330-2. Therefore, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 are still connected to other elements or structures through the dielectric layer stack 304 and the insulating layer stack 372 Electrical isolation, maintaining electrical floating.

Please refer to FIG. 10 , which is a cross-sectional view of another semiconductor testing device 300 c provided according to an embodiment of the present disclosure. It should be noted that, among the semiconductor testing element 300c and the semiconductor testing element 300b, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 300 c is provided, which can be disposed in the die region 104 . The semiconductor test element 300c may include a semiconductor substrate 302, a first interconnect structure 310-1, a second interconnect structure 310-2, a third interconnect structure 310-3, and a fourth interconnect structure Structure 350. Composition, structure and relative relationship of the aforementioned semiconductor substrate 302 , the first internal interconnection structure 310 - 1 , the second internal interconnection structure 310 - 2 , the third internal interconnection structure 310 - 3 and the fourth internal interconnection structure 350 It is the same as that of the semiconductor testing device 300b, so it will not be repeated here.

Proceed to Figure 10. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 360 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360 . As previously mentioned, the RDL structure 370 may include a plurality of RDLs. In some embodiments, a first redistribution layer 370 - 1 may be formed on the semiconductor substrate 302 and the molding material 360 . As mentioned above, the first redistribution layer 370-1 includes an insulating layer 372-1, a plurality of connecting portions 374-1 and a plurality of plug portions 376-1. After the first redistribution layer 370-1 is formed, a second redistribution layer 370-2 can be formed on the first redistribution layer 370-1. The second redistribution layer 370-2 may include an insulating layer 372-2, a plurality of connecting portions 374-2 disposed in the insulating layer 372-2, and a plurality of electrically connecting the connecting portions 374-1 and the connecting portions 374-2 The plug portion 376-2. As shown in FIG. 10 , the first RDL 370 - 1 and the second RDL 370 - 2 can be electrically connected to the fourth internal interconnection structure 350 .

In addition, when fabricating the first redistribution layer 370-1 and the second redistribution layer 370-2, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure are simultaneously fabricated. A first redistribution layer 370-1 and a second redistribution layer 370-2 are formed on the connecting structure 310-3. In some embodiments, the part of the connecting portion 374-2 on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 is used as a first terminal 330-1 and a second terminal 330-2, and the first terminal 330-1 is electrically connected to the first internal interconnection structure 310-1, and the second terminal 330-2 is electrically connected to the second internal interconnection structure 310-2 is electrically connected. In other words, the first terminal 330-1 and the second terminal 330-2 may be disposed on the same horizontal layer as the connecting portion 374-2 in the second redistribution layer 370-2. The first terminal 330-1 and the second terminal 330-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether the manufacturing site of the back-end process is electrically overloaded. The semiconductor testing of , will be explained in detail later.

In some embodiments, after the semiconductor testing of the second RDL 370-2 at this process site is completed, the fabrication of multiple RDLs on the second RDL 370-2 can be continued to complete the process. The RDL structure 370 is shown in FIG. 10 . In addition, after the fabrication of the RDL structure 370 is completed, a contact terminal 380 can be further disposed on the RDL structure 370 . As shown in FIG. 10 , the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the redistribution layer structure 370 and the fourth internal interconnection structure 350 . In some embodiments, the above-mentioned remote back-end process may form the above-mentioned insulating layer stack 372 on the first inter-connection structure 310-1, the second inter-interconnect structure 310-2, and the third inter-interconnect structure 310-3 , and the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. 10 . However, in other embodiments, a plurality of connecting portions may also be formed in the insulating layer 372 on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 and a plurality of plug parts, but these connection parts on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 are not connected with the plug parts. Contact terminals are provided; or these connection parts and plug parts are electrically isolated from the first terminal 330-1 and the second terminal 330-2. Therefore, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 are still connected to other elements or structures through the dielectric layer stack 304 and the insulating layer stack 372 Electrical isolation, maintaining electrical floating.

Please refer to FIG. 11 , which is a cross-sectional view of another semiconductor testing device 300d provided according to an embodiment of the present disclosure. It should be noted that, among the semiconductor test element 300d and the semiconductor test element 300c, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor testing device 300 d is provided, which can be disposed in the die region 104 . The semiconductor test element 300d may include a semiconductor substrate 302, a first interconnect structure 310-1, a second interconnect structure 310-2, a third interconnect structure 310-3, and a fourth interconnect structure Structure 350. Composition, structure and relative relationship of the aforementioned semiconductor substrate 302 , the first internal interconnection structure 310 - 1 , the second internal interconnection structure 310 - 2 , the third internal interconnection structure 310 - 3 and the fourth internal interconnection structure 350 It is the same as that of the semiconductor testing device 300a, so it will not be repeated here.

Proceed to Figure 11. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 360 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360 . As previously mentioned, the RDL structure 370 may include a plurality of RDLs. In some embodiments, a first RDL 370 - 1 and a second RDL 370 - 2 may be formed on the semiconductor substrate 302 and the molding material 360 . As mentioned above, the first redistribution layer 370-1 may include an insulating layer 372-1, a plurality of connection portions 374-1, and a plurality of plug portions 376-1. The second redistribution layer 370-2 may include an insulating layer 372-2, a plurality of connection portions 374-2, and a plurality of plug portions 376-2. After forming the second redistribution layer 370-2, a third redistribution layer 370-3 can be formed on the second redistribution layer 370-2. The third redistribution layer 370-3 may include an insulating layer 372-3, a plurality of connecting portions 374-3 disposed in the insulating layer 372-3, and a plurality of electrically connecting the connecting portions 374-2 and the connecting portions 374-3 The plug portion 376-3. As shown in FIG. 11 , the first RDL 370 - 1 , the second RDL 370 - 2 and the third RDL 370 - 3 may be electrically connected to the fourth internal interconnection structure 350 .

In addition, when the above-mentioned three-layer redistribution layers 370-1, 370-2 and 370-3 are fabricated, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure are simultaneously fabricated. Three redistribution layers 370-1, 370-2 and 370-3 are formed on the connecting structure 310-3. In some embodiments, the part of the connecting portion 374-3 on the first internal interconnect structure 310-1 and the second internal interconnect structure 310-2 is used as a first terminal 330-1 and a second terminal 330 -2, and the first terminal 330-1 is electrically connected to the first internal interconnection structure 310-1, and the second terminal 330-2 is electrically connected to the second internal interconnection structure 310-2. In other words, the first terminal 330-1 and the second terminal 330-2 and the connecting portion 374-3 in the third redistribution layer 370-3 may be disposed on the same horizontal layer. The first terminal 330-1 and the second terminal 330-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether the manufacturing site of the back-end process is electrically overloaded. The semiconductor testing of , will be explained in detail later.

In some embodiments, after the third RDL 370 - 3 is completed, the fabrication of the RDL structure 370 is completed. After the semiconductor test at the process site is completed, a contact terminal 380 may be disposed on the RDL structure 370 . As shown in FIG. 11 , the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the redistribution layer structure 370 and the fourth internal interconnection structure 350 . In some embodiments, the above-mentioned remote back-end process may form the insulating layer stack 372 on the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3, And the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. 11 . Therefore, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 are still electrically connected to other elements or structures through the dielectric layer stack 304 and the insulating layer stack 372. isolation, maintaining electrical floating.

Please refer to FIG. 12 , which is a cross-sectional view of another semiconductor testing device 300e provided according to an embodiment of the present disclosure. It should be noted that, among the semiconductor test element 300e and the semiconductor test element 300d, similar elements are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor test device 300 e is provided, which can be disposed in the die region 104 . The semiconductor test element 300e may include a semiconductor substrate 302, a first interconnect structure 310-1, a second interconnect structure 310-2, a third interconnect structure 310-3, and a fourth interconnect structure The structure 350, the composition and structure of the aforementioned semiconductor substrate 302, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2, the third internal interconnection structure 310-3 and the fourth internal interconnection structure 350 The relative relationship is the same as that of the semiconductor test device 300a, so it will not be repeated here.

Proceed to Figure 12. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnection structure, a die singulation may be performed, and then a molding material 360 is formed. Then, a remote back-end process is performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360 . As mentioned above, the RDL structure 370 may include a plurality of RDLs, such as the aforementioned first RDL 370-1, second RDL 370-2, and third RDL 370-3. In some embodiments, the RDL structure 370 may contain more RDLs. Each of the redistribution layers 370 - 1 , 370 - 2 , and 370 - 3 includes an insulating layer, and the insulating layer can be regarded as an insulating layer stack 372 . Each of the redistribution layers 370-1, 370-2, and 370-3 further includes a plurality of connecting portions 374 disposed in the insulating layers, and a plurality of plug portions 376 electrically connected to the connecting portions 374 in the insulating layers. In addition, when fabricating the first redistribution layer 370-1, the second redistribution layer 370-2 and the third redistribution layer 370-3, the first internal interconnection structure 310-1 and the second internal interconnection are made at the same time. A RDL structure 370 including three RDLs is formed on the structure 310-2 and the third internal interconnection structure 310-3. After the RDL structure 370 is formed, a forming contact terminal 380 may be disposed on the RDL structure 370 . It should be noted that, when the contact terminal 380 is formed, the first terminal 330-1 can be formed on the first internal interconnection structure 310-1 and the second internal interconnection structure 310-2 can be formed simultaneously A second endpoint 330-2. In other words, the first terminal 330-1 and the second terminal 330-2 can be disposed on the same horizontal layer as the contact terminal 380. In these embodiments, the first terminal 330-1 is electrically connected to the first interconnect structure 310-1, and the second terminal 330-2 is electrically connected to the second interconnect structure 310-2 . The first terminal 330-1 and the second terminal 330-2 can be used as test terminals when a semiconductor test is performed, and the semiconductor test can be used to test whether the manufacturing site of the back-end process is electrically overloaded. The semiconductor testing of , will be explained in detail later.

In some embodiments, the first terminal 330-1 and the second terminal 330-2 may be used for semiconductor testing. In the subsequent process, the first terminal 330-1 and the second terminal 330-2 may not be electrically connected to other circuits or structures. Therefore, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2 and the third internal interconnection structure 310-3 can still be kept electrically floating except during semiconductor testing.

According to the above description, it can be seen that a plurality of semiconductor test elements 300 a , 300 b , 300 c , 300 d , and 300 e can be disposed in the die region 104 . Different semiconductor test devices can be used to test whether the electrical overload problem occurs at different process sites. In some embodiments, the semiconductor test elements 300a, 300b, 300c, 300d, and 300e are further used to detect whether the dielectric breakdown and electrical overload problem occurs at different process sites. These test sites and semiconductor tests will be detailed later. illustrate. As mentioned above, during semiconductor testing, the probes are in contact with the first terminal 330-1 and the second terminal 330-2, so the first terminal 330-1 and the second terminal 330-1 may be contacted. End point 330-2 is damaged by stress. Therefore, the first terminal 330-1 and the second terminal 330-2 can no longer participate in the construction of any electrical connection in the future. As mentioned above, the first terminal 330-1 or the second terminal 330-2 can be covered by the insulating layer stack 372, or the first terminal 330-1 or the second terminal 330-2 can be no longer connected with other terminals. The circuit is electrically connected. That is, the first endpoint 330-1 and the second endpoint 330-2 can be regarded as sacrificial endpoints, but the present disclosure is not limited thereto.

See also Figure 13. In the semiconductor test elements 300a, 300b, 300c, 300d, and 300e for testing dielectric breakdown, the third internal interconnection structure 310-3 is used as an antenna for attracting charges, so the third internal interconnection structure 310-3 is used as an antenna for attracting charges. The sum of the areas of the conductive layers in the connection structure 310-3 can affect the sensitivity of the semiconductor test elements 300a, 300b, 300c, 300d, 300e. For example, the greater the total area of the conductive layers in the third internal interconnection structure 310-3, the higher the sensitivity of the semiconductor test element. As shown in FIG. 13 , in some embodiments, in the semiconductor test element 300f, the total area of the conductive layers in the third internal interconnection structure 310-3 is smaller than that of the conductive layers in the semiconductor test elements 300a, 300b, 300c, 300d, and 300e. The total area, so the sensitivity of the semiconductor test element 300f is smaller than the sensitivity of the semiconductor test elements 300a, 300b, 300c, 300d, and 300e. In other words, the semiconductor testing device provided by the present disclosure can adjust the sensitivity of the semiconductor testing device by adjusting the total area of the conductive layers in the third internal interconnection structure 310-3.

It should also be noted that, although the arrangement positions of the first terminal 330-1 and the second terminal 330-2 of the semiconductor test element 300f disclosed in FIG. 13 are the same as those of the semiconductor test element 300e, the third The positions of the first terminal 330-1 and the second terminal 330-2 can also be the same as those of the semiconductor test elements 300a, 300b, 300c, and 300d.

Please refer to FIG. 14 . FIG. 14 is a schematic flowchart of a semiconductor testing method according to an embodiment of the present disclosure. As shown in FIG. 14, the semiconductor testing method 40 includes operation 401, operation 410, operation 420, operation 412a, operation 412b, operation 414a and operation 414b. In addition, other operation steps may be included before, during and after the semiconductor testing method 40 provided by the present disclosure for additional operations, and some other operations are only briefly described herein, but are not limited thereto.

In some embodiments, as described in operation 401, a semiconductor structure is received. The semiconductor structure may be a semiconductor wafer, as shown in FIG. 1 , including a plurality of die regions 104 and scribe line regions 102 defined on the semiconductor substrate. Each die region 104 may include various types of semiconductor elements or combinations thereof disposed on the semiconductor substrate, and these elements may be the same as those described above, and thus will not be repeated here. The semiconductor structure may include a first semiconductor test element and a second semiconductor test element, and the first semiconductor test element and the second semiconductor test element are electrically isolated from each other and are respectively electrically isolated from the semiconductor substrate. In some embodiments, the first semiconductor test element may be semiconductor test element 200a, and the second semiconductor test element may be semiconductor test element 300a. In some embodiments, the first semiconductor test element 200a and the second semiconductor test element 300a may be fabricated with the interconnect structure in the die region 104 by a back-end process. Therefore, at the end of the back-end process, the first semiconductor test element 200a and the second semiconductor test element 300a can be used to test whether the problem of electrical overload occurs in the back-end process. It should also be noted that the semiconductor testing method of the present disclosure is a wafer level test.

Please refer to FIGS. 15A and 15B . In some embodiments, operation 410 and operation 420 may be performed simultaneously. For example, in operation 410, the probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the first semiconductor test element 200a, and operation 412a or operation 412b is performed according to the detection result. As described above, the first terminal 230-1 of the first semiconductor test element 200a, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230 -2 constitutes a circuit path. Therefore, as shown in FIG. 15A , when the probe P touches the first terminal 230-1 and the second terminal 230-2, and the detection result is a via, it is determined that the semiconductor structure is in this segment as described in operation 412a. There is no electrical overload problem during the process, so the next process site can be entered.

However, if the problem of electrical overloading occurs in the back-end process, the connection metal layer 220 may be broken due to the excessive accumulation of charges, as shown by the broken part MB in FIG. 15B . A via formed by the terminal 230-1, the first internal interconnection structure 210-1, the connection metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 becomes an open circuit. Therefore, when the probe P touches the first terminal 230-1 and the second terminal 230-2, and the detection result is an open circuit, it is determined as described in operation 412b that the semiconductor structure has undergone metal galvanization during this process. Destructive overload problem.

Please refer to FIGS. 16A and 16B . Simultaneously with the operation 410, in the operation 420, the probe P is used to contact the first terminal 330-1 and the second terminal 330-2 of the second semiconductor test element 300a, and the operation 414a or the operation 414b is performed according to the detection result thereof. . As described above, the first internal interconnection structure 310-1 (and the first terminal 330-1), the second internal interconnection structure 310-2 (and the second terminal 330-2) of the second semiconductor test element 300a ) and the third internal interconnect structure 310-3 are electrically isolated from each other. Therefore, as shown in FIG. 16A, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is an open circuit, it is determined that the semiconductor structure is in this section as described in operation 414a. There is no electrical overload problem during the process, so the next process site can be entered.

However, if the problem of electrical overloading occurs in the back-end process, it may be due to the excessive accumulation of charges between the conductive layers, which eventually exceeds the breakdown voltage of the dielectric layer 304, causing current to flow through the dielectric layer, as indicated by the arrows in FIG. 16B shown, and make the first terminal 330-1, the first internal interconnection structure 310-1, the third internal interconnection structure 310-3, the second internal interconnection structure 310-2 and the second terminal 330-2 constitute a circuit path. Therefore, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is an open circuit, it is determined as described in operation 414b that the semiconductor structure is dielectric in this process. Layer collapse electrical overload problem.

As previously mentioned, the semiconductor test method 30 may be performed at other process sites. For example, after the back-end process is completed, die singulation can be performed, the die is divided and then placed on a carrier wafer, and then the molding material is formed, and the remote back-end process can be started. process to form RDL structures and contact terminals. In some embodiments, the semiconductor testing method 40 may be implemented after each RDL is completed in a remote back-end process, so as to detect whether an electrical overloading problem occurs in the current RDL. In addition, the semiconductor testing method provided by the present disclosure is still a wafer-level testing method when used for testing the remote back-end process.

Please refer to FIGS. 17A and 17B and FIGS. 18A and 18B . In some embodiments, the first semiconductor test element may be semiconductor test element 200b; and the second semiconductor test element may be semiconductor test element 300b.

After the first RDL 270-1/370-1 in the RDL structure 270/370 is completed, operation 410 and operation 420 may be performed simultaneously. For example, in operation 410, the probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the first semiconductor test element 200b, and operation 412a or operation 412b is performed according to the detection result. As shown in FIG. 17A , when the probe P touches the first terminal 230-1 and the second terminal 230-2, and the detection result is a via, it is determined that the semiconductor structure is in the process as described in operation 412a. There is no electrical overload problem, so the next process site can be entered. However, if the electrical overload occurs in the later-stage process, causing the connection metal layer 220 to be broken, as shown by the broken portion MB in FIG. 17B , the detection result is an open circuit. As described in operation 412b, when the detection result is an open circuit, it is determined that the semiconductor structure has a problem of electrical overloading of the metal during the process.

Please refer to FIGS. 18A and 18B . Simultaneously with operation 410, in operation 420, the probe P is used to contact the first terminal 330-1 and the second terminal 330-2 of the second semiconductor test element 300b, and operation 414a or operation 414b is performed according to the detection result thereof . As shown in FIG. 18A , when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is an open circuit, as described in operation 414a, it is determined that the semiconductor structure is in this process There is no electrical overload problem, so the next process site can be entered. However, when the probe P touches the first terminal 330-1 and the second terminal 330-2, and the detection result is a via as shown in FIG. 18B, as described in operation 414b, it is determined that the semiconductor structure is in this section Dielectric collapse and electrical overload occurred during the process.

Please refer to FIGS. 19A and 19B and FIGS. 20A and 20B. In some embodiments, the first semiconductor test element may be the semiconductor test element 200c; and the second semiconductor test element may be the semiconductor test element 300c.

In these embodiments, after the second RDL 270-2/370-2 in the RDL structure 270/370 is completed, operation 410 and operation 420 may be performed simultaneously. For example, in operation 410, the probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the first semiconductor test element 200c, and operation 412a or operation 412b is performed according to the detection result. As shown in FIG. 19A , when the probe P contacts the first terminal 230-1 and the second terminal 230-2, and the detection result is a via, it is determined that the semiconductor structure is in the process as described in operation 412a. There is no electrical overload problem, so the next process site can be entered. However, if the electrical overload occurs during this process, causing the connection metal layer 220 to break down, as shown in the broken portion MB in FIG. 19B , the detection result is an open circuit. As described in operation 412b, when the detection result is an open circuit, it is determined that the semiconductor structure has a problem of electrical overloading of the metal during the process.

Please refer to FIGS. 20A and 20B . Simultaneously with the operation 410, in the operation 420, the probe P is used to contact the first terminal 330-1 and the second terminal 330-2 of the second semiconductor test element 300c, and the operation 414a or the operation 414b is performed according to the detection result thereof. . As shown in FIG. 20A , when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is an open circuit, as described in operation 414a, it is determined that the semiconductor structure is in this process. There is no electrical overload problem in the process, so it can enter the next process site. However, when the probe P touches the first terminal 330-1 and the second terminal 330-2, and the detection result is a via as shown in FIG. 20B, as described in operation 414b, it is determined that the semiconductor structure is in this section The problem of dielectric layer collapse and electrical overload occurs during the process.

Please refer to FIGS. 21A and 21B and FIGS. 22A and 22B. In some embodiments, the first semiconductor test element may be the semiconductor test element 200d; and the second semiconductor test element may be the semiconductor test element 300d.

In these embodiments, after the third RDL 270-3/370-3 in the RDL structure 270/370 is completed, operation 410 and operation 420 may be performed simultaneously. For example, in operation 410, the probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the first semiconductor test element 200d, and operation 412a or operation 412b is performed according to the detection result. As shown in FIG. 21A , when the probe P touches the first terminal 230-1 and the second terminal 230-2, and the detection result is a via, it is determined that the semiconductor structure is in the process as described in operation 412a. There is no electrical overload problem, so the next process site can be entered. However, if the electrical overload occurs during this process and causes the connection metal layer 220 to break down, as shown in the broken portion MB in FIG. 21B , the detection result is an open circuit. As described in operation 412b, when the detection result is an open circuit, it is determined that the semiconductor structure has a problem of electrical overloading of the metal during the process.

Please refer to FIG. 22A and FIG. 22B. Simultaneously with the operation 410, in the operation 420, the probe P is used to contact the first terminal 330-1 and the second terminal 330-2 of the second semiconductor test element 300d, and the operation 414a or the operation can be performed according to the detection result thereof. 414b. As shown in FIG. 22A, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is an open circuit, as described in operation 414a, it is determined that the semiconductor structure is in this process There is no electrical overload problem in the process, so it can enter the next process site. However, when the probe P touches the first terminal 330-1 and the second terminal 330-2, and the detection result is a via as shown in FIG. 22B, as described in operation 414b, it is determined that the semiconductor structure is in this section The problem of dielectric layer collapse and electrical overload occurs during the process.

Please refer to FIGS. 23A and 23B and FIGS. 24A and 24B. In some embodiments, the first semiconductor test element may be the semiconductor test element 200e; and the second semiconductor test element may be the semiconductor test element 300e.

In these embodiments, after the redistribution layer structure 270/370 is fabricated, the contact terminals 280/380 can be formed on the redistribution layer 270/370, and the first semiconductor test element 200e and the second semiconductor test element 200e can be formed at the same time. A first terminal 230-1/330-1 and a second terminal 230-2/330-2 are formed on the RDL structure 270/370 of the test element 300e. After that, operations 410 and 420 may be performed. For example, in operation 410, the probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the first semiconductor test element 200e, and operation 412a or operation 412b is performed according to the detection result. As shown in FIG. 23A , when the probe P contacts the first terminal 230-1 and the second terminal 230-2, and the detection result is a via, it is determined that the semiconductor structure is in the process as described in operation 412a. There is no electrical overload problem, so the next process site can be entered. However, if the electrical overload occurs in the later-stage process, causing the connection metal layer 220 to be broken, as shown by the broken portion MB in FIG. 23B , the detection result is an open circuit. As described in operation 412b, when the detection result is an open circuit, it is determined that the semiconductor structure has a problem of electrical overloading of the metal during the process.

Please refer to FIG. 24A and FIG. 24B. Simultaneously with operation 410, in operation 420, the probe P is used to contact the first terminal 330-1 and the second terminal 330-2 of the second semiconductor test element 300e, and operation 414a or operation 414b is performed according to the detection result thereof . As shown in FIG. 24A, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is an open circuit, as described in operation 414a, it is determined that the semiconductor structure is in this process There is no electrical overload problem in the process, so it can enter the next process site. However, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, and the detection result is a via as shown in FIG. 24B, as described in operation 414b, it is determined that the semiconductor structure is in this section The problem of dielectric layer collapse and electrical overload occurs during the process.

In short, the method can perform simple on/off tests at different process sites by means of a plurality of semiconductor test elements arranged on a semiconductor substrate, and the test results of the on or off circuits can be easily known. Whether the process site is electrically overloaded, and it can be directly determined whether the electrical overload of metal destruction or the breakdown of dielectric layer occurs. That is to say, the semiconductor testing device provided according to the present disclosure can provide timely and accurate test results, which is more beneficial to increase the reliability and process yield of the semiconductor packaging process.

In some embodiments, a semiconductor test element is provided. The semiconductor test element includes: a semiconductor substrate, a first internal interconnection structure, a second internal interconnection structure, a connecting metal layer, a redistribution layer structure, a first terminal and a second terminal. The first internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The connecting metal layer is electrically connected to the first internal interconnection structure and the second internal interconnection structure, and the connecting metal layer is electrically isolated from the semiconductor substrate. The redistribution layer structure is disposed on the first internal interconnection structure and the second internal interconnection structure, and is electrically connected with the first internal interconnection structure and the second internal interconnection structure. The first terminal is electrically connected to the first internal interconnection structure through the redistribution layer structure; and the second terminal is electrically connected to the second internal interconnection structure through the redistribution layer structure .

In some embodiments, a semiconductor test element is provided. The semiconductor test element includes: a semiconductor substrate, a first internal interconnection structure, a second internal interconnection structure, a third internal interconnection structure, a redistribution layer structure, a first terminal and a second terminal point. The first internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate and the first internal interconnection structure. The third internal interconnection structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate, the first internal interconnection structure and the second internal interconnection structure. The RDL structure is disposed on the first interconnect structure, the second interconnect structure, and the third interconnect structure, and is connected to the first interconnect structure and the second interconnect structure Electrical connection. The first terminal is electrically connected to the first internal interconnection structure through the redistribution layer structure; and the second terminal is electrically connected to the second internal interconnection structure through the redistribution layer structure .

In some embodiments, a semiconductor testing method is provided. The method includes: receiving a semiconductor structure, the semiconductor structure including a semiconductor substrate, a first semiconductor test element disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and a first semiconductor test element disposed on the semiconductor substrate and connected to the semiconductor substrate Both the semiconductor substrate and the first semiconductor test element are electrically isolated second semiconductor test elements. The method further includes: performing a first on/off test on the first semiconductor testing element, and performing a second on/off test on the second semiconductor testing element. The method further includes: when the test result of the first via/disconnect is disconnected, judging that a metal galvanic overload has occurred; and when the result of the second via/disconnect test is an open circuit, determining that a dielectric layer has occurred Crash electrical overload.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other procedures and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructions should not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein.

100: Semiconductor Wafers 102: Cutting lane area 104: Die area 200a～200e, 300a～300e: Semiconductor test element 202, 302: Semiconductor substrates 204, 304: Dielectric Layer Stacking 206, 306: Conductive layer 208, 308: Conductive plugs 210-1, 310-1: First internal interconnect structure 210-2, 310-2: Second internal interconnect structure 220: connect metal layer 230-1, 330-1: First endpoint 230-2, 330-2: Second endpoint 240, 240-1, 240-2: Dummy Internal Interconnect Structures 250, 310-3: Third Internal Interconnect Structure 350: Fourth internal interconnect structure 260, 360: Molding materials 270, 370: Redistribution Layer Structure 270-1, 370-1: First Redistribution Layer 270-2, 370-2: Second Redistribution Layer 270-3, 370-3: Third Redistribution Layer 272: Insulation layer stacking 272-1～272-3, 372-1～372-3: Insulation layer 274: Connection part 274-1～274-3, 374-1～374-3: Connection part 276-1～276-3, 376-1～376-3: Plug part 280, 380: touch endpoint G1, G2: Interval MB: The metal layer is broken 40: Method

Aspects of the present disclosure are best understood from the following detailed description read in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a partial schematic diagram of a semiconductor wafer provided according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 3 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 4 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 5 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 6 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 7 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 8 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 9 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 10 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 11 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and may also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 12 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 13 is a cross-sectional view of a semiconductor testing device provided according to an embodiment of the present disclosure, and can also be a cross-sectional schematic view taken along the AA' tangent line in FIG. 1 . FIG. 14 is a schematic flowchart of a testing method according to an embodiment of the present disclosure. 15A and 15B are schematic diagrams according to one or more embodiments of the present disclosure. 16A and 16B are schematic diagrams according to one or more embodiments of the present disclosure. 17A and 17B are schematic diagrams according to one or more embodiments of the present disclosure. 18A and 18B are schematic diagrams according to one or more embodiments of the present disclosure. 19A and 19B are schematic diagrams according to one or more embodiments of the present disclosure. 20A and 20B are schematic diagrams according to one or more embodiments of the present disclosure. 21A and 21B are schematic diagrams according to one or more embodiments of the present disclosure. 22A and 22B are schematic diagrams according to one or more embodiments of the present disclosure. 23A and 23B are schematic diagrams according to one or more embodiments of the present disclosure. 24A and 24B are schematic diagrams according to one or more embodiments of the present disclosure.

40: Method

Claims (10)

A semiconductor test element, comprising: a semiconductor substrate; a first internal interconnection structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate; a second internal interconnection structure disposed on the semiconductor substrate on the semiconductor substrate and electrically isolated from the semiconductor substrate; a connecting metal layer electrically connecting the first internal interconnection structure and the second internal interconnection structure, and the connecting metal layer is electrically isolated from the semiconductor substrate A redistribution layer (redistribution layer, RDL) structure is arranged on the first internal interconnection structure and the second internal interconnection structure, and is electrically connected to the first internal interconnection structure and the second internal interconnection structure connection; a first terminal electrically connected to the first internal interconnect structure through the redistribution layer structure; and a second terminal electrically connected to the second internal interconnection structure through the redistribution layer structure sexual connection, wherein the semiconductor test element further includes a dummy internal interconnection structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and wherein the dummy internal interconnection structure is disposed on the first internal interconnection The structure is electrically isolated from the second internal interconnect structure and from the first internal interconnect structure and the second internal interconnect structure. The semiconductor test element of claim 1, further comprising a third internal interconnection structure, It is disposed on the semiconductor substrate and is electrically connected to the semiconductor substrate, wherein the third internal interconnection structure is electrically isolated from the first internal interconnection structure and the second internal interconnection structure. The semiconductor test device of claim 1, wherein the first internal interconnection structure and the second internal interconnection structure respectively comprise a plurality of dielectric layers, a plurality of conductive layers disposed within the dielectric layers, and A plurality of conductive plugs (vias) electrically connected to the conductive layers are provided. The semiconductor test device of claim 1, wherein the redistribution layer structure comprises a plurality of redistribution layers, and the redistribution layers respectively comprise a plurality of connection parts and a plug part electrically connected to the connection parts. A semiconductor test element, comprising: a semiconductor substrate; a first internal interconnection structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate; a second internal interconnection structure disposed on the semiconductor substrate , and is electrically isolated from the semiconductor substrate and the first internal interconnection structure; a third internal interconnection structure is disposed on the semiconductor substrate and is connected to the semiconductor substrate, the first internal interconnection structure and the second internal interconnection structure The internal interconnection structures are all electrically isolated; a redistribution layer (RDL) structure is disposed on the first internal interconnection structure, the second internal interconnection structure and the third internal interconnection structure, and is connected with the the first internal interconnection structure and the second internal interconnection structure are electrically connected; a first terminal is electrically connected to the first internal interconnection structure through the redistribution layer structure and a second terminal electrically connected to the second internal interconnection structure through the redistribution layer structure, wherein the third internal interconnection structure is disposed between the first internal interconnection structure and the second internal interconnection structure between internal interconnect structures. The semiconductor test device of claim 5, further comprising a fourth internal interconnection structure disposed on the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the fourth internal interconnection structure and the first internal interconnection structure The connecting structure, the second internal interconnection structure and the third internal interconnection structure are all electrically isolated. The semiconductor testing device of claim 5, wherein the first internal interconnection structure, the second internal interconnection structure and the third internal interconnection structure respectively comprise a plurality of dielectric layers, a plurality of which are disposed on the dielectrics Conductive layers within the layers, and a plurality of conductive plugs electrically connected to the conductive layers. A semiconductor testing method, comprising: receiving a semiconductor structure, the semiconductor structure comprising a semiconductor substrate, a first semiconductor testing element disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and a semiconductor substrate disposed on the semiconductor substrate a second semiconductor test element electrically isolated from the semiconductor substrate and the first semiconductor test element; a first pass/disconnect test is performed on the first semiconductor test element; a second semiconductor test element is performed on the second semiconductor test element Make/break test; When the result of the first pass/disconnect test is an open circuit, it is determined that a metal breakdown electrical overload occurs; and when the result of the second pass/disconnect test is an open circuit, it is determined that a dielectric breakdown electrical overload occurs, Wherein the first semiconductor test element includes a dummy internal interconnection structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and wherein the dummy internal interconnection structure is disposed between a first internal interconnection structure and the semiconductor substrate A second internal interconnection structure is electrically isolated between and from the first internal interconnection structure and the second internal interconnection structure. The test method of claim 8, wherein the first semiconductor test element comprises: a connecting metal layer disposed between the first internal interconnection structure and the second internal interconnection structure and electrically connected to the semiconductor substrate isolation; a first terminal electrically connected to the first internal interconnection structure; and a second terminal electrically connected to the second internal interconnection structure. The testing method of claim 8, wherein the second semiconductor test element comprises: a third internal interconnection structure; a fourth internal interconnection structure electrically isolated from the third internal interconnection structure; and a fifth internal interconnection structure The internal interconnection structure is disposed between the third internal interconnection structure and the fourth internal interconnection structure.

Images