CN102044549B - Solid state image capture device and method for manufacturing same - Google Patents

Solid state image capture device and method for manufacturing same Download PDF

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Publication number
CN102044549B
CN102044549B CN201010271652.0A CN201010271652A CN102044549B CN 102044549 B CN102044549 B CN 102044549B CN 201010271652 A CN201010271652 A CN 201010271652A CN 102044549 B CN102044549 B CN 102044549B
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groove
layer
diffusion layer
substrate
semiconductor substrate
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CN102044549A (en
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村越笃
原田翼
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Toshiba Corp
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Toshiba Corp
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Abstract

According to one embodiment, a solid state image capture device includes a multilayered interconnect layer, a semiconductor substrate, a pillar diffusion layer and an insulating member. The multilayered interconnect layer includes an interconnect. The semiconductor substrate is provided on the multilayered interconnect layer and the semiconductor substrate has a through-trench. The pillar diffusion layer is formed in the semiconductor substrate around the through-trench. In addition, an insulating member is filled into the through-trench.

Description

Solid state image capture device and manufacture method thereof
The cross reference of related application
The application based on and require to enjoy in the priority of the formerly Japanese patent application No.2009-237189 submitting on October 14th, 2009; At this, add by reference its full content.
Technical field
The embodiments described herein relates generally to a kind of solid state image capture device and for the manufacture of the method for this equipment.
Background technology
Developed traditionally the solid state image capture device that front is subject to photograph, multilayer interconnection line layer is wherein provided on the end face of Semiconductor substrate; And provide colour filter and lenticule on described multilayer interconnection line layer.In front, be subject to, in the solid state image capture device of photograph, in the surface layer part of Semiconductor substrate, to form photodiode; And in multilayer interconnection line layer, form transfer gate (transfer gate).Photodiode is for example formed by the N-shaped diffusion zone that is divided into each pixel by p-type barrier layer.The light inciding Semiconductor substrate from top via lenticule, colour filter and multilayer interconnection line layer is realized opto-electronic conversion via photodiode; And read generated electronics via transfer gate.
This front is subject to the light utilization ratio of solid state image capture device of photograph very low, and this is because the light entering from the outside just incides in Semiconductor substrate after by multilayer interconnection line layer.Therefore,, when Pixel Dimensions reduces, the light quantity inciding on the photodiode of each pixel reduces; And sensitivity also can reduce undesirably.In addition, when Pixel Dimensions reduces, the distance between pixel also can reduce.Therefore,, when inciding the light in pixel due to the metal interconnecting wires experience diffuse reflection in multilayer interconnection line layer and entering another pixel, also there will be the problem such as colour mixture.Colour mixture causes color resolution to reduce; And possibly cannot distinguish trickle aberration.
In order to solve such problem, the solid state image capture device that a kind of back side is subject to photograph has been proposed, wherein light incides on the bottom surface of Semiconductor substrate, and the one side of multilayer interconnection line layer is not provided.The back side is subject to that the light utilization ratio of solid state image capture device of photograph is higher and sensitivity is also higher, and this is because the light entering from the outside incides in Semiconductor substrate not by multilayer interconnection line layer in the situation that.
For the back side, be subject to the solid state image capture device of photograph, the interconnection line that stretches from multilayer interconnection line layer is problematic.Consider the installation configuration of solid state image capture device, the one side stretching interconnection line upwards entering to light is favourable.Therefore, can expect that the bottom-exposed of making larger ， hole, hole in Semiconductor substrate goes out the interconnection line of multilayer interconnection line layer, and via this hole, the interconnection line exposing directly be carried out to wire-bonded.
Yet in this case,, when forming colour filter in Semiconductor substrate, wire-bonded part cannot be used as the mark for position alignment.Therefore,, when forming colour filter, from support substrates face, irradiate infrared ray; And the shade of the highest interconnection line layer causing due to the infrared ray by support substrates, multilayer interconnection line layer and Semiconductor substrate is identified and with marking.
Yet in this solid state image capture device, the position alignment of the highest interconnection line layer of multilayer interconnection line layer is to utilize the interconnection line layer of its below to carry out as benchmark; The position alignment of the minimum interconnection line layer of multilayer interconnection line layer utilizes contact (contact) to carry out as benchmark; The position alignment of contact utilizes grid to carry out as benchmark; And the position alignment of grid is that utilization is carried out as benchmark at the STI (shallow isolating trough (shallow trench isolation)) of the lower surface formation of Semiconductor substrate.Therefore, from the first benchmark of STI, via grid, contact, minimum interconnection line layer, one or more intermediate interconnection line layers and the highest interconnection line layer, to colour filter, indirectly carry out successively the position alignment of colour filter.On the other hand, also utilize STI as benchmark, to carry out the position alignment on the barrier layer of dividing pixel.
Thereby, because determine the relative position relation between described colour filter and barrier layer a large amount of inter-module ground connection that arrange between colour filter and barrier layer, so fluctuation is undesirably large.As a result, when reduction pixel scale, the height of pixel is integrated very difficult, and this is because be difficult to the border between the colour filter of direct location in the region directly over barrier layer.Although can expect forming independently the alignment mark of the position alignment that is exclusively used in Semiconductor substrate, the quantity of operation can undesirably increase and the process cost of solid state image capture device can extremely undesirably increase.
Accompanying drawing explanation
Figure 1 shows that according to the plane graph of the solid state image capture device of an embodiment;
Figure 2 shows that according to the sectional view of the solid state image capture device of this embodiment;
Fig. 3 A is depicted as according to the electrode pad of the solid state image capture device of this embodiment (electrode pad) region, and Fig. 3 B is depicted as the plane graph in marker material region;
Fig. 4 is depicted as and manufactures according to the sectional view of the operation of the method for the solid state image capture device of this embodiment to Figure 27;
Figure 28 is depicted as according to the sectional view of the solid state image capture device of the first comparative example; And
Figure 29 is depicted as according to the sectional view of the solid state image capture device of the second comparative example.
Embodiment
Conventionally, according to an embodiment, solid state image capture device comprises multilayer interconnection line layer, Semiconductor substrate, column diffusion layer and insulating element.Multilayer interconnection line layer comprises interconnection line.On multilayer interconnection line layer, provide Semiconductor substrate and described Semiconductor substrate to there is groove (through-trench).Column diffusion layer is formed on groove in Semiconductor substrate around.In addition, insulating element is filled in this groove.
According to another embodiment, solid state image capture device comprises multilayer interconnection line layer, Semiconductor substrate, the first column diffusion layer, the second column diffusion layer, insulating element, Impurity Diffusion region, electrode pad and colour filter.Multilayer interconnection line layer comprises interconnection line.On multilayer interconnection line layer, provide Semiconductor substrate and described Semiconductor substrate to there is the first conductive layer and first and second groove.The first groove in Semiconductor substrate forms the first column diffusion layer around and described the first column diffusion layer is connected to interconnection line.The second groove in Semiconductor substrate forms the second column diffusion layer around.Insulating element is filled in each first and second groove.The Impurity Diffusion region of the second conduction type is divided into a plurality of regions by the first conductive layer.Electrode pad provides in Semiconductor substrate and is connected to the first column diffusion layer.In addition, in Semiconductor substrate, provide colour filter for each institute zoning.
According to another embodiment, a kind of method for the manufacture of solid state image capture device is disclosed.Described method comprises makes first and second groove to penetrate the bottom of substrate.At least the bottom of this substrate is made by semi-conducting material, and provides the first conductive layer in the bottom of described substrate.Described method comprises by Impurity injection is formed to the first column diffusion layer around and forms the second column diffusion layer around at the second groove at the first groove in the side of first and second groove.Described method comprises by filling insulating material is formed to insulating element to the inside of each first and second groove.It is, under discernible state, Impurity injection is formed to the Impurity Diffusion region that the first conductive layer is divided into second conduction type in a plurality of regions to the lower surface of this substrate that described method comprises by the insulating element in being filled into the second groove.Described method is included in the formation of substrate below and comprises the multilayer interconnection line layer of interconnection line and described interconnection line is connected to the first column diffusion layer.Described method comprises that top by removing this substrate upper surface in the bottom of this substrate exposes insulating element and first and second column diffusion layer.Described method is included on the upper surface of bottom of this substrate and forms electrode pad and described electrode pad is connected to the first column diffusion layer.In addition, it is above the upper surface of the bottom of this substrate, to form colour filter under discernible state that described method is included in the insulating element being filled in the second groove, for each institute zoning.
It is existing that embodiment of the present invention will be described.
First, will the difference part of this embodiment simply be described.
According to the solid state image capture device of this embodiment, be characterised in that described solid state image capture device is the solid state image capture device that the back side is subject to photograph, wherein from top, irradiate light; On multilayer interconnection line layer, provide Semiconductor substrate; Colour filter etc. is provided thereon; In Semiconductor substrate, make a plurality of grooves; At described groove, form the column diffusion layer of high concentration around; And the inside by filling insulating material to described groove.The a part of column diffusion layer around forming at groove is as conductive component, and this conductive component is connected to by the interconnection line of multilayer interconnection line layer the electrode pad providing in Semiconductor substrate; And be filled into insulating element in the inside of all the other grooves as alignment mark, for the manufacture of during carry out position alignment.In this case, because groove penetrates Semiconductor substrate, so insulating element can be identified from the two sides of Semiconductor substrate.A plurality of grooves are made simultaneously.
Now describe in detail with reference to the accompanying drawings according to the configuration of the solid state image capture device of this embodiment.
Figure 1 shows that according to the plane graph of the solid state image capture device of this embodiment.
Figure 2 shows that according to the sectional view of the solid state image capture device of this embodiment.
Fig. 3 A is depicted as according to the plane graph in the electrode pad region of the solid state image capture device of this embodiment.Fig. 3 B is depicted as the plane graph in marker material region.
In order more easily to watch content shown in Fig. 2, only amplify and show difference part.Therefore, Fig. 2 does not strictly mate with Fig. 1, Fig. 3 A and 3B.
Below, in the configuration of describing solid state image capture device (referring to figs. 1 through Fig. 3 B), the average direction of propagation (optical propagation direction) that is just catching the image time when solid state image capture device is taken as downwards; Rightabout is taken as upwards; And be taken as side direction with the direction of quadrature up and down.On the other hand, in describing the method for manufacturing this solid state image capture device, (with reference to Fig. 4, arrive Figure 27), finished surface (handling surface) is taken as lower surface; Treatment surface (processing surface) is taken as upper surface; And match with the indication making progress downwards.Although due to as described below, treatment surface is reversed in the middle of manufacturing according to the method for the solid state image capture device of this embodiment, therefore in to the description of this manufacture method reverse downwards and the indication making progress, its benchmark is provided in this case.
As shown in Figure 1, in solid state image capture device 1, provide optical receiving region 6 that the light of reception is converted to the signal of telecommunication.From top, the configuration of the outer rim of optical receiving region 6 is rectangle.Many pixels are disposed in the matrix configuration of optical receiving region 6.At optical receiving region 6, provide peripheral circuit region 7 around to drive optical receiving region 6 and the signal of telecommunication of exporting from optical receiving region 6 is carried out and processed.The outer rim configuration of peripheral circuit region 7 is also rectangle.One or more electrode pads region 8 and one or more marker materials region 9 are provided in solid state image capture device 1.To the configuration in electrode pad region 8 and marker material region 9 be described below.
As shown in Figure 2, according to providing support substrate 11 in the solid state image capture device 1 of this embodiment.Support substrates 11 is for example formed and is guaranteed the strength and stiffness of whole solid state image capture device 1 by silicon.The passivating film 12 of for example being made by silicon dioxide is provided in support substrates 11; And provide multilayer interconnection line layer 13 thereon.In other words, support substrates 11 is bonded on the lower surface of multilayer interconnection line layer 13 via passivating film 12.
In multilayer interconnection line layer 13, in the insulating film of intermediate layer 14 of being made by insulating material, provide multiple layer metal interconnection line 15, described insulating material is such as silicon dioxide.In optical receiving region 6, in the highest part of multilayer interconnection line layer 13, provide transfer gate 16.In electrode pad region 8, in the highest part of multilayer interconnection line layer 13, provide contact 17.Contact 17 is connected to top metal interconnecting wires 15.
The Semiconductor substrate 20 of being made by monocrystalline silicon is provided on multilayer interconnection line layer 13.Top middle formation p-type layer 21 in Semiconductor substrate 20; And in the part in Semiconductor substrate 20 except p-type layer 21, form N-shaped layer 22.Upper surface in Semiconductor substrate 20 provides silicon dioxide film 51; And provide silicon nitride film 52 thereon.Silicon dioxide film 51 and silicon nitride film 52 form antireflection film 53.
In optical receiving region 6, in N-shaped layer 22, form selectively p-type Resistance 23.From top, it seems, the configuration of p-type Resistance 23 is for example lattice configuration.P-type Resistance 23 is divided into a plurality of PD (photodiode) region 25 by Semiconductor substrate 20; And each PD region 25 is corresponding to a pixel of solid state image capture device 1.Via p-type layer 21, electricity is separated each other with p-type Resistance 23 in PD region 25.From top, it seems, the configuration in PD region 25 is for example foursquare substantially; And a plurality of PD region 25 is arranged to matrix configuration.
In the bottom in PD region 25, form the area with high mercury 26 of n+ type conduction type.N-shaped layer 22 is kept intact in the top in PD region 25.In the orlop part in PD region 25, form anti-reverse layer (the inversion preventing layer) 27 of p-type electric-conducting type.Thereby PD region 25 is formed by area with high mercury 26 and N-shaped layer 22; And described PD region 25 is because p-type layer 21, p-type Resistance 23 and anti-reverse layer 27 surround.The impurity (for example phosphorus (P)) that forms alms giver is introduced in area with high mercury 26 and N-shaped layer 22.The impurity (for example boron (B)) that forms acceptor is introduced in p-type layer 21, p-type Resistance 23 and anti-reverse layer 27.In the lower surface of Semiconductor substrate 20, form STI 29 to surround optical receiving region 6.On the other hand, in peripheral circuit region 7, at the lower surface of Semiconductor substrate 20, form reading circuit (not shown) etc.
In optical receiving region 6, on antireflection film 53, provide a plurality of colour filters 54.For example in the region directly over each PD region 25 for each PD region 25 provides colour filter 54.In this case, the region directly over the border between adjacent colour filter 54 is arranged in p-type Resistance 23.Colour filter 54 for example comprises transmit red light and stops the red colour filter of other color of light; Transmit green and stop the green colour filter of other color of light; And transmit blue and stop the blue colour filter of other color of light.On each colour filter 54, provide plano-convex lenticule 55.Thereby, in each pixel of solid state image capture device 1 from each in lenticule 55, colour filter 54 and PD region 25 is provided successively.Also for each pixel provides above-mentioned transfer gate 16.Also for each pixel forms amplifier/reset transistor (not shown).
As shown in Fig. 2 and Fig. 3 A, along the outer rim in electrode pad region 8, in each electrode pad region 8, make the groove 31 of class framework configuration.Antireflection film 53 is not shown in Fig. 3 A and 3B.From top, it seems, the configuration of groove 31 is for example that the length of side is 80 μ m and the square with round and smooth corner substantially.In the region being surrounded by groove 31, make a plurality of grooves 32 with a configuration.From top, it seems, the configuration of each groove 32 is for example that the length of side is the square of 0.5 μ m substantially.Groove 32 is arranged to matrix configuration; And the distance between groove 32 is for example 0.8 μ m.Although illustrated in Fig. 3 A in a groove 31, according to seven row, take advantage of seven row to be furnished with the example of four nineteen grooves 32, can arrange more groove 32.Groove 31 and 32 penetrates Semiconductor substrate 20.
Insulating material, the insulating element 33 and 34 of for example being made by silicon dioxide, is filled into the inside of groove 31 and 32.Insulating element 33 has class framework configuration; And insulating element 34 has the configuration of quadrangle column.Insulating element 33 and 34 penetrates Semiconductor substrate 20.Inner face along groove 31 in Semiconductor substrate 20 forms column diffusion layer 35 around at groove 31.Inner face along groove 32 in Semiconductor substrate 20 forms column diffusion layer 36 around at groove 32.Form column diffusion layer 35 and 36 to surround respectively insulating element 33 and 34 and penetrate Semiconductor substrate 20.Because insulating element 34 has the configuration of quadrangle column as mentioned above, so column diffusion layer 35 has quadrangle column cylindrical configuration.The impurity (for example, boron (B)) that forms acceptor is introduced into column diffusion layer 35 and 36; Column diffusion layer 35 and 36 conduction type are p-types; And its effective impurity concentration is higher than the effective impurity concentration of Semiconductor substrate 20.Effectively impurity concentration is the impurity concentration that conductance is made contributions, i.e. all activated impurity except alms giver's (N-shaped impurity) part with acceptor (p-type impurity) counteracting.For example, column diffusion layer 35 and 36 effective impurity concentration are approximately 1 * 10 20cm -3and the effective impurity concentration of Semiconductor substrate 20 is approximately 1 * 10 12cm -3.
In part in Semiconductor substrate 20 between column body diffused layer 36, form p-type electric-conducting district 37.37YupXing Resistance, p-type electric-conducting district 23 forms simultaneously; And from top, it seems that its configuration is to divide the configuration of the lattice of each groove 32.Thus, the part semiconductor substrate 20 between groove 32, remaining silicon part, has formed high concentration p-type region, and it has the effective impurity concentration higher than the other parts of Semiconductor substrate 20.Column diffusion layer 36He p-type electric-conducting district 37 is connected to the contact 17 of multilayer interconnection line floor 13.
In each electrode pad region 8, in Semiconductor substrate 20, provide the electrode pad 57 being made of metal.From top, it seems, the configuration of electrode pad 57 is for example square.The end portion of silicon nitride film 52 (with reference to Fig. 2) coated electrode pole plate 57.Electrode pad 57 is the regions that surrounded by the groove 31 with class framework configuration, is arranged in the region directly at least a portion groove 32, contacts, and be attached thereto with at least a portion of column diffusion layer 36 with at least a portion in p-type electric-conducting district 37.Thus, in electrode pad region 8, the metal interconnecting wires 15 being formed in multilayer interconnection line floor 13 is connected to electrode pad 57 via the column diffusion layer 36He p-type electric-conducting district 37 being formed in Semiconductor substrate 20.In the example shown in Fig. 3 A, by by electrode pad 57 and the isolated position alignment surplus of guaranteeing when forming electrode pad 57 of the groove 31 with class framework configuration.
As shown in Fig. 2 and Fig. 3 B, in the Semiconductor substrate 20 in marker material region 9, make groove 42.The insulating element 44 of for example being made by the insulating material such as silicon dioxide is filled into the inside of groove 42.Insulating element 44 is the position alignment during for the manufacturing process of solid state image capture device 1 as alignment mark, such as photo-mask process, inspection process etc.In Semiconductor substrate 20, groove 42 forms column diffusion layer 46 around.As described below, make each other groove 31,32 and 42 simultaneously; Form each other column diffusion layer 35,36 and 46 simultaneously; And fill each other insulating element 33,34 and 44 simultaneously.From top, it seems, the configuration of insulating element 44 can be identical with the configuration of insulating element 34 or be differed from one another.
Now use description to manufacture according to the method for the solid state image capture device of this embodiment.
Fig. 4 is depicted as and manufactures according to the sectional view of the operation of the method for the solid state image capture device of this embodiment to Figure 27.
Fig. 4 only shows electrode pad region and shows the region A of Figure 12 to Figure 11.Figure 12, Figure 13 show the cross section identical with Fig. 2 with Figure 15 to Figure 27.Figure 14 shows the region B of Figure 13.Fig. 4 is oppositely vertical with respect to Fig. 2 quilt to Figure 15.Similar with Fig. 2, at Fig. 4, in Figure 27, only amplify and show difference part.
First, as shown in Figure 4, prepare SOI (silicon-on-insulator) substrate 60.In SOI substrate 60, from lower surface, base material 61, BOX oxide-film 62 and silicon layer 63 are provided successively.
Below, describing Fig. 4 in the operation shown in Figure 15, base material 61 faces are used as finished surface; And silicon layer 63 faces are used as treatment surface.Therefore, base material 61 faces are counted as downwards; And silicon layer 63 faces are counted as upwards.Although the light for picture catching does not have incident during manufacturing solid state image capture device 1, at Fig. 4, in Figure 27, still as in Fig. 2, show for showing the arrow of optical propagation direction for simplicity.For solid state image capture device 1 and intermediate products thereof, optical propagation direction is fixed.
Base material 61 is made by monocrystalline silicon and is had a p-type electric-conducting type.BOX oxide-film 62 is made and is for example had the film thickness of 145nm by silicon dioxide.Silicon layer 63 is made and is for example had the film thickness of 3.7 μ m by monocrystalline silicon.The bottom of silicon layer 63 for example has the film thickness of 0.2 μ m and forms the p-type layer 21 of p-type electric-conducting type; And the top of silicon layer 63 for example has the film thickness of 3.5 μ m and forms the N-shaped layer 22 of N-shaped conduction sexual type.Silicon layer 63 is in solid state image capture device 1, to form the part of Semiconductor substrate 20 after completion.Although optical propagation direction is counted as upwards in Fig. 4, at optical propagation direction, be counted as downward in the situation that, silicon layer 63 is corresponding to the bottom of SOI substrate 60.
As shown in Figure 5, on SOI substrate 60, carry out thermal oxidation to form the silicon dioxide film 65 for example with 5nm thickness on N-shaped layer 22.Then, by CVD (chemical vapour deposition (CVD)), form the silicon nitride film 66 for example with 100nm thickness.
Next, as shown in Figure 6, on silicon nitride film 66, form photoresist film 67; And carry out exposure and develop to making opening 67a in making the region of groove 31,32 and 42 (with reference to Fig. 3 A and 3B).Now, for example the width of each opening 67a is set to 0.4 μ m; And all the other width between opening 67a are set to 0.8 μ m.
Then, as shown in Figure 7, use photoresist film 67 as mask and use BOX oxide-film 62 to carry out dry ecthing to remove selectively silicon nitride film 66, silicon dioxide film 65 and silicon layer 63 as stop-layer (stopper).Thus, in silicon layer 63, make groove 31 (with reference to Fig. 3 A), 32 and 42 (with reference to Fig. 3 B) (being hereinafter conventionally also referred to as groove 32 etc.) to penetrate silicon layer 63.Although groove 32 grades penetrate silicon layer 63 and arrive BOX oxide-film 62, groove 32 grades do not penetrate BOX oxide-film 62.Subsequently, by utilizing oxygen plasma to carry out dry-cure and utilizing aqueous sulfuric acid to carry out wet process, remove photoresist film 67.
Then, as shown in Figure 8, carry out CDE (chemical dry ecthing).Thus, about 10nm is eat-back in each side of groove 32 grades.Now, silicon nitride film 66 is not etched; Silicon dioxide film 65 is subject to the protection of silicon nitride film 66 and is not etched; And the silicon layer 63 of side that is only exposed to groove 32 etc. is recessed.As a result, in the upper part of groove 32 grades, silicon dioxide film 65 and silicon nitride film 66 protrude towards the middle body of groove 32 etc., and have the configuration of class eaves.
Next, as shown in Figure 9, carry out thermal oxidation to form the silicon dioxide film 68 for example with 5nm thickness on each side of groove 32 grades.Then, the impurity Implantation such as boron (B).Now, implanted dopant when rotation SOI substrate 60.The injection direction of impurity is with respect to downward direction inclination 5 degree.In other words, use the inclination angle of 5 degree.Accelerating voltage is for example set to 15keV; And injection rate is for example set to 5 * 10 15cm -2.Thus, on the inwall of groove 31, form column diffusion layer 35 (with reference to Fig. 3 A); On the inwall of groove 32, form column diffusion layer 36; And on the inwall of groove 42, form column diffusion layer 46 (with reference to Fig. 3 B).
Now, because the top section of silicon layer 63 is subject to the protection of silicon nitride film 66, so high concentration boron not by Implantation in the class shoulder regions of groove 32 grades.This is because when the film thickness of silicon nitride film 66 is 100nm, and when accelerating voltage B Implanted with 15keV, the peak value penetration range in silicon nitride film is 38.2nm; Even if allow 17.7nm to propagate width (Δ Rp) two times, maximum penetration distance is also only 73.6nm; And silicon nitride film 66 is not penetrated.Therefore, boron is not intensively injected in the class shoulder regions of groove.Therefore, during oxidation processes subsequently, can not launch boron; And oxidation furnace can be not contaminated.
Then, as shown in figure 10, by utilizing LP-CVD (low-pressure chemical vapor deposition) deposition of silica to form silicon dioxide film 69.Now, the amount of the silicon dioxide of deposition is set to the inside of filling reliably groove 32 grades.For example, in the situation that the A/F of groove 32 grades is set to 0.4 μ m, the amount of the silicon dioxide of deposition is set to 0.3 μ m.Thus, silicon dioxide film 69 is also filled into the inside of groove 32 grades.
Next, as shown in figure 11, with silicon nitride film 66, as stop-layer, carry out CMP (chemico-mechanical polishing) to remove silicon dioxide film 69 and only leave silicon dioxide film 69 in the inside of groove 32 etc. from silicon nitride film 66.Thus, in the inside of groove 31,32 and 42, imbed respectively insulating element 33 (with reference to Fig. 3 A), 34 and 44 (with reference to Fig. 3 B) that made by silicon dioxide.Subsequently, carrying out hot phosphoric acid processes to remove silicon nitride film 66.
Thereby, as shown in figure 12, in electrode pad region 8, form groove 31 and 32, column diffusion layer 34 and 36 and insulating element 33 and 34; And in marker material region 9, form groove 42, column diffusion layer 46 and insulating element 44.Because insulating element 44 is formed by silicon dioxide, so insulating element 44 is compared and had high-contrast with the silicon layer 63 of being made by silicon when by electron microscope observation; And can easily identify insulating element 44.Thus, in this stage, insulating element 44 can be from treatment surface one side identification.Therefore, insulating element 44 can be used as alignment mark.At Fig. 4 to the region shown in Figure 11 corresponding to region A shown in Figure 12.
Then, as shown in figure 13, use insulating element 44 as alignment mark, in the inside of silicon layer 63, form the assembly (with reference to Fig. 1) of optical receiving region 6 and peripheral circuit region 7.On SOI substrate 60, form multilayer interconnection line layer 13.Particularly, use insulating element 44 at the upper surface of silicon layer 63, to form STI 29 as alignment mark.Then, use insulating element 44 as alignment mark, boron Implantation formed in N-shaped floor 22 so that in optical receiving region 6 to the p-type Resistance 23 of lattice configuration and in electrode pad region 8, form the p-type electric-conducting district 37 that lattice configures.Now, 23He p-type electric-conducting district, p-type Resistance 37 forms with p-type floor 21 and contacts.Form p-type Resistance 23 silicon layer 63 is divided into a plurality of PD region 25; And in the region between column diffusion layer 36, form p-type electric-conducting district 37.
Then, using insulating element 44 is each pixel region formation transfer gate 16 as alignment mark.Then, by the foreign ion that forms alms giver being injected in the top of silicon layer 63 in optical receiving region 6, form area with high mercury 26.Now, in each part of being divided by p-type Resistance 23 and the part below 26 remains N-shaped layer 22 at area with high mercury.Then, by the Impurity injection that forms acceptor is formed to anti-reverse layer 27 in the top part of silicon layer 63 in optical receiving region 6.Each part of being divided by p-type Resistance 23 thus, forms photodiode (PD) region 25.
Next, in electrode pad region 8, use insulating element 44 as alignment mark, on silicon layer 63, to form contact 17.Contact 17 is connected to column diffusion layer 36He p-type electric-conducting district 37.Then, by depositing interlayer dielectric 14 to bury transfer gate 16 and contact 17 and to form multilayer interconnection line layer 13 by form metal interconnecting wires 15 in interlayer dielectric 14.
During forming diffusion layer and form the operation of above-mentioned multilayer interconnection line layer 13 in silicon layer 63, in optical receiving region 6, form (not shown) such as amplifier transistor, reset transistors.In peripheral circuit region 7, form reading circuit (not shown) etc.Then, deposition of silica on multilayer interconnection line layer 13; Form passivating film 12; And carry out planarized upper surface via CMR.
Figure 14 is the local amplification sectional view of magnification region B of the Figure 13 in this stage.In silicon layer 63 as shown in figure 14, the insulating element 34 of being made by insulating material is filled in groove 32; And form p-type column diffusion layer 36 around at groove 32.In the part of the N-shaped floor 22 between column diffusion layer 36, form p-type electric-conducting district 37; And the conductivity type of this part is reversed p-type.In top part at silicon layer 63 when forming peripheral circuit, form high concentration p-type diffusion layer 38; And form self aligned polycide (salicide) layer 39 thereon, wherein silicon is mixed with metal.P-type diffusion layer 38 and self aligned polycide layer 39 are not shown in other accompanying drawing.Multilayer interconnection line layer 13 is provided on self aligned polycide layer 39; And in multilayer interconnection line layer 13, provide the metal interconnecting wires 15 and the contact 17 that are made of metal.The lower end of contact 17 is connected to self aligned polycide layer 39; And upper end is connected to 15 layers of minimum metal interconnecting wires.
Then, as shown in figure 15, support substrates 11 is adhered to the upper surface of passivating film 12.In other words, via passivating film 12, on the upper surface of multilayer interconnection line layer 13, engage support substrates 11.Support substrates 11 is for example silicon wafer.In operation below, support substrates 11 faces are used as finished surface.Therefore, at Figure 16, in Figure 27, vertical direction is by again reverse and identical with the direction of Fig. 2.Vertical direction and Figure 16 in the following description match to Figure 27.
Next, as shown in figure 16, by using BOX oxide-film 62 to carry out as stop-layer the base material 61 that polishing removes SOI substrate 60.
Then, as shown in figure 17, by utilizing hydrofluoric acid solution to dissolve, remove BOX oxide-film 62.Now, remaining silicon layer 63 forms Semiconductor substrate 20.Thus, at the upper surface of Semiconductor substrate 20, expose insulating element 33,34 and 44 and column diffusion layer 35,36 and 46.Remove the top of insulating element 33,34 and 44 so that upper surface is recessed, thereby produce groove in the part corresponding to groove 31,32 and 42.Now, the etch quantity causing due to hydrofluoric acid solution is set to for example 50% crosses etching to having BOX oxide-film 62 execution of the film thickness of 145nm.In this case, by the about 75nm of silicon dioxide over etching.Therefore, insulating element 33,34 and 44 upper surface are from the upper surface of the Semiconductor substrate 20 recessed about 75nm that begins.
Next, as shown in figure 18, by plasma CVD, form silicon dioxide film 51.Now, the film thickness of silicon dioxide film 51 is set to the film thickness that is filled in reliably the groove of making in groove 32 grades ( groove 31,32 and 42).In above-mentioned example, because the degree of depth of the groove of making in groove 32 is approximately 75nm, the film thickness of silicon dioxide film 51 is for example set to 150nm.Then, by plasma CVD, form and there is for example silicon nitride film 71 of 50nm film thickness.
Then, as shown in figure 19, on silicon nitride film 71, form photoresist film 72; And carry out exposure and develop to making opening 72a in forming the region of electrode pad 57 (with reference to Fig. 2).
Next, as shown in figure 20, with photoresist film 72, as mask, carry out dry ecthing to remove selectively silicon nitride film 71 and silicon dioxide film 51.Thus, in electrode pad region 8, expose Semiconductor substrate 20.Subsequently, utilize oxygen plasma to carry out ashing to remove photoresist film 72.
Then, as shown in figure 21, by sputter successively titanium deposition (Ti), titanium nitride (TiN) and aluminium (Al) to form conducting film 73 on whole surface.For example, the thickness of titanium layer is set to 20nm; The thickness of titanium nitride layer is set to 30nm; And the thickness of aluminium lamination is set to 330nm.The expose portion of conducting film 73 contact semiconductor substrates 20 and be connected to the column diffusion layer 36He p-type electric-conducting district 37 in electrode pad region 8.
Next, as shown in figure 22, on conducting film 73, form photoresist film 74; And carry out exposure and develop to come patterning photoresist film 74 to cover the region that will form electrode pad 57 (with reference to Figure 23).
Then, as shown in figure 23, with photoresist film 74, as mask, carry out dry ecthing to remove selectively conducting film 73.Thus, electrode pad 57 is formed by remaining conducting film 73 in conduction region 8.Now, also by etching, remove silicon nitride film 71 (with reference to Figure 22); And described in be etched in silicon dioxide film 51 and stop.Subsequently, utilize oxygen plasma to carry out ashing to remove photoresist film 74.
Next, as shown in figure 24, by plasma CVD, on silicon dioxide film 51, form silicon nitride film 52 so that coated electrode pole plate 57.Antireflection film 53 is formed by silicon dioxide film 51 and silicon nitride film 52.Now, the optical characteristics of consideration such as transmissivity and refractive index determined the film thickness of silicon nitride film 52 and is for example set as 50nm.
Then, as shown in figure 25, on silicon nitride film 52, form photoresist film 75; And carry out exposure and develop to make opening 75a in the region directly over the middle body at electrode pad 57.
Next, as shown in figure 26, use photoresist film 75 as mask, to carry out dry ecthing so that silicon nitride film 52 is removed in the region under opening 75a.Subsequently, utilize oxygen plasma to carry out ashing to remove photoresist film 75.
Then, as shown in figure 27, carry out the sintering in forming gas so that the fusion of the contact surface between electrode pad 57 and Semiconductor substrate 20 forms the titanium and the silicon that forms Semiconductor substrate 20 of electrode pad 57.Thereby, reduced the contact resistance between electrode pad 57 and column diffusion layer 36 and between electrode pad 57He p-type electric-conducting district 37.Then, in the region directly over PD region 25, on silicon nitride film 52, form red, green and blue colour filter 54.Now, because only utilize thin antireflection film 53 to cover insulating element 44, so insulating element 44 can be identified from treatment surface.Therefore, when forming colour filter 54, insulating element 44 is used as alignment mark.Border between colour filter 54 is arranged in the region directly over p-type Resistance 23.
Next, as shown in Figure 2, use insulating element 44 as alignment mark, on each colour filter 54, form lenticule 55.Thereby, produce the solid state image capture device 1 that the back side is subject to photograph.
Now will the functional effect of this embodiment be described.
First, will the effect that increase position alignment precision be described.
In the manufacturing process of the solid state image capture device 1 of this embodiment, the insulating element 44 being filled in groove 42 is used as alignment mark.Because insulating element 44 is for example formed by silicon dioxide, so insulating element 44 is compared and had high-contrast and can easily be identified with the Semiconductor substrate 20 of being made by silicon when by electron microscope observation for example.Insulating element 44 penetrates Semiconductor substrate 20 (silicon layer 63) and is exposed to upper surface and lower surface.Therefore,, when forming the p-type barrier layer 23 of the operation shown in Figure 13, the insulating element 44 that is exposed to the upper surface (face relative with light entrance face) of silicon layer 63 can be used as alignment mark; And can directly with insulating element 44, as benchmark, come executing location to aim at.On the other hand, when forming the colour filter 54 of the operation shown in Figure 27, the insulating element 44 that is exposed to the upper surface (light entrance face) of Semiconductor substrate 20 can be used as alignment mark; And can directly with insulating element 44, as benchmark, come executing location to aim at.
Therefore, can as benchmark, carry out with identical insulating element 44 position alignment of p-type barrier layer 23 and colour filter 54.Therefore, not occurrence positions skew substantially between p-type barrier layer 23 and colour filter 54; And the border between colour filter 54 can be arranged in the region directly over p-type barrier layer 23 reliably.In other words, the position alignment precision between p-type barrier layer 23 and colour filter 54 is very high.As a result, be easy to realize the height of pixel integrated.
In order to describe in more detail effect, will the first comparative example of this embodiment be described now.
Figure 28 is depicted as according to the sectional view of the solid state image capture device of this comparative example.
In the solid state image capture device 101 of basis this comparative example as shown in figure 28, the lead connecting method of above-mentioned routine techniques is applied to according to this embodiment solid state image capture device 1 (with reference to Fig. 2).In other words, solid state image capture device 101 with according to the difference of the solid state image capture device 1 (with reference to Fig. 2) of this embodiment, be in Semiconductor substrate 20, not make groove 32 grades (with reference to Fig. 2); But make large openings 110.Openings 110 penetrates Semiconductor substrate 20, enters multilayer interconnection line layer 13, and arrives the metal interconnecting wires 115a for connecting.In solid state image capture device 101, going between 111 is directly joined to metal interconnecting wires 115a for engaging via openings 110.
In solid state image capture device 101, do not form insulating element 44 (with reference to Fig. 2).Therefore,, as described with respect to routine techniques above, when manufacturing solid state image capture device 101, STI 29 is used as the benchmark of position alignment.Or, in multilayer interconnection line layer 13 minimum metal interconnecting wires 115b layer utilize infrared ray from below irradiate and when forming colour filter 54, be used as alignment mark.In other words, from STI 29 via transfer gate 16, contact (not shown), 115 layers of the highest metal interconnecting wires, from 115 layers of second metal interconnecting wires at top, indirectly carry out successively the position alignment of colour filter 54 from 115 layers of the 3rd metal interconnecting wires and the minimum metal interconnecting wires 115b layer at top to colour filter 54.The position alignment of on the other hand, dividing the p-type Resistance 23 of pixel is also used STI 29 as benchmark.Therefore, the relative position relation between colour filter 54 and p-type Resistance 23 is determined via the many assemblies between them.So position alignment precision is very low.As a result, be difficult to the border between colour filter 54 to be arranged in the region directly over p-type Resistance 23; And the height that is difficult to realize pixel is integrated.Although can expect increasing the width of p-type Resistance 23, the characteristic of pixel can undesirably reduce thus, that is, the volume in PD region 25 will undesirably reduce, and the saturated number of electronics will reduce and sensitivity will reduce etc.
To the effect that improve position alignment precision be described with several direct examples now.In the following description, taking pel spacing (the layout cycle in PD region 25) is 1.40 μ m, and wherein the width of p-type Resistance 23 is that the width in 0.25 μ m and PD region 25 is 1.15 μ m.In this case, for the border between colour filter 54 being arranged in the region directly over p-type Resistance 23, colour filter 54 must be no more than half of p-type Resistance 23 width (0.25 μ m) with respect to the position alignment precision of p-type Resistance 23, be no more than ± 0.125 μ m.And, in multilayer interconnection line layer 13, form 115 layers of four metal interconnecting wires.
In this case, in the first comparative example, for the alignment precision of STI-transfer gate of 0.025 μ m, the alignment precision of transfer gate-contact of 0.025 μ m, the alignment precision of the ultrared colour filter-the highest metal interconnecting wires layer by transmission of the alignment precision between each metal interconnecting wires of the multilayer interconnection line layer of the alignment precision of the contact of 0.025 μ m-minimum metal interconnecting wires layer, 0.050 μ m and 0.070 μ m, the alignment precision that amounts to STI-colour filter is the quadratic sum of above-mentioned alignment precision, ± { ( 0.025 ) 2 + ( 0.025 ) 2 + ( 0.025 ) 2 + ( 0.050 ) 2 + ( 0.050 ) 2 + ( 0.050 ) 2 + ( 0.070 ) 2 } = ± 0.119 μm 。On the other hand, the alignment precision of STI 29-p type Resistance 23 is 0.070 μ m.Therefore, the alignment precision of p-type Resistance 23-colour filter 54 is its quadratic sums,
Figure BSA00000256458600152
it has undesirably surpassed above-mentioned permissible range (being no more than ± 0.125 μ m).Therefore, the border between colour filter 54 cannot be arranged in the region directly over p-type Resistance 23 reliably.
On the contrary, according to this embodiment, for the same terms of the first comparative example, the alignment precision of insulating element 44-p type Resistance 23 is 0.070 μ m; And the alignment precision of insulating element 44-colour filter 54 is also 0.070 μ m.Therefore, the alignment precision of p-type Resistance 23-colour filter 54 is its quadratic sums, in other words, this precision (is no more than ± 0.125 μ m) in above-mentioned permissible range.Therefore, the border between colour filter 54 can be arranged in the region directly over p-type Resistance 23 reliably.
Now description is reduced to the effect of stretching resistance.
According to this embodiment, the column diffusion layer 36 around forming at groove 32 be used as conductive component in case by the metal interconnecting wires 15 forming in multilayer interconnection line layer 13 to light incident direction stretch (in Fig. 2 upwards).In other words, contact 17 is connected to electrode pad 57 via column diffusion layer 36.By the Impurity injection of for example boron is formed to column diffusion layer 36 in the Semiconductor substrate 20 of being made by monocrystalline silicon.Therefore, this impurity is not separated out (precipitate) in the grain boundary of Semiconductor substrate 20; And effective impurity concentration of column diffusion layer 36 can be enough high.Thus, can reduce the resistance of column diffusion layer 36; And can reduce the stretching resistance when metal interconnecting wires 15 being stretched to solid state image capture device 1 outside.By form p-type electric-conducting district 37 between column diffusion layer 36, described p-type electric-conducting district 37 also contributes to the conduction between contact 17 and electrode pad 57.Therefore, can further reduce stretching resistance.As a result, can realize the high speed operation of solid state image capture device 1.
In order to describe in more detail effect, now the second comparative example of this embodiment will be described.
Figure 29 is depicted as according to the sectional view of the solid state image capture device of this comparative example.
In the solid state image capture device 102 of basis this comparative example as shown in figure 29, on the side of through hole 31,32 and 42 (through hole 32 etc.), form the dielectric film 121 of being made by for example silicon dioxide.Side along through hole 32 and 42 forms dielectric film 121 with class duct arrangement in the side of through hole 32 and 42.The conductive component 122 of being made by the polysilicon that has wherein injected impurity is filled into the inside of through hole 31,32 and 42.Contact 17 and electrode pad 57 are connected to the conductive component 122 being filled in through hole 32.
When manufacturing the solid state image capture device 102 of this comparative example, the dielectric film 121 forming on the side of through hole 42 can be used as alignment mark.Therefore, similar with this embodiment, can realize high position alignment precision.By contact 17 is connected to electrode pad 57 via the conductive component 122 being filled in through hole 32, the metal interconnecting wires 15 forming can be stretched to light entrance face in multilayer interconnection line layer 13.
Yet, according in the solid state image capture device 102 of this comparative example, must increase the impurity concentration of conductive component 122 to reduce stretching resistance.Yet, in Semiconductor substrate 20, make through hole 32 etc., in the situation that its side forms dielectric film 121 and subsequently silicon refilled to the inside of through hole 32 etc., the crystal structure of the silicon refilling inevitably and undesirably has polycrystalline structure.In other words, conductive component 122 is undesirably formed by polysilicon rather than monocrystalline silicon.Therefore, though by a large amount of Impurity injections in conductive component 122 in the situation that, the impurity injecting is undesirably separated out in the grain boundary of polysilicon; And be difficult to increase effective impurity concentration.Therefore, cannot reduce fully stretching resistance.As a result, the high speed operation in solid state image capture device 102 is very difficult.
It will also be appreciated that the inside that metal rather than polysilicon is refilled to groove 32 etc.Yet the filling capacity of metal is less than the filling capacity of silicon.Therefore, must the length-width ratio of groove be remained low.Therefore, be difficult to reduce the size of groove.And in the situation that filling has the metal of low heat resistant, heat treatment step subsequently is also restricted.Therefore, for example between electrode pad 57 and Semiconductor substrate 20, the silicification reaction at interface is inadequate; And there is deviation, such as contact resistance, increase.
On the contrary, in this embodiment, in the Semiconductor substrate 20 of being made by monocrystalline silicon, form column diffusion layer 36He p-type electric-conducting district 37.Therefore, even can not separate out in grain boundary when impurity is introduced in a large number yet.Therefore, effective impurity concentration in column diffusion layer 36He p-type electric-conducting district 37 can be enough high; And can reduce resistance.Do not hindering in the degree that forms groove 32 and column diffusion layer 36, the diameter and the arrangement interval that reduce as much as possible groove 32 are favourable.Thus, reduce the layout cycle of groove 32; Increased the number of the column diffusion layer 36 that is connected to each electrode pad 57; And reduced stretching resistance.As a result, the high speed operation of solid state image capture device 1 is feasible.
Now description is reduced to the effect of process cost.
In this embodiment as above, by form column diffusion layer 36 in electrode pad region 8, realize the conductive component that penetrates Semiconductor substrate 20; And realize by form insulating element 44 in marker material region 9 alignment mark that penetrates Semiconductor substrate 20.In this embodiment, these can form by the operation of same train.Therefore the operation that, does not need to provide special-purpose forms alignment mark; Therefore can keep low process cost.In this embodiment, form 37HepXing Resistance, p-type electric-conducting district 23 simultaneously.This also will keep low process cost.
According in the solid state image capture device 1 of this embodiment, in Semiconductor substrate 20, make and there is the groove 31 of class framework configuration to surround electrode pad region 8; And insulating element 33 is filled into its inside.Thereby the column diffusion layer 36He p-type electric-conducting district 37 connecting between contact 17 and electrode pad 57 can isolate reliably with the other parts of Semiconductor substrate 20.As a result, can from the current path between metal interconnecting wires 15 and electrode pad 57, leak by anti-stop signal; Can prevent that noise from sneaking into described current path; And can reduce the dead resistance of described current path.Because groove 31 and insulating element 33 can with groove 32 and 42 and insulating element 34 and 44 form simultaneously, so can not increase process cost.
Above reference example embodiment has described the present invention.Yet, the invention is not restricted to these exemplary embodiments.Comprising in the degree of main idea of the present invention, the assembly of interpolation, omission or condition change those skilled in the art suitably carry out interpolation, deletion or design change or the operation of to(for) above-mentioned exemplary embodiment are also included within scope of the present invention.
For example, although show in the above-described embodiments the example that the conduction type of column diffusion layer 36 is p-types, the conduction type of column diffusion layer 36 can be also N-shaped.In this case, need between column diffusion layer 36, not form p-type electric-conducting district 37; And N-shaped layer 22 can utilize same as before.Because forming during peripheral circuit region 7 when introducing formation alms giver's impurity, can further reduce stretching resistance by described impurity being incorporated in the bottom of N-shaped layer 22 in electrode pad region 8, so this situation is favourable.
Although show in the above-described embodiments the example that insulating element 33,34 and 44 is formed by silicon dioxide, the present invention is not limited thereto.Insulating element 33,34 and 44 for example can be formed by silicon nitride.
Although show in the above-described embodiments the example that groove 32 and 42 has the configuration of quadrangle column, the present invention is not limited thereto.Groove 32 and 42 for example can have circular column configuration.The configuration of the configuration of groove 32 and groove 42 needs not to be identical.Can consider that conductivity sets the configuration of groove 32; And groove 42 can have the configuration contributing to as alignment mark.For example, from top, it seems, groove 42 can have rectangular arrangement; And insulating element 44 not only can be used to indicate position but also can be used to indicate direction.Although also show in the above-described embodiments groove 31, have the example of foursquare class framework configuration substantially, the present invention is not limited thereto.For example, groove 31 can have annulus configuration.
According to above-mentioned exemplary embodiment, can realize the method that there is the high position alignment precision of assembly and the solid state image capture device of low process cost and manufacture this solid state image capture device.
Although described specific embodiment, these embodiment only provide with exemplary forms, and are not intended to limit the scope of the invention.In fact, can adopt various other forms to realize novel device described here and method; In addition, in the situation that not departing from spirit of the present invention, can carry out various omissions, replacement and change to the form of equipment described here and method.Claims and equivalent thereof are intended to covering may fall into this form or the modification in scope and spirit of the present invention.

Claims (11)

1. a solid state image capture device, comprising:
The multilayer interconnection line layer that comprises interconnection line;
Semiconductor substrate on described multilayer interconnection line layer, described Semiconductor substrate has the first conductive layer and first and second groove;
Described the first groove in described Semiconductor substrate the first column diffusion layer around, described the first column diffusion layer is connected to described interconnection line;
Described the second groove in described Semiconductor substrate the second column diffusion layer around;
Insulating element in each in described first and second groove;
The Impurity Diffusion region of the second conduction type, for being divided into a plurality of regions by described the first conductive layer;
In described Semiconductor substrate and be connected to the electrode pad of described the first column diffusion layer; And
In described Semiconductor substrate for the colour filter of each institute zoning, wherein
In described Semiconductor substrate, form the 3rd groove to surround the region that wherein forms described the first groove, and
Also described insulating element is filled in described the 3rd groove, and
Described insulating element in described the second groove is used as between alignment mark and described the second groove and described the first groove and described the 3rd groove across described a plurality of regions.
2. equipment as claimed in claim 1, is also included in another Impurity Diffusion region of the second conduction type between described the first column diffusion layer,
This first and second column diffusion layer is described the second conduction type.
3. equipment as claimed in claim 1, wherein said column diffusion layer is the first conduction type.
4. for the manufacture of a method for solid state image capture device, comprising:
Make first and second groove to penetrate the bottom of substrate, the described bottom of at least described substrate is made by semi-conducting material, in the described bottom of described substrate, provides the first conductive layer;
By by Impurity injection in the side of described first and second groove, at this first groove, around form the first column diffusion layer and form the second column diffusion layer around at this second groove;
By by filling insulating material to each the inside in described first and second groove, form insulating element;
By the described insulating element in being filled into this second groove, be under discernible state, Impurity injection to be arrived to the lower surface of described substrate, form the Impurity Diffusion region that described the first conductive layer is divided into second conduction type in a plurality of regions;
Below described substrate, form and comprise the multilayer interconnection line layer of interconnection line and described interconnection line is connected to described the first column diffusion layer;
By removing the top of described substrate, the upper surface in the described bottom of described substrate exposes described insulating element and this first and second column diffusion layer;
On this upper surface of the described bottom of described substrate, form electrode pad and described electrode pad is connected to described the first column diffusion layer; And
Described insulating element in being filled into this second groove is under discernible state, forms colour filter, for each institute zoning above this upper surface of the described bottom of described substrate.
5. method as claimed in claim 4, wherein said semi-conducting material is monocrystal material.
6. method as claimed in claim 4, wherein
SOI substrate is used as described substrate, and described top is made by base material and BOX oxide-film, and described BOX oxide-film provides below described base material, and described bottom is made by monocrystalline silicon layer, and
The described top of removing described substrate comprises:
Use described BOX oxide-film as stop-layer, by polishing, remove described base material; And
By dissolving, remove described BOX oxide-film.
7. method as claimed in claim 4 before being also included in and making this first and second groove, forms silicon nitride film on the described lower surface of described substrate,
Forming described column diffusion layer comprises:
By etching, make the side of this first and second groove recessed, make described silicon nitride film relatively outstanding towards the middle body of this first and second groove; And
When the described substrate of rotation, from the direction tilting with respect to upward direction, inject described impurity,
Silicon is used as described semi-conducting material.
8. method as claimed in claim 4, wherein
During forming described column diffusion layer, the conduction type of this first and second column diffusion layer is the second conduction type, and
During forming described Impurity Diffusion region, between described the first column diffusion layer, form another Impurity Diffusion region of described the second conduction type.
9. method as claimed in claim 4, wherein
Make the described bottom that this first and second groove is included in described substrate and make the 3rd groove to surround the region of wherein making this first groove, and
Form described insulating element and comprise the also inside to described the 3rd groove by described filling insulating material.
10. method as claimed in claim 4, is also included in and forms described multilayer interconnection line layer afterwards and before removing the described top of described substrate, above the lower surface of described multilayer interconnection line layer, engage support substrates.
11. methods as claimed in claim 4, wherein, during forming described Impurity Diffusion region and forming described colour filter, the described insulating element being filled in this second groove is used as alignment mark.
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