CN102044521A - Semiconductor component with through guide hole, manufacturing method of semiconductor component and packaging structure of semiconductor component with through guide hole - Google Patents
Semiconductor component with through guide hole, manufacturing method of semiconductor component and packaging structure of semiconductor component with through guide hole Download PDFInfo
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- CN102044521A CN102044521A CN 200910208066 CN200910208066A CN102044521A CN 102044521 A CN102044521 A CN 102044521A CN 200910208066 CN200910208066 CN 200910208066 CN 200910208066 A CN200910208066 A CN 200910208066A CN 102044521 A CN102044521 A CN 102044521A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The invention relates to a semiconductor component with a through guide hole, a manufacturing method of the semiconductor component, and a packaging structure of the semiconductor component with the through guide hole. The semiconductor component with the through guide hole comprises a silicon chip and at least one through guide hole. The silicon chip comprises a silicon substrate and an active circuit layer. The active circuit layer is positioned on a second surface of the silicon substrate and is provided with at least one metal layer. The through guide hole runs through the silicon substrate and comprises a conducting metal. The conducting metal is electrically connected to the metal layer of the active circuit layer, and one surface of the conducting metal is exposed outside a first surface of the silicon substrate. Thereby, a chip can be directly stacked on the semiconductor component, a protective layer and a redistribution layer are not necessary to be formed on the first surface of the silicon substrate, and then the process is simplified and the cost is reduced.
Description
Technical field
The invention relates to a kind of semiconductor subassembly and manufacture method thereof and have the encapsulating structure of semiconductor subassembly, in detail, is the encapsulating structure that has the semiconductor subassembly and the manufacture method thereof of perforating holes and have the semiconductor subassembly of perforating holes about a kind of.
Background technology
With reference to figure 1, show known generalized section with semiconductor subassembly of perforating holes.This known semiconductor subassembly 1 with perforating holes comprises a silicon substrate 11 and at least one perforating holes 12.This silicon substrate 11 has a first surface 111, a second surface 112 and at least one perforation 113, and this perforation 113 runs through this silicon substrate 11.This perforating holes 12 runs through this silicon substrate 11.This perforating holes 12 comprises a barrier layer 121 and a conducting metal 122.This barrier layer 121 is positioned at the sidewall of this perforation 113, and defines a central channel 124.This conducting metal 122 is positioned at this central channel 124.
This is known, and to have the shortcoming of semiconductor subassembly 1 of perforating holes as follows.If when this known semiconductor assembly 1 need electrically connect with other assembly (not shown), then need respectively form a rerouting layer (not shown) respectively at two-sided (first surface 111 and the second surface 112) of this silicon substrate 11.Yet, form the cost costliness of this rerouting layer, and in manufacture process, be difficult for firm this silicon substrate 11, cause yield not good.
Therefore, be necessary to provide a kind of encapsulating structure that has the semiconductor subassembly and the manufacture method thereof of perforating holes and have the semiconductor subassembly of perforating holes, to address the above problem.
Summary of the invention
The invention provides a kind of semiconductor subassembly with perforating holes, it comprises a silicon substrate and at least one perforating holes.This silicon substrate has a first surface, a second surface and at least one perforation, and this perforation runs through this silicon substrate.This perforating holes runs through this silicon substrate, and this perforating holes comprises one first barrier layer, a conducting metal and one second barrier layer.This first barrier layer is positioned at the sidewall of this perforation, and defines one first central channel.This conducting metal is positioned at this first central channel, and has a ring-type sidepiece and a bottom, and this ring-type sidepiece and this bottom define one second central channel, and a bottom surface of this bottom is revealed in outside the second surface of this silicon substrate.This second barrier layer is positioned at this second central channel.
The present invention provides a kind of manufacturing method of semiconductor module with perforating holes in addition, it may further comprise the steps: the semiconductor assembly (a) is provided, comprise a silicon substrate and at least one perforating holes, this silicon substrate has a first surface, one second surface and at least one groove, this groove opening is in this first surface, this perforating holes is positioned at this groove, this perforating holes comprises one first barrier layer, one conducting metal and one second barrier layer, this first barrier layer is positioned at the sidewall of this groove, and define one first central channel, this conducting metal is positioned at this first central channel, and have a ring-type sidepiece and a bottom, this ring-type sidepiece and this bottom define one second central channel, and this second barrier layer is positioned at this second central channel; And (b) remove this silicon substrate of part from the second surface of this silicon substrate, with a bottom surface of the bottom of the conducting metal that appears this perforating holes.
By this; the bottom surface of the bottom of this conducting metal is revealed in outside the second surface of this silicon substrate; and directly be stacked on the carrier, and do not need to form another protective layer and another rerouting layer, and then simplify technology and reduce cost in the second surface of this silicon substrate.In addition, can avoid in the known technology, when this silicon substrate respectively forms a rerouting layer respectively at this first surface and this second surface, be difficult for firm this silicon substrate, and cause the not good problem of yield
The present invention more provides a kind of semiconductor subassembly with perforating holes, and it comprises a silicon and at least one perforating holes.This silicon comprises a silicon substrate and an active lines layer.This silicon substrate has a first surface, a second surface and at least one perforation, and this perforation runs through this silicon substrate.This active lines layer is positioned at the second surface of this silicon substrate, and has at least one metal level and at least one fluting, the position of the perforation of corresponding this silicon substrate in position of this fluting, and this fluting appears this metal level of part.This perforating holes runs through this silicon substrate, and this perforating holes comprises one first barrier layer and a conducting metal.This first barrier layer is positioned at the sidewall of this perforation, and defines one first central channel.This conducting metal is positioned at the fluting of this first central channel and this active lines layer, and is electrically connected to the metal level of this active lines layer, and a surface of this conducting metal is revealed in outside the first surface of this silicon substrate.
The present invention provides a kind of manufacturing method of semiconductor module with perforating holes again, it may further comprise the steps: a silicon (a) is provided, this silicon comprises a silicon substrate and an active lines layer, this silicon substrate has a first surface and a second surface, this active lines layer is positioned at the second surface of this silicon substrate, and has at least one metal level; (b) first surface in this silicon substrate removes this silicon substrate of part and this active lines layer of part, and to form at least one column groove and at least one fluting respectively, this column groove runs through this silicon substrate, and this fluting appears this metal level of part; (c) form a conducting metal in this column groove and this fluting, this conducting metal is electrically connected to the metal level of this active lines layer, and a surface of this conducting metal is revealed in outside the first surface of this silicon substrate; (d) first surface in this silicon substrate removes this silicon substrate of part, and to form at least one annular ditch groove, this annular ditch groove runs through this silicon substrate, and around this conducting metal; Reach and (e) form one first barrier layer in this annular ditch groove.
By this, the surface of this conducting metal is revealed in outside the first surface of this silicon substrate, and is able to direct storehouse one chip thereon, and does not need to form a protective layer and a rerouting layer in the first surface of this silicon substrate, and then simplifies technology and reduce cost.In addition, the thickness of this first barrier layer is 10 μ m to 20 μ m, and when storehouse one chip thereon the time, the scolder that can avoid this chip overflows and causes bridge joint.
The present invention provides a kind of encapsulating structure with semiconductor subassembly of perforating holes again, and it comprises at least one carrier, semiconductor assembly and at least one chip.This semiconductor subassembly is positioned on this carrier, and this semiconductor subassembly comprises a silicon substrate and at least one perforating holes.This silicon substrate has a first surface, a second surface and at least one perforation, and this perforation runs through this silicon substrate.This perforating holes runs through this silicon substrate, and this perforating holes comprises one first barrier layer and a conducting metal.This first barrier layer is positioned at the sidewall of this perforation, and defines one first central channel.This conducting metal is positioned at this first central channel, and a surface of this conducting metal is revealed in outside this silicon substrate.This chip is positioned on this semiconductor subassembly, and the conducting metal that sees through the perforating holes of this semiconductor subassembly is electrically connected to this carrier.
Description of drawings
Fig. 1 shows known generalized section with semiconductor subassembly of perforating holes;
Fig. 2 to Figure 17 shows that the present invention has the schematic diagram of manufacture method of first embodiment of the semiconductor subassembly of perforating holes;
Figure 18 to Figure 19 shows that the present invention has the generalized section of second embodiment of the semiconductor subassembly of perforating holes;
Figure 20 to Figure 23 shows that the present invention has the schematic diagram of manufacture method of the 3rd embodiment of the semiconductor subassembly of perforating holes;
Figure 24 shows that the present invention has the generalized section of the 4th embodiment of the semiconductor subassembly of perforating holes;
Figure 25 to Figure 28 shows that the present invention has the schematic diagram of manufacture method of the 5th embodiment of the semiconductor subassembly of perforating holes;
Figure 29 shows that the present invention has the generalized section of the 6th embodiment of the semiconductor subassembly of perforating holes;
Figure 30 shows that the present invention has the generalized section of first embodiment of encapsulating structure of the semiconductor subassembly of perforating holes;
Figure 31 shows that the present invention has the generalized section of second embodiment of encapsulating structure of the semiconductor subassembly of perforating holes; And
Figure 32 shows that the present invention has the generalized section of the 3rd embodiment of encapsulating structure of the semiconductor subassembly of perforating holes.
Embodiment
Referring to figs. 2 to Figure 15, show that the present invention has the schematic diagram of manufacture method of first embodiment of the semiconductor subassembly of perforating holes.With reference to figure 2 and Fig. 3, a silicon 21 is provided, this silicon 21 comprises a silicon substrate 211 and an active lines layer 212.This silicon substrate 211 has a first surface 2111 and a second surface 2112.This active lines layer 212 is positioned at the second surface 2112 of this silicon substrate 211, and has at least one metal level 2121.Then, preferably, form the first surface 2111 of one first photoresistance 22 in this silicon substrate 211, this first photoresistance 22 has one first opening 221, to appear the first surface 2111 of this silicon substrate 211 of part.
With reference to figure 4 and Fig. 5, remove this silicon substrate 211 of part and this active lines layer 2121 of part according to this first opening 221 in the first surface 2111 of this silicon substrate 211, to form at least one column groove 2114 and at least one fluting 2122 simultaneously, this column groove 2114 runs through this silicon substrate 211, and this fluting 2122 appears this metal level 2121 of part.With reference to figure 6 and Fig. 7, remove this first photoresistance 22, and electroplate a conducting metal 232, make this conducting metal 232 be positioned at the first surface 2111 of this silicon substrate 211 and fill up this column groove 2114 and this fluting 2122.With reference to figure 8 and Fig. 9, remove this conducting metal 232 on the first surface 2111 that is positioned at this silicon substrate 211, only keep this conducting metal 232 that is positioned at this column groove 2114 and this fluting 2122, this conducting metal 232 is electrically connected to the metal level 2121 of this active lines layer 212, and a surface 2321 of this conducting metal 232 is revealed in outside the first surface 2111 of this silicon substrate 211.
With reference to Figure 10 and Figure 11, form the first surface 2111 of one second photoresistance 24 in this silicon substrate 211, this second photoresistance 24 has second opening 241 of a ring-type, to appear the first surface 2111 of this silicon substrate 211 of part.With reference to Figure 12 and Figure 13, remove this silicon substrate 211 of part in the first surface 2111 of this silicon substrate 211, to form at least one annular ditch groove 2113, this annular ditch groove 2113 runs through this silicon substrate 211, and around this conducting metal 232.With reference to Figure 14 and Figure 15, remove this second photoresistance 24, and form one first barrier layer 233 in this annular ditch groove 2113, this first barrier layer 233 defines one first central channel 231.This conducting metal 232 and this first barrier layer 233 form at least one perforating holes 23.
With reference to Figure 16 and Figure 17, remove this silicon substrate 211 of part so that one first end 234 of this perforating holes 23 protrudes from the first surface 2111 of this silicon substrate 211, form first embodiment that the present invention has the semiconductor subassembly 2 of perforating holes simultaneously.With reference to Figure 18 and Figure 19, form at least one surface metal-layer 25, this surface metal-layer 25 is positioned at the surface 2321 of this conducting metal 232, forms second embodiment that the present invention has the semiconductor subassembly 3 of perforating holes simultaneously.In the present embodiment, this surface metal-layer 25 is a surface-treated layer (Surface Finish), form in the electroless-plating mode, and its material is nickel/gold (Ni/Au).Yet, in other was used, this surface metal-layer 25 can be a solder layer (Solder Layer), and this process can not remove this silicon substrate 211 of part, and directly forming this surface metal-layer 25, this surface metal-layer 25 is positioned at the surface 2321 of this conducting metal 232.
Again with reference to Figure 16 and Figure 17, show that respectively the present invention has the vertical view and the generalized section of first embodiment of the semiconductor subassembly of perforating holes.This semiconductor subassembly 2 with perforating holes comprises a silicon 21 and at least one perforating holes 23.This silicon 21 comprises a silicon substrate 211 and an active lines layer 212.This silicon substrate 211 has a first surface 2111, a second surface 2112 and at least one perforation (i.e. the lateral wall of this annular ditch groove 2113), and this perforation (i.e. the lateral wall of this annular ditch groove 2113) runs through this silicon substrate 211.This active lines layer 212 is the second surfaces 2112 that are positioned at this silicon substrate 211, and have at least one metal level 2121 and at least one fluting 2122, the position of the perforation (i.e. the lateral wall of this annular ditch groove 2113) of corresponding this silicon substrate 211 in position of this fluting 2122, and this fluting 2122 appears this metal level 2121 of part.
This perforating holes 23 runs through this silicon substrate 211, and this perforating holes 23 comprises one first barrier layer 233 and a conducting metal 232.In the present embodiment, this perforating holes 23 has one first end 234 and one second end 235, and first end 234 of this perforating holes 23 protrudes from the first surface 2111 of this silicon substrate 211.Yet in other was used, first end 234 of this perforating holes 23 can flush with the first surface 2111 of this silicon substrate 211, as shown in figure 15.This first barrier layer 233 is positioned at the sidewall (i.e. the lateral wall of this annular ditch groove 2113) of the perforation of this silicon substrate 211, and defines one first central channel 231.In the present embodiment, this first barrier layer 233 flushes with the second surface 2112 of silicon substrate 211.This conducting metal 232 is positioned at the fluting 2122 of this first central channel 231 and this active lines layer 212, and be electrically connected to the metal level 2121 of this active lines layer 212, a surface 2321 of this conducting metal 232 is revealed in outside the first surface 2111 of this silicon substrate 211.
Again with reference to Figure 18 and Figure 19, show that respectively the present invention has the vertical view and the generalized section of second embodiment of the semiconductor subassembly of perforating holes.The semiconductor subassembly with perforating holes 3 of present embodiment and the semiconductor subassembly with perforating holes 2 of first embodiment (Figure 14 and Figure 15) are roughly the same, and wherein identical assembly is given identical numbering.Be in this semiconductor subassembly 3 different with first embodiment of present embodiment more comprises at least one surface metal-layer 25, and this surface metal-layer 25 is positioned at the surface 2321 of this conducting metal 232.In the present embodiment, this surface metal-layer 25 is a surface-treated layer (Surface Finish), and it comprises a ground floor 251 and a second layer 252.This ground floor 251 is positioned at the surface 2321 of this conducting metal 232, and the material of this ground floor 251 is nickel (Ni).This second layer 252 is positioned on this ground floor 251, and the material of this second layer 252 is a gold (Au).Yet in other was used, this surface metal-layer 25 can be a solder layer (Solder Layer).
By this; the surface 2321 of this conducting metal 232 is revealed in outside the first surface 2111 of this silicon substrate 211; and be able to direct storehouse one chip 912 (Figure 31) thereon; and do not need to form a protective layer (not shown) and a rerouting layer (not shown) in the first surface 2111 of this silicon substrate 211, and then simplify technology and reduce cost.In addition, this surface metal-layer 25 can be protected this conducting metal 232, to avoid its oxidation.And in the present embodiment, the thickness of this first barrier layer 233 is 10 μ m to 20 μ m, and when storehouse one chip 912 (Figure 31) thereon the time, the scolder 9121 (Figure 31) that can avoid this chip 912 overflows and causes bridge joint.
Referring to figures 20 through Figure 23, show that the present invention has the schematic diagram of manufacture method of the 3rd embodiment of the semiconductor subassembly of perforating holes.With reference to Figure 20, provide semiconductor assembly 20.This semiconductor subassembly 20 comprises a silicon substrate 211 and at least one perforating holes 23.This silicon substrate 211 has a first surface 2111, a second surface 2112 and at least one groove 2113, and this groove 2113 is opened on this first surface 2111.This perforating holes 23 is positioned at this groove 2113, and this perforating holes 23 comprises one first barrier layer 233, a conducting metal 232 and one second barrier layer 236.This first barrier layer 233 is positioned at the sidewall of this groove 2113, and defines one first central channel 231.This conducting metal 232 is positioned at this first central channel 231, and has a ring-type sidepiece 2322 and a bottom 2323, and this ring-type sidepiece 2322 and this bottom 2323 define one second central channel 237.This second barrier layer 236 is positioned at this second central channel 237.In the present embodiment, this perforating holes 23 has one first end 234 and one second end 235, and first end 234 of this perforating holes 23 flushes with the first surface 2111 of this silicon substrate 211.
In the present embodiment, the manufacture method of this semiconductor subassembly 20 is as follows.At first, provide this silicon substrate 211, this silicon substrate 211 has this first surface 2111 and this second surface 2112.Then, remove this silicon substrate 211 of part in the first surface 2111 of this silicon substrate 211, to form a column groove (not shown).Then, electroplate this conducting metal 232, make this conducting metal 232 be positioned at this column groove in the first surface 2111 of this silicon substrate 211.Preferably, make step that this conducting metal 232 is positioned at this column groove as described later.At first, this conducting metal 232 of first surface 2111 sputters in this silicon substrate 211, this conducting metal 232 is positioned on the first surface 2111 of this column groove and this silicon substrate 211, then, electroplate this conducting metal 232, this conducting metal 232 is positioned on the first surface 2111 of this column groove and this silicon substrate 211, last, remove this conducting metal 232 on the first surface 2111 that is positioned at this silicon substrate 211.This conducting metal 232 has a ring-type sidepiece 2322 and a bottom 2323, and this ring-type sidepiece 2322 and this bottom 2323 define one second central channel 237.Then, remove this silicon substrate 211 of part in the first surface 2111 of this silicon substrate 211, to form at least one annular ditch groove 2113, this annular ditch groove 2113 is around this conducting metal 232.At last, dispose an insulating material in this annular ditch groove 2113 and this second central channel 237,, form this semiconductor subassembly 20 simultaneously to form this first barrier layer 233 and this second barrier layer 236.
With reference to Figure 21; in the present embodiment, form a protective layer (Passivation Layer) 26 and one rerouting layer (Redistribution Layer, RDL) 27 in the first surface 2111 of this silicon substrate 211; this protective layer 26 has at least one opening 261, to appear this perforating holes 23 of part.This rerouting layer 27 is positioned at this opening 261, and is electrically connected to this perforating holes 23.
With reference to Figure 22, remove this silicon substrate 211 of part from the second surface 2112 of this silicon substrate 211, with a bottom surface 2321 of the bottom 2323 that appears this conducting metal 232.In the present embodiment, utilize elder generation's grinding after etching method to remove this silicon substrate 211 of part, protrude from the second surface 2112 of this silicon substrate 211 up to second end 235 of this perforating holes 23 from the second surface 2112 of this silicon substrate 211.Yet, in other is used, can only utilize engraving method to remove this silicon substrate 211 of part from the second surface 2112 of this silicon substrate 211.With reference to Figure 23, in the present embodiment, more form at least one surface metal-layer 25, this surface metal-layer 25 is positioned at the bottom surface 2321 of the bottom 2323 of this conducting metal 232, and extend to a side of the bottom 2323 of this conducting metal 232, form the 3rd embodiment that the present invention has the semiconductor subassembly 5 of perforating holes simultaneously.In the present embodiment, this surface metal-layer 25 is a surface-treated layer (Surface Finish), form in the electroless-plating mode, and its material is nickel/gold (Ni/Au).Yet in other was used, this surface metal-layer 25 can be a solder layer (Solder Layer).
Again with reference to Figure 23, show that the present invention has the generalized section of the 3rd embodiment of the semiconductor subassembly of perforating holes.This semiconductor subassembly 5 with perforating holes comprises a silicon substrate 211, at least one perforating holes 23, a protective layer (Passivation Layer) 26, one rerouting layer (Redistribution Layer, RDL) 27 and at least one surface metal-layer 25.This silicon substrate 211 has a first surface 2111, a second surface 2112 and at least one perforation (i.e. the sidewall of this groove 2113), and this perforation (i.e. the sidewall of this groove 2113) runs through this silicon substrate 211.
This perforating holes 23 runs through this silicon substrate 211, and this perforating holes 23 comprises one first barrier layer 233, a conducting metal 232 and one second barrier layer 236.In the present embodiment, this perforating holes 23 has one first end 234 and one second end 235, and first end 234 of this perforating holes 23 flushes with the first surface 2111 of this silicon substrate 211, and second end 235 of this perforating holes 23 protrudes from the second surface 2112 of this silicon substrate 211.This first barrier layer 233 is positioned at the sidewall (i.e. the sidewall of this groove 2113) of the perforation of this silicon substrate 211, and defines one first central channel 231.This conducting metal 232 is positioned at this first central channel 231, and have a ring-type sidepiece 2322 and a bottom 2323, this ring-type sidepiece 2322 and this bottom 2323 define one second central channel 237, and a bottom surface 2321 of this bottom 2323 is revealed in outside the second surface 2112 of this silicon substrate 211, and the bottom 2323 of this conducting metal 232 protrudes from the second surface 2112 of this silicon substrate 211.This second barrier layer 236 is positioned at this second central channel 237.
This protective layer 26 is positioned at the first surface 2111 of this silicon substrate 211, and this protective layer 26 has at least one opening 261, to appear this perforating holes 23 of part.This rerouting layer 27 is positioned at this opening 261, and is electrically connected to this perforating holes 23.This surface metal-layer 25 is positioned at the bottom surface 2321 of the bottom 2323 of this conducting metal 232, and this surface metal-layer 25 extends to a side of the bottom 2323 of this conducting metal 232.In the present embodiment, this surface metal-layer 25 is a surface-treated layer (Surface Finish), and its material is nickel/gold (Ni/Au).Yet in other was used, this surface metal-layer 25 can be a solder layer (Solder Layer).
With reference to Figure 24, show that the present invention has the generalized section of the 4th embodiment of the semiconductor subassembly of perforating holes.The semiconductor subassembly with perforating holes 5 (Figure 23) of the semiconductor subassembly with perforating holes 6 of present embodiment and the 3rd embodiment is roughly the same, and wherein identical assembly is given identical numbering.Different ring-type sidepiece 2322, this first barrier layer 233 of part and these second barrier layers 236 of part that are in this conducting metal 232 of part with the 3rd embodiment of present embodiment more protrude from the second surface 2112 of this silicon substrate 211.
With reference to Figure 25 to Figure 28, show that the present invention has the schematic diagram of manufacture method of the 5th embodiment of the semiconductor subassembly of perforating holes.The manufacturing method of semiconductor module (Figure 20 to Figure 23) with perforating holes of the manufacturing method of semiconductor module with perforating holes of present embodiment and the 3rd embodiment is roughly the same, and wherein identical assembly is given identical numbering.The different bottoms 2323 that more contact this conducting metal 232 in this first barrier layer 233 that are in of present embodiment with the 3rd embodiment.
Again with reference to Figure 28, show that the present invention has the generalized section of the 5th embodiment of the semiconductor subassembly of perforating holes.The semiconductor subassembly with perforating holes 5 (Figure 23) of the semiconductor subassembly with perforating holes 7 of present embodiment and the 3rd embodiment is roughly the same, and wherein identical assembly is given identical numbering, and is extremely shown in Figure 28 as Figure 25.The different bottoms 2323 that more contact this conducting metal 232 in this first barrier layer 233 that are in of present embodiment with the 3rd embodiment.
With reference to Figure 29, show that the present invention has the generalized section of the 6th embodiment of the semiconductor subassembly of perforating holes.The semiconductor subassembly with perforating holes 7 (Figure 28) of the semiconductor subassembly with perforating holes 8 of present embodiment and the 5th embodiment is roughly the same, and wherein identical assembly is given identical numbering.The different second surfaces 2112 that protrude from this silicon substrate 211 in second end 235 of this perforating holes 23 that are in the 5th embodiment of present embodiment, wherein the ring-type sidepiece 2322 of the bottom 2323 of this conducting metal 232, this conducting metal 232 of part, this first barrier layer 233 of part and this second barrier layer 236 of part protrude from the second surface 2112 of this silicon substrate 211.
By this; the bottom surface 2321 of the bottom 2323 of this conducting metal 232 is revealed in outside the second surface 2112 of this silicon substrate 211; and directly be stacked on the carrier 911 (Figure 31 and Figure 32); and do not need to form another protective layer (not shown) and another rerouting layer (not shown) in the second surface 2112 of this silicon substrate 211, and then simplify technology and reduce cost.Even, can avoid in the known technology, when this silicon substrate 211 respectively forms a rerouting layer respectively at this first surface 2111 and this second surface 2112, be difficult for firm this silicon substrate 211, and cause the not good problem of yield.In addition, this surface metal-layer 25 can be protected this conducting metal 232, to avoid its oxidation.
With reference to Figure 30, show that the present invention has the generalized section of first embodiment of encapsulating structure of the semiconductor subassembly of perforating holes.This encapsulating structure 91 with semiconductor subassembly of perforating holes comprises at least one carrier 911, semiconductor assembly, at least one chip 912 and an adhesive body 913.In the present embodiment, this carrier 911 is a silicon substrate body or an organic substrate body.This semiconductor subassembly has second embodiment of the semiconductor subassembly 3 of perforating holes for the present invention.Yet, in other is used, this semiconductor subassembly 3 can be turned over turnback, perhaps, the replaceable one-tenth the present invention of this semiconductor subassembly has first embodiment of the semiconductor subassembly 2 of perforating holes.This semiconductor subassembly 3 is positioned on this carrier 911.This chip 912 is positioned on this semiconductor subassembly 3, and the conducting metal 232 that sees through the perforating holes 23 of this semiconductor subassembly 3 is electrically connected to this carrier 911.
This adhesive body 913 coats a first surface 9111, this semiconductor subassembly 3 and this chip 912 of this carrier 911.Yet, in other is used, this encapsulating structure 91 more comprises a primer (not shown), one active surface 9122 of the first surface 2111 of this this silicon substrate 211 of primer (not shown) covered section and this chip 912 of part, a first surface 9111 of this this carrier 911 of adhesive body 913 covered sections, this semiconductor subassembly 3 and this chip 912.Perhaps, in other was used, this encapsulating structure 91 did not comprise this adhesive body 913, and comprises a primer (not shown), an active surface 9122 of the first surface 2111 of this this silicon substrate 211 of primer (not shown) covered section and this chip 912 of part.
With reference to Figure 31, show that the present invention has the generalized section of second embodiment of encapsulating structure of the semiconductor subassembly of perforating holes.This encapsulating structure 92 with semiconductor subassembly of perforating holes comprises at least one carrier 911, semiconductor assembly, at least one chip 912 and an adhesive body 913.In the present embodiment, this semiconductor subassembly has the 3rd embodiment of the semiconductor subassembly 5 of perforating holes for the present invention.Yet, in other is used, this semiconductor subassembly 5 can be turned over turnback, perhaps, the replaceable one-tenth the present invention of this semiconductor subassembly has the 3rd embodiment of semiconductor subassembly 5 of perforating holes or the 4th embodiment of the semiconductor subassembly 6 that the present invention has perforating holes.This semiconductor subassembly 5 is positioned on this carrier 911.This chip 912 is positioned on this semiconductor subassembly 5, and the conducting metal 232 that sees through the perforating holes 23 of this semiconductor subassembly 5 is electrically connected to this carrier 911.This adhesive body 913 coats a first surface 9111, this semiconductor subassembly 5 and this chip 912 of this carrier 911.
With reference to Figure 32, show that the present invention has the generalized section of the 3rd embodiment of encapsulating structure of the semiconductor subassembly of perforating holes.This encapsulating structure 93 with semiconductor subassembly of perforating holes comprises at least one carrier 911, semiconductor assembly, at least one chip 912 and an adhesive body 913.In the present embodiment, this semiconductor subassembly has the 5th embodiment of the semiconductor subassembly 7 of perforating holes for the present invention.Yet, in other is used, this semiconductor subassembly 7 can be turned over turnback, perhaps, the replaceable one-tenth the present invention of this semiconductor subassembly has the 6th embodiment of the semiconductor subassembly 8 of perforating holes.This semiconductor subassembly 7 is positioned on this carrier 911.This chip 912 is positioned on this semiconductor subassembly 7, and the conducting metal 232 that sees through the perforating holes 23 of this semiconductor subassembly 7 is electrically connected to this carrier 911.This adhesive body 913 coats a first surface 9111, this semiconductor subassembly 7 and this chip 912 of this carrier 911.
Only the foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, practise the foregoing description being made amendment and changing and still do not take off spirit of the present invention in the personage of this technology.Interest field of the present invention claims as described later is listed.
Claims (39)
1. semiconductor subassembly with perforating holes comprises:
One silicon substrate has a first surface, a second surface and at least one perforation, and this perforation runs through this silicon substrate; And
At least one perforating holes runs through this silicon substrate, and this perforating holes comprises:
One first barrier layer is positioned at the sidewall of this perforation, and defines one first central channel;
One conducting metal is positioned at this first central channel, and has a ring-type sidepiece and a bottom, and this ring-type sidepiece and this bottom define one second central channel, and a bottom surface of this bottom is revealed in outside the second surface of this silicon substrate; And
One second barrier layer is positioned at this second central channel.
2. semiconductor subassembly as claimed in claim 1, wherein this perforating holes has one first end and one second end, and first end of this perforating holes flushes with the first surface of this silicon substrate, and second end of this perforating holes flushes with the second surface of this silicon substrate.
3. semiconductor subassembly as claimed in claim 1, wherein this perforating holes has one first end and one second end, and second end of this perforating holes protrudes from the second surface of this silicon substrate.
4. semiconductor subassembly as claimed in claim 3, wherein the bottom of this conducting metal protrudes from the second surface of this silicon substrate.
5. semiconductor subassembly as claimed in claim 4, wherein the ring-type sidepiece of this conducting metal of part, this first barrier layer of part and this second barrier layer of part more protrude from the second surface of this silicon substrate.
6. semiconductor subassembly as claimed in claim 1, wherein this first barrier layer more contacts the bottom of this conducting metal.
7. semiconductor subassembly as claimed in claim 1 more comprises at least one surface metal-layer, and this surface metal-layer is positioned at the bottom surface of the bottom of this conducting metal.
8. semiconductor subassembly as claimed in claim 7, wherein this surface metal-layer extends to a side of the bottom of this conducting metal.
9. manufacturing method of semiconductor module with perforating holes comprises:
(a) provide the semiconductor assembly, comprise a silicon substrate and at least one perforating holes, this silicon substrate has a first surface, one second surface and at least one groove, this groove opening is in this first surface, this perforating holes is positioned at this groove, this perforating holes comprises one first barrier layer, one conducting metal and one second barrier layer, this first barrier layer is positioned at the sidewall of this groove, and define one first central channel, this conducting metal is positioned at this first central channel, and have a ring-type sidepiece and a bottom, this ring-type sidepiece and this bottom define one second central channel, and this second barrier layer is positioned at this second central channel; And
(b) remove this silicon substrate of part from the second surface of this silicon substrate, with a bottom surface of the bottom of the conducting metal that appears this perforating holes.
10. method as claimed in claim 9, wherein this step (a) comprising:
(a1) provide this silicon substrate, this silicon substrate has this first surface and this second surface;
(a2) first surface in this silicon substrate removes this silicon substrate of part, to form a column groove; And
(a3) form this conducting metal in this column groove, make this conducting metal have this ring-type sidepiece and this bottom, this ring-type sidepiece and this bottom define this second central channel; And
(a4) first surface in this silicon substrate removes this silicon substrate of part, and to form at least one annular ditch groove, this annular ditch groove is around this conducting metal; And
(a5) configuration one insulating material is in this annular ditch groove and this second central channel, and to form this first barrier layer and this second barrier layer, this first barrier layer defines this first central channel.
11. method as claimed in claim 9, wherein in this step (a), this perforating holes has one first end and one second end, and first end of this perforating holes flushes with the first surface of this silicon substrate.
12. method as claimed in claim 9, wherein this first barrier layer more contacts the bottom of this conducting metal.
13. method as claimed in claim 9 wherein in this step (b), utilizes etching or elder generation's grinding after etching method to remove this silicon substrate of part from the second surface of this silicon substrate.
14. method as claimed in claim 9, wherein this step (b) comprises that more one forms the step of at least one surface metal-layer afterwards, and this surface metal-layer is positioned at the bottom surface of the bottom of this conducting metal.
15. as the method for claim 14, wherein this surface metal-layer extends to a side of the bottom of this conducting metal.
16. the semiconductor subassembly with perforating holes comprises:
One silicon comprises:
One silicon substrate has a first surface, a second surface and at least one perforation, and this perforation runs through this silicon substrate; And
One active lines layer is positioned at the second surface of this silicon substrate, and has at least one metal level and at least one fluting, the position of the perforation of corresponding this silicon substrate in position of this fluting, and this fluting appears this metal level of part; And
At least one perforating holes runs through this silicon substrate, and this perforating holes comprises:
One first barrier layer is positioned at the sidewall of this perforation, and defines one first central channel; And
One conducting metal is positioned at the fluting of this first central channel and this active lines layer, and is electrically connected to the metal level of this active lines layer, and a surface of this conducting metal is revealed in outside the first surface of this silicon substrate.
17. as the semiconductor subassembly of claim 16, wherein this perforating holes has one first end and one second end, first end of this perforating holes flushes with the first surface of this silicon substrate.
18. as the semiconductor subassembly of claim 16, wherein this perforating holes has one first end and one second end, first end of this perforating holes protrudes from the first surface of this silicon substrate.
19. as the semiconductor subassembly of claim 16, wherein this first barrier layer flushes with the second surface of silicon substrate.
20. as the semiconductor subassembly of claim 16, more comprise at least one surface metal-layer, this surface metal-layer is positioned at the surface of this conducting metal.
21. the manufacturing method of semiconductor module with perforating holes comprises:
(a) provide a silicon, this silicon comprises a silicon substrate and an active lines layer, and this silicon substrate has a first surface and a second surface, and this active lines layer is positioned at the second surface of this silicon substrate, and has at least one metal level;
(b) first surface in this silicon substrate removes this silicon substrate of part and this active lines layer of part, and to form at least one column groove and at least one fluting respectively, this column groove runs through this silicon substrate, and this fluting appears this metal level of part;
(c) form a conducting metal in this column groove and this fluting, this conducting metal is electrically connected to the metal level of this active lines layer, and a surface of this conducting metal is revealed in outside the first surface of this silicon substrate;
(d) first surface in this silicon substrate removes this silicon substrate of part, and to form at least one annular ditch groove, this annular ditch groove runs through this silicon substrate, and around this conducting metal; And
(e) form one first barrier layer in this annular ditch groove, this conducting metal and this first barrier layer form at least one perforating holes.
22. as the method for claim 21, wherein this step (e) comprises that more one removes this silicon substrate of part so that one first end of this perforating holes protrudes from the step of the first surface of this silicon substrate afterwards.
23. as the method for claim 21, wherein this step (e) comprises that more one forms the step of at least one surface metal-layer afterwards, this surface metal-layer is positioned at the surface of this conducting metal.
24. the encapsulating structure with semiconductor subassembly of perforating holes comprises:
At least one carrier;
The semiconductor assembly is positioned on this carrier, comprises;
One silicon substrate has a first surface, a second surface and at least one perforation, and this perforation runs through this silicon substrate; And
At least one perforating holes runs through this silicon substrate, and this perforating holes comprises:
One first barrier layer is positioned at the sidewall of this perforation, and defines one first central channel; And
One conducting metal is positioned at this first central channel, and a surface of this conducting metal is revealed in outside this silicon substrate; And
At least one chip is positioned on this semiconductor subassembly, and the conducting metal that sees through the perforating holes of this semiconductor subassembly is electrically connected to this carrier.
25. as the encapsulating structure of claim 24, wherein this carrier is a silicon substrate body or an organic substrate body.
26. encapsulating structure as claim 24, wherein the conducting metal of the perforating holes of this silicon substrate has a ring-type sidepiece and a bottom, this ring-type sidepiece and this bottom define one second central channel, and a bottom surface of this bottom is revealed in outside the second surface of this silicon substrate, this perforating holes more comprises one second barrier layer, is positioned at this second central channel.
27. as the encapsulating structure of claim 26, wherein this perforating holes has one first end and one second end, first end of this perforating holes flushes with the first surface of this silicon substrate.
28. as the encapsulating structure of claim 26, wherein this perforating holes has one first end and one second end, second end of this perforating holes flushes with the second surface of this silicon substrate.
29. as the encapsulating structure of claim 26, wherein this perforating holes has one first end and one second end, second end of this perforating holes protrudes from the second surface of this silicon substrate.
30. as the encapsulating structure of claim 29, wherein the bottom of this conducting metal protrudes from the second surface of this silicon substrate.
31. as the encapsulating structure of claim 30, wherein the ring-type sidepiece of this conducting metal of part, this first barrier layer of part and this second barrier layer of part more protrude from the second surface of this silicon substrate.
32. as the encapsulating structure of claim 24, wherein this first barrier layer more contacts the bottom of this conducting metal.
33. as the encapsulating structure of claim 26, more comprise at least one surface metal-layer, this surface metal-layer is positioned at the bottom surface of the bottom of this conducting metal.
34. as the encapsulating structure of claim 33, wherein this surface metal-layer extends to a side of the bottom of this conducting metal.
35. encapsulating structure as claim 24, wherein this semiconductor subassembly more comprises an active lines layer, this active lines layer is positioned at the second surface of this silicon substrate, and have at least one metal level and at least one fluting, the position of the perforation of corresponding this silicon substrate in position of this fluting, and this fluting appears this metal level of part, this conducting metal more is positioned at the fluting of this active lines layer, and be electrically connected to the metal level of this active lines layer, a surface of this conducting metal is revealed in outside the first surface of this silicon substrate.
36. as the encapsulating structure of claim 35, wherein this perforating holes has one first end and one second end, first end of this perforating holes flushes with the first surface of this silicon substrate.
37. as the encapsulating structure of claim 35, wherein this perforating holes has one first end and one second end, first end of this perforating holes protrudes from the first surface of this silicon substrate.
38. as the encapsulating structure of claim 35, wherein this first barrier layer flushes with the second surface of silicon substrate.
39. as the encapsulating structure of claim 35, more comprise at least one surface metal-layer, this surface metal-layer is positioned at the surface of this conducting metal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108400122A (en) * | 2017-02-07 | 2018-08-14 | 台湾积体电路制造股份有限公司 | The routing Design of pseudo- metal cap and redistribution lines |
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| JP3990347B2 (en) * | 2003-12-04 | 2007-10-10 | ローム株式会社 | Semiconductor chip, manufacturing method thereof, and semiconductor device |
| CN101281883B (en) * | 2008-05-26 | 2010-06-23 | 日月光半导体制造股份有限公司 | Method for forming threading hole on substrate |
| CN101483150B (en) * | 2009-02-13 | 2010-10-13 | 华中科技大学 | Process for treating silicon through-hole interconnection construction |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108400122A (en) * | 2017-02-07 | 2018-08-14 | 台湾积体电路制造股份有限公司 | The routing Design of pseudo- metal cap and redistribution lines |
| CN108400122B (en) * | 2017-02-07 | 2020-01-03 | 台湾积体电路制造股份有限公司 | Routing design of dummy metal caps and redistribution lines |
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