CN102034798B - Packaging structure and packaging process - Google Patents
Packaging structure and packaging process Download PDFInfo
- Publication number
- CN102034798B CN102034798B CN200910174516.7A CN200910174516A CN102034798B CN 102034798 B CN102034798 B CN 102034798B CN 200910174516 A CN200910174516 A CN 200910174516A CN 102034798 B CN102034798 B CN 102034798B
- Authority
- CN
- China
- Prior art keywords
- wafer
- load
- bearing surface
- wafer module
- external contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Dicing (AREA)
Abstract
The invention discloses a packaging structure and a packaging process. The packaging structure comprises a circuit substrate, a first wafer module, a second wafer module and a packaging adhesive, wherein the circuit substrate is provided with a bearing surface, and the first wafer module and the second wafer module are adjacently arranged on the bearing surface; the first wafer module is providedwith a plurality of first external connection points which are arranged at first intervals; the second wafer module is provided with a plurality of second external connection points which are arranged at second intervals, and the first interval is greater than the second interval; the packaging adhesive is arranged on the bearing surface and covered with the first wafer module and the second wafer module; the packaging adhesive is provided with a plurality of first open pores and a plurality of second open pores; the first open pores are respectively exposed out of the first external connection points; and the second open pores are respectively exposed out of the second external connection points.
Description
Technical field
The invention relates to a kind of encapsulating structure and encapsulation procedure, and particularly relevant for a kind of encapsulating structure and encapsulation procedure that adopts adjacent (side by side) wafer configuration.
Background technology
System in package technology (SIP) is about being the technology of single encapsulation with the two or more chip integratings with standalone feature of wafer scale, its advantage comprises that not only size is less, comprise that also each function wafer can develop separately, so the system in package technology has than system-level wafer (SoC) development rate and lower development cost faster.
(Package on Package, POP) processing procedure is assemble method common in the system in package technology to stacked package, is that the encapsulation unit with the difference in functionality wafer piles up mutually, for example the memory chips encapsulation unit is stacked on the logic wafer package unit.Yet the various memory chips encapsulation units of different size have different pin layouts usually.Do not carrying out under the adjustment of extra configuration, the pin layout of lower chip encapsulation unit (as logic wafer package unit) only can be used for carrying specific memory device wafer package unit.Compatibility and the extendibility of system in package technology have been limited so, relatively.
Summary of the invention
The invention provides a kind of encapsulating structure, can effectively integrate a plurality of wafer modules with different pin layouts, with compatibility and the extendibility that improves follow-up stacked package processing procedure.
The present invention also provides the processing procedure of aforementioned encapsulating structure, and a plurality of wafer modules that have different pin layouts in order to integration are to provide good compatibility and extendibility.
For specifically describing content of the present invention, at this a kind of encapsulating structure is proposed, comprise a circuit base plate, one first wafer module, one second wafer module and a packing colloid.Circuit base plate has a load-bearing surface, and the first wafer module and the second wafer module are adjacent to be disposed on the load-bearing surface.The first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts.The second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein first spacing is greater than second spacing.In addition, packing colloid is disposed on the load-bearing surface, and covers the first wafer module and the second wafer module, and packing colloid has a plurality of first perforates and a plurality of second perforate.First perforate exposes the first external contact respectively, and second perforate exposes the second external contact respectively.
In one embodiment, the first wafer module comprises one first wafer and a plurality of first soldered ball.First wafer configuration be disposed on the load-bearing surface of the first wafer periphery and circuit base plate has a plurality of first weld pads, and first wafer is electrically connected to first weld pad on load-bearing surface.First soldered ball is disposed at respectively on first weld pad, with as the first external contact.
In one embodiment, the first wafer module comprises one first wafer and a plurality of first soldered ball.First wafer configuration is on load-bearing surface, and an end face of first wafer has a plurality of first weld pads.First soldered ball is disposed at respectively on first weld pad, with as the first external contact.
In one embodiment, the second wafer module comprises one second wafer and a plurality of second soldered ball.Second wafer configuration be disposed on the load-bearing surface of the second wafer periphery and circuit base plate has a plurality of second weld pads, and second wafer is electrically connected to second weld pad on load-bearing surface.Second soldered ball is disposed at respectively on second weld pad, with as the second external contact.
In one embodiment, the second wafer module comprises one second wafer and a plurality of second soldered ball.Second wafer configuration is on load-bearing surface, and an end face of second wafer has a plurality of second weld pads.Second soldered ball is disposed at respectively on second weld pad, with as the second external contact.
In one embodiment, described encapsulating structure also comprises one first outer member, is disposed at first wafer top and is engaged to the first external contact.
In one embodiment, described encapsulating structure also comprises one second outer member, is disposed at second wafer top and is engaged to the second external contact.
In one embodiment, described encapsulating structure also comprises a plurality of the 3rd soldered balls, is disposed on the bottom surface of circuit base plate with respect to load-bearing surface.
The present invention also proposes a kind of encapsulation procedure.At first, provide a circuit base plate, this circuit base plate has a load-bearing surface.Then, be adjacent to dispose one first wafer module and one second wafer module on load-bearing surface.The first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts.The second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein first spacing is not equal to second spacing.Then, form a packing colloid on load-bearing surface, to cover the first wafer module and the second wafer module.Afterwards, form a plurality of first perforates and a plurality of second perforate in packing colloid, first perforate exposes the first external contact respectively, and second perforate exposes the second external contact respectively.
In one embodiment, circuit base plate has a plurality of first weld pads and a plurality of second weld pad that is positioned on the load-bearing surface, and the method that is adjacent to dispose the first wafer module and the second wafer module comprises: form a plurality of first soldered balls at first weld pad respectively, with as the first external contact, and form a plurality of second soldered balls at second weld pad respectively, with as the second external contact; And, be adjacent to dispose one first wafer and one second wafer on load-bearing surface, and engage first wafer and second wafer to circuit base plate.First weld pad is positioned on the load-bearing surface of the first wafer periphery and is electrically connected to first wafer, and second weld pad is positioned on the load-bearing surface of the second wafer periphery and is electrically connected to second wafer.
In one embodiment, circuit base plate has a plurality of first weld pads that are positioned on the load-bearing surface, and the method that is adjacent to dispose the first wafer module and the second wafer module comprises: form a plurality of first soldered balls at first weld pad respectively, with as the first external contact; Be adjacent to dispose one first wafer and one second wafer on load-bearing surface, and engage first wafer and second wafer to circuit base plate, wherein first weld pad is positioned on the load-bearing surface of the first wafer periphery and is electrically connected to first wafer, and an end face of second wafer has a plurality of second weld pads; And, form a plurality of second soldered balls at second weld pad respectively, with as the second external contact.
In one embodiment, the method that is adjacent to dispose the first wafer module and the second wafer module comprises: be adjacent to dispose one first wafer and one second wafer on load-bearing surface, and engage first wafer and second wafer to circuit base plate, wherein an end face of first wafer has a plurality of first weld pads, and an end face of second wafer has a plurality of second weld pads; Form a plurality of first soldered balls at first weld pad respectively, with as the first external contact; And, form a plurality of second soldered balls at second weld pad respectively, with as the second external contact.
In one embodiment, described encapsulation procedure comprises that more a plurality of the 3rd soldered balls of formation are on the bottom surface of circuit base plate with respect to load-bearing surface.
In one embodiment, form first perforate and the method for second perforate in packing colloid and comprise laser hole burning (laser ablation).
In one embodiment, described encapsulation procedure also comprises configuration one first outer member in first wafer module top, and engages externally contact of first outer member to the first.
In one embodiment, described encapsulation procedure also comprises configuration one second outer member in second wafer module top, and engages externally contact of second outer member to the second.
Based on above-mentioned, encapsulating structure of the present invention and encapsulation procedure have been integrated have different pin layouts a plurality of wafer modules of (being contact spacing difference), therefore can be compatible to the outer member of multiple different size simultaneously, and have good compatibility and extendibility.
For the above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate institute's accompanying drawing to be described in detail below.
Description of drawings
Fig. 1 is a kind of encapsulating structure of one embodiment of the invention;
Fig. 2 carries out the stack package structure that the stacked package processing procedure obtains afterwards for Fig. 1 encapsulating structure;
Fig. 3 is the making flow process of Fig. 1 and Fig. 2 encapsulating structure;
Fig. 4 is a kind of encapsulating structure of another embodiment of the present invention;
Fig. 5 carries out the stack package structure that the stacked package processing procedure obtains afterwards for Fig. 4 encapsulating structure;
Fig. 6 is the making flow process of Fig. 4 and Fig. 5 encapsulating structure;
Fig. 7 is a kind of encapsulating structure of further embodiment of this invention;
Fig. 8 carries out the stack package structure that the stacked package processing procedure obtains afterwards for Fig. 7 encapsulating structure;
Fig. 9 is the making flow process of Fig. 7 and Fig. 8 encapsulating structure.
Description of reference numerals
100,400,700: encapsulating structure; 110,410,710-circuit base plate;
112,412,712-load-bearing surface; 114,414,726-first weld pad;
116,436,736-second weld pad; 118,418,718-bottom surface;
119,419,719-the 3rd weld pad; 120,420, the 720-first wafer module;
122,422,722-first wafer; 124,424,724-first soldered ball;
132,432,732-second wafer; 134,434,734-second soldered ball;
140,440,740-packing colloid; 142,442,742-first perforate;
144,444,744-second perforate; 130,430, the 730-second wafer module;
160,460,760-the 3rd soldered ball; 170,470,770-first outer member;
172,472,772-weld pad; 180,480,780-second outer member;
182,482,782-weld pad; 432a, 722a, 732a-end face;
P1-first spacing; P2-second spacing;
152,154,452,454,752,754-lead.
Embodiment
The present invention has one first wafer module and the one second wafer module of the pin layout of difference with adjacent mode setting on the load-bearing surface of a circuit base plate.More specifically, for example have one first spacing between a plurality of first external contact of the first wafer module, and for example have one second spacing between a plurality of second external contact of the second wafer module, and first spacing is greater than second spacing.In addition, the packaging plastic cognition that is covered on the load-bearing surface exposes the first external contact and the second external contact, engages with outer member with the second wafer module for the first wafer module.
This encapsulating structure and encapsulation procedure can be applicable to system in package technology (SIP) or other technical fields that is suitable for.The first wafer module and the second wafer module for example are logic wafer modules, in order to engage with the memory chips module on upper strata.In addition, along with the specification difference of last layer elements, the pin of the first wafer module and the second wafer module can select to adopt fan-in (fan-in) or the design of fan-out (fan-out).Below the variation of described multiple design will be described for a plurality of embodiment.
Fig. 1 is a kind of encapsulating structure of one embodiment of the invention.As shown in Figure 1, encapsulating structure 100 comprises a circuit base plate 110, one first wafer module 120, one second wafer module 130 and a packing colloid 140.The first wafer module 120 of present embodiment and the second wafer module 130 all are the pin designs of adopting fan-out.Circuit base plate 110 has a load-bearing surface 112 and is positioned at a plurality of first weld pads 114 and a plurality of second weld pad 116 on the load-bearing surface 112.Have one first spacing P1 between per two adjacent first weld pads 114, and have one second spacing P2 between per two adjacent second weld pads 116, and the first spacing P1 is greater than the second spacing P2.
More specifically, the first wafer module 120 comprises one first wafer 122 and a plurality of first soldered ball 124, and wherein first wafer 122 is disposed on the load-bearing surface 112, and first weld pad 114 is positioned at first wafer, 122 peripheries.First soldered ball 124 is disposed on first weld pad 114.In the present embodiment, first wafer 122 is to adopt the routing juncture to be electrically connected to circuit base plate 110 by many leads 152, and the internal wiring (not illustrating) by circuit base plate 110 is electrically connected to first weld pad 114 again.Certainly, first wafer 122 also can adopt chip bonding or other possible modes are electrically connected to circuit base plate 110.In addition, first soldered ball 124 is disposed at respectively on first weld pad 114, and with as the aforesaid first external contact, and it has the first spacing P1 equally.
In addition, the second wafer module 130 comprises one second wafer 132 and a plurality of second soldered ball 134, and wherein second wafer 132 is disposed on the load-bearing surface 112, and second weld pad 116 is positioned at second wafer, 132 peripheries.Second soldered ball 134 is disposed on second weld pad 116.In the present embodiment, second wafer 132 is to adopt the routing juncture to be electrically connected to circuit base plate 110 by many leads 154, and the internal wiring (not illustrating) by circuit base plate 110 is electrically connected to second weld pad 116 again.Certainly, second wafer 132 also can adopt chip bonding or other possible modes are electrically connected to circuit base plate 110.In addition, second soldered ball 134 is disposed at respectively on second weld pad 116, and with as the aforesaid second external contact, and it has the second spacing P2 equally.
Refer again to Fig. 1, circuit base plate 110 also can have with respect to a bottom surface 118 of load-bearing surface 112 and be disposed at a plurality of the 3rd weld pads 119 on the bottom surface 118.May be configured with one the 3rd soldered ball 160 on each the 3rd weld pad 119, be connected to external circuit for encapsulating structure 100, for example printed circuit board (PCB) etc.
Fig. 2 carries out stacked package (Package on Package, POP) stack package structure that obtains after the processing procedure for Fig. 1 encapsulating structure 100.As shown in Figure 2, one first outer member 170 and one second outer member 180 are disposed at first wafer 122 and second wafer, 132 tops respectively.At this, first outer member 170 and second outer member 180 for example are respectively the encapsulation units of wafer stacking (chip stacked) kenel.First outer member 170 has a plurality of weld pads 172 corresponding to the first spacing P1, and engages with first soldered ball 124 by the soldered ball that may form in addition on weld pad 172 and the weld pad 172.Second outer member 180 has a plurality of weld pads 182 corresponding to the second spacing P2, and engages with second soldered ball 134 by the soldered ball that may form in addition on weld pad 182 and the weld pad 182.Therefore, present embodiment can pile up first outer member 170 and second outer member 180 adjacent and that have different pin layouts simultaneously on encapsulating structure 100, and good compatibility and extendibility can be provided.
Fig. 3 is the making flow process of Fig. 1 and Fig. 2 encapsulating structure, please be simultaneously with reference to Fig. 1-3.At first, shown in step 310, provide circuit base plate 110, wherein circuit base plate 110 has load-bearing surface 112 and is positioned at first weld pad 114 and second weld pad 116 on the load-bearing surface 112.
Then, shown in step 320, form first soldered ball 124 at first weld pad 114 respectively, with as the first external contact, and respectively at second weld pad, 116 formation, second soldered ball 134, with as the second external contact.
Then, shown in step 330, be adjacent to dispose first wafer 122 and second wafer 132 on load-bearing surface 112, and adopt routing to engage or other possible joining techniques engage first wafer 122 and second wafer 132 to circuit base plate 110.First weld pad 114 is positioned at first wafer, 122 peripheries and is electrically connected to first wafer 122, and second weld pad 116 is positioned at second wafer, 132 peripheries and is electrically connected to second wafer 132.
Carry out step 330 again though present embodiment carries out step 320 earlier, in fact, the order of step 320 and step 330 can be exchanged.
Then, shown in step 340, form packing colloid 140 on load-bearing surface 112, to cover first wafer 122 and second wafer 132.Afterwards, shown in step 350, form first perforate 142 and a plurality of second perforate 144 in packing colloid 140.First perforate 142 exposes first soldered ball 124 respectively, and second perforate 144 exposes second soldered ball 134 respectively.Present embodiment for example is laser hole burning or other are as chemical etching or the equiprobable method of electric paste etching in order to the method that forms first perforate 142 and second perforate 144.
In addition, present embodiment also can dispose first outer member 170 in first wafer, 122 tops shown in step 360, and engages first outer member, 170 to first soldered balls 124.In addition, dispose second outer member 180 in second wafer, 132 tops, and engage second outer member, 180 to second soldered balls 134, to obtain stack package structure as shown in Figure 2.
What deserves to be mentioned is that the described encapsulation procedure of present embodiment can adopt via cutting the resulting base board unit of array base palte and make.Perhaps, adopt the array base palte that does not cut as yet to make, and finish by the time after abovementioned steps 350 or the step 360, cut processing procedure again, with the encapsulating structure that obtains being illustrated as Fig. 1 or Fig. 2.In addition, after abovementioned steps 350 or step 360, can also form the 3rd soldered ball 160 at the 3rd weld pad 119 of circuit base plate 110 bottoms, and the 3rd soldered ball 160 is carried out steps such as reflow.Described step should be those skilled in the art to be understood, and gives unnecessary details no longer one by one herein.
Fig. 4 is a kind of encapsulating structure of another embodiment of the present invention.As shown in Figure 4, encapsulating structure 400 comprises a circuit base plate 410, one first wafer module 420, one second wafer module 430 and a packing colloid 440.The first wafer module 420 of present embodiment adopts the pin design of fan-out, and the second wafer module 430 adopts the pin design of fan-in.In other words, circuit base plate 410 has a load-bearing surface 412 and is positioned at a plurality of first weld pads 414 on the load-bearing surface 412.Has one first spacing P1 between per two adjacent first weld pads 414.
The first wafer module 420 comprises one first wafer 422 and a plurality of first soldered ball 424, and wherein first wafer 422 is disposed on the load-bearing surface 412, and first weld pad 414 is positioned at first wafer, 422 peripheries.First soldered ball 424 is disposed on first weld pad 414.In the present embodiment, first wafer 422 is to adopt the routing juncture to be electrically connected to circuit base plate 410 by many leads 452, and the internal wiring (not illustrating) by circuit base plate 410 is electrically connected to first weld pad 414 again.Certainly, first wafer 422 also can adopt chip bonding or other possible modes are electrically connected to circuit base plate 410.In addition, first soldered ball 424 is disposed at respectively on first weld pad 414, and it has the first spacing P1 equally.
In addition, the second wafer module 430 comprises one second wafer 432 and a plurality of second soldered ball 434, and wherein second wafer 432 is disposed on the load-bearing surface 412, and an end face 432a of second wafer 432 has a plurality of second weld pads 436.Have one second spacing P2 between per two adjacent second weld pads 436, and the first spacing P1 is greater than the second spacing P2.In the present embodiment, second wafer 432 is to adopt the routing juncture to be electrically connected to circuit base plate 410 by many leads 454.Certainly, second wafer 432 also can adopt chip bonding or other possible modes are electrically connected to circuit base plate 410.In addition, second soldered ball 434 is disposed at respectively on second weld pad 436, and it has the second spacing P2 equally.
Refer again to Fig. 4, circuit base plate 410 also can have with respect to a bottom surface 418 of load-bearing surface 412 and be disposed at a plurality of the 3rd weld pads 419 on the bottom surface 418.May be configured with one the 3rd soldered ball 460 on each the 3rd weld pad 419, be connected to external circuit for encapsulating structure 400, for example printed circuit board (PCB) etc.
Fig. 5 carries out stacked package (Package on Package, POP) stack package structure that obtains after the processing procedure for Fig. 4 encapsulating structure 400.As shown in Figure 5, one first outer member 470 and one second outer member 480 are disposed at first wafer 422 and second wafer, 432 tops respectively.At this, first outer member 470 and second outer member 480 for example are respectively the encapsulation units of wafer stacking (chip stacked) kenel.First outer member 470 has a plurality of weld pads 472 corresponding to the first spacing P1, and engages with first soldered ball 424 by the soldered ball that may form in addition on weld pad 472 and the weld pad 472.Second outer member 480 has a plurality of weld pads 482 corresponding to the second spacing P2, and engages with second soldered ball 434 by the soldered ball that may form in addition on weld pad 482 and the weld pad 482.Therefore, present embodiment can pile up first outer member 470 and second outer member 480 adjacent and that have different pin layouts simultaneously on encapsulating structure 400, and good compatibility and extendibility can be provided.
Fig. 6 is the making flow process of Fig. 4 and Fig. 5 encapsulating structure, please be simultaneously with reference to Fig. 4-6.At first, shown in step 610, provide circuit base plate 410, wherein circuit base plate 410 has load-bearing surface 412 and is positioned at first weld pad 414 on the load-bearing surface 412.
Then, shown in step 620, form first soldered ball 424 at first weld pad 414.Then, shown in step 630, be adjacent to dispose first wafer 422 and second wafer 432 on load-bearing surface 412, and adopt routing to engage or other possible joining techniques engage first wafer 422 and second wafer 432 to circuit base plate 410.First weld pad 414 is positioned at first wafer, 422 peripheries and is electrically connected to first wafer 422, and the end face 432a of second wafer 432 has a plurality of second weld pads 436.
Carry out step 630 again though present embodiment carries out step 620 earlier, in fact, the order of step 620 and step 630 can be exchanged.
Then, shown in step 640, form a plurality of second soldered balls 434 at second weld pad 436 respectively.And, shown in step 650, form packing colloid 440 on load-bearing surface 412, to cover first wafer 422 and second wafer 432.
Afterwards, shown in step 660, form first perforate 442 and a plurality of second perforate 444 in packing colloid 440.First perforate 442 exposes first soldered ball 424 respectively, and second perforate 444 exposes second soldered ball 434 respectively.Present embodiment for example is laser hole burning or other are as chemical etching or the equiprobable method of electric paste etching in order to the method that forms first perforate 442 and second perforate 444.
In addition, present embodiment also can dispose first outer member 470 in first wafer, 422 tops shown in step 670, and engages first outer member, 470 to first soldered balls 424.In addition, dispose second outer member 480 in second wafer, 432 tops, and engage second outer member, 480 to second soldered balls 434, to obtain stack package structure as shown in Figure 5.
What deserves to be mentioned is that the described encapsulation procedure of present embodiment can adopt via cutting the resulting base board unit of array base palte and make.Perhaps, adopt the array base palte that does not cut as yet to make, and finish by the time after abovementioned steps 660 or the step 670, cut processing procedure again, with the encapsulating structure that obtains being illustrated as Fig. 4 or Fig. 5.In addition, after abovementioned steps 660 or step 670, can also form the 3rd soldered ball 460 at the 3rd weld pad 419 of circuit base plate 410 bottoms, and the 3rd soldered ball 460 is carried out steps such as reflow.Described step should be those skilled in the art to be understood, and gives unnecessary details no longer one by one herein.
Based on the content of previous embodiment, another embodiment of the present invention also can change the pin design of the first wafer module being adopted fan-in into, and the second wafer module changes the pin design of adopting fan-out into.Perhaps, from another perspective, the encapsulating structure of this another embodiment and encapsulation procedure can be similar to Fig. 4-6 person of illustrating, and only significant difference is that the first spacing P1 can be less than the second spacing P2.
Fig. 7 is a kind of encapsulating structure of further embodiment of this invention.As shown in Figure 7, encapsulating structure 700 comprises a circuit base plate 710, one first wafer module 720, one second wafer module 730 and a packing colloid 740.The first wafer module 720 of present embodiment and the second wafer module 730 all adopt the pin design of fan-in.
The first wafer module 720 comprises one first wafer 722 and a plurality of first soldered ball 724, and wherein first wafer 722 is disposed on the load-bearing surface 712, and an end face 722a of first wafer 722 has a plurality of first weld pads 726.Has one first spacing P1 between per two adjacent first weld pads 726.In the present embodiment, first wafer 722 is to adopt the routing juncture to be electrically connected to circuit base plate 710 by many leads 752.Certainly, first wafer 722 also can adopt chip bonding or other possible modes are electrically connected to circuit base plate 710.In addition, first soldered ball 724 is disposed at respectively on first weld pad 726, and it has the first spacing P1 equally.
In addition, the second wafer module 730 comprises one second wafer 732 and a plurality of second soldered ball 734, and wherein second wafer 732 is disposed on the load-bearing surface 712, and an end face 732a of second wafer 732 has a plurality of second weld pads 736.Have one second spacing P2 between per two adjacent second weld pads 736, and the first spacing P1 is greater than the second spacing P2.In the present embodiment, second wafer 732 is to adopt the routing juncture to be electrically connected to circuit base plate 710 by many leads 754.Certainly, second wafer 732 also can adopt chip bonding or other possible modes are electrically connected to circuit base plate 710.In addition, second soldered ball 734 is disposed at respectively on second weld pad 736, and it has the second spacing P2 equally.
Refer again to Fig. 7, circuit base plate 710 also can have with respect to a bottom surface 718 of load-bearing surface 712 and be disposed at a plurality of the 3rd weld pads 719 on the bottom surface 718.May be configured with one the 3rd soldered ball 760 on each the 3rd weld pad 719, be connected to external circuit for encapsulating structure 700, for example printed circuit board (PCB) etc.
Fig. 8 carries out the stack package structure that the stacked package processing procedure obtains afterwards for Fig. 7 encapsulating structure 700.As shown in Figure 8, one first outer member 770 and one second outer member 780 are disposed at first wafer 722 and second wafer, 732 tops respectively.At this, first outer member 770 and second outer member 780 for example are respectively the encapsulation units of wafer stacking kenel.First outer member 770 has the pin layout corresponding to the first spacing P1, and engages with first soldered ball 724 by a plurality of weld pads 772.Second outer member 780 has the pin layout corresponding to the second spacing P2, and engages with second soldered ball 734 by a plurality of weld pads 782.Therefore, present embodiment can pile up first outer member 770 and second outer member 780 adjacent and that have different pin layouts simultaneously on encapsulating structure 700, and good compatibility and extendibility can be provided.
Fig. 9 is the making flow process of Fig. 7 and Fig. 8 encapsulating structure, please be simultaneously with reference to Fig. 7-9.At first, shown in step 910, provide circuit base plate 710, wherein circuit base plate 710 has load-bearing surface 712.
Then, shown in step 920, be adjacent to dispose first wafer 722 and second wafer 732 on load-bearing surface 712, and adopt routing to engage or other possible joining techniques engage first wafer 722 and second wafer 732 to circuit base plate 710.The end face 722a of first wafer 722 has a plurality of first weld pads 726, and the end face 732a of second wafer 732 has a plurality of second weld pads 736.
Then, shown in step 930, form a plurality of first soldered balls 724 at first weld pad 726 respectively, form a plurality of second soldered balls 734 at second weld pad 736 respectively.And, shown in step 940, form packing colloid 740 on load-bearing surface 712, to cover first wafer 722 and second wafer 732.
Afterwards, shown in step 950, form first perforate 742 and a plurality of second perforate 744 in packing colloid 740.First perforate 742 exposes first soldered ball 724 respectively, and second perforate 744 exposes second soldered ball 734 respectively.Present embodiment for example is laser hole burning or other are as chemical etching or the equiprobable method of electric paste etching in order to the method that forms first perforate 742 and second perforate 744.
In addition, present embodiment also can dispose first outer member 770 in first wafer, 722 tops shown in step 960, and engages first outer member, 770 to first soldered balls 724.In addition, dispose second outer member 780 in second wafer, 732 tops, and engage second outer member, 780 to second soldered balls 734, to obtain stack package structure as shown in Figure 8.
What deserves to be mentioned is that the described encapsulation procedure of present embodiment can adopt via cutting the resulting base board unit of array base palte and make.Perhaps, adopt the array base palte that does not cut as yet to make, and finish by the time after abovementioned steps 950 or the step 960, cut processing procedure again, with the encapsulating structure that obtains being illustrated as Fig. 7 or Fig. 8.In addition, after abovementioned steps 950 or step 960, can also form the 3rd soldered ball 760 at the 3rd weld pad 719 of circuit base plate 710 bottoms, and the 3rd soldered ball 760 is carried out steps such as reflow.Described step should be those skilled in the art to be understood, and gives unnecessary details no longer one by one herein.
Though aforementioned a plurality of embodiment is the wafer module of having integrated two kinds of different pin layouts is that example describes, the present invention does not limit the quantity of the wafer module kind that can integrate in the encapsulating structure, and it may be different along with the practical design demand.
In sum, encapsulating structure of the present invention and encapsulation procedure have been integrated have different pin layouts a plurality of wafer modules of (being contact spacing difference), and described wafer module disposed adjacent, with as the lower floor's encapsulation unit in the stacked package processing procedure.In other words, encapsulating structure of the present invention and encapsulation procedure have been realized adjacent chip configuration and stacked package technology simultaneously, and have this both advantage concurrently.Thus, lower floor's encapsulation unit can be compatible to the outer member of multiple different size simultaneously, for example the memory package unit of different size.Therefore, encapsulating structure and the encapsulation procedure of the present invention's proposition have good compatibility and extendibility.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (9)
1. encapsulating structure comprises:
One circuit base plate has a load-bearing surface;
One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:
One first wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of first weld pads and is disposed on this load-bearing surface of this first wafer periphery, and this first wafer is electrically connected to described first weld pad; And
A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;
One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:
One second wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of second weld pads and is disposed on this load-bearing surface of this second wafer periphery, and this second wafer is electrically connected to described second weld pad; And,
A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,
One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
2. encapsulating structure comprises:
One circuit base plate has a load-bearing surface;
One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:
One first wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of first weld pads and is disposed on this load-bearing surface of this first wafer periphery, and this first wafer is electrically connected to described first weld pad; And
A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;
One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:
One second wafer is disposed on this load-bearing surface, and an end face of this second wafer has a plurality of second weld pads; And,
A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,
One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
3. encapsulating structure comprises:
One circuit base plate has a load-bearing surface;
One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:
One first wafer is disposed on this load-bearing surface, and an end face of this first wafer has a plurality of first weld pads; And,
A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;
One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:
One second wafer is disposed on this load-bearing surface, and this circuit base plate has a plurality of second weld pads and is disposed on this load-bearing surface of this second wafer periphery, and this second wafer is electrically connected to described second weld pad; And,
A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,
One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
4. encapsulating structure comprises:
One circuit base plate has a load-bearing surface;
One first wafer module is disposed on this load-bearing surface, and this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and wherein this first wafer module comprises:
One first wafer is disposed on this load-bearing surface, and an end face of this first wafer has a plurality of first weld pads; And,
A plurality of first soldered balls are disposed at respectively on described first weld pad, with as the described first external contact;
One second wafer module, this first wafer module and this second wafer module are adjacent to be disposed on this load-bearing surface, this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, and wherein this second wafer module comprises:
One second wafer is disposed on this load-bearing surface, and an end face of this second wafer has a plurality of second weld pads; And,
A plurality of second soldered balls are disposed at respectively on described second weld pad, and with as the described second external contact, wherein this first spacing is greater than this second spacing; And,
One packing colloid, be disposed on this load-bearing surface, this packing colloid covers this first wafer module and this second wafer module, and this packing colloid has a plurality of first perforates and a plurality of second perforate, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
5. according to claim 1,2,3 or 4 described encapsulating structures, also comprise one first outer member, be disposed at this first wafer top and be engaged to the described first external contact.
6. encapsulation procedure comprises:
One circuit base plate is provided, and this circuit base plate has a load-bearing surface;
Be adjacent to dispose one first wafer module and one second wafer module on this load-bearing surface, this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, wherein this first spacing is not equal to this second spacing, this circuit base plate has a plurality of first weld pads and a plurality of second weld pad that is positioned on this load-bearing surface, and the method that is adjacent to dispose this first wafer module and this second wafer module comprises:
Form a plurality of first soldered balls at described first weld pad respectively, with as the described first external contact, and respectively at a plurality of second soldered balls of described second weld pad formation, with as the described second external contact; And,
Be adjacent to dispose one first wafer and one second wafer on this load-bearing surface, and engage this first wafer and this second wafer to this circuit base plate, described first weld pad is positioned on this load-bearing surface of this first wafer periphery and is electrically connected to this first wafer, and described second weld pad is positioned on this load-bearing surface of this second wafer periphery and is electrically connected to this second wafer;
Form a packing colloid on this load-bearing surface, to cover this first wafer module and this second wafer module; And,
Form a plurality of first perforates and a plurality of second perforate in this packing colloid, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
7. encapsulation procedure comprises:
One circuit base plate is provided, and this circuit base plate has a load-bearing surface;
Be adjacent to dispose one first wafer module and one second wafer module on this load-bearing surface, this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, wherein this first spacing is not equal to this second spacing, wherein this circuit base plate has a plurality of first weld pads that are positioned on this load-bearing surface, and the method that is adjacent to dispose this first wafer module and this second wafer module comprises:
Form a plurality of first soldered balls at described first weld pad respectively, with as the described first external contact;
Be adjacent to dispose one first wafer and one second wafer on this load-bearing surface, and engage this first wafer and this second wafer to this circuit base plate, described first weld pad is positioned on this load-bearing surface of this first wafer periphery and is electrically connected to this first wafer, and an end face of this second wafer has a plurality of second weld pads; And,
Form a plurality of second soldered balls at described second weld pad respectively, with as the described second external contact;
Form a packing colloid on this load-bearing surface, to cover this first wafer module and this second wafer module; And,
Form a plurality of first perforates and a plurality of second perforate in this packing colloid, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
8. encapsulation procedure comprises:
One circuit base plate is provided, and this circuit base plate has a load-bearing surface;
Be adjacent to dispose one first wafer module and one second wafer module on this load-bearing surface, this first wafer module has a plurality of first external contact, and has one first spacing between the per two adjacent first external contacts, and this second wafer module has a plurality of second external contact, and has one second spacing between the per two adjacent second external contacts, wherein this first spacing is not equal to this second spacing, and the method that wherein is adjacent to dispose this first wafer module and this second wafer module comprises:
Be adjacent to dispose one first wafer and one second wafer on this load-bearing surface, and engage this first wafer and this second wafer to this circuit base plate, one end face of this first wafer has a plurality of first weld pads, and an end face of this second wafer has a plurality of second weld pads;
Form a plurality of first soldered balls at described first weld pad respectively, with as the described first external contact; And,
Form a plurality of second soldered balls at described second weld pad respectively, with as the described second external contact;
Form a packing colloid on this load-bearing surface, to cover this first wafer module and this second wafer module; And,
Form a plurality of first perforates and a plurality of second perforate in this packing colloid, described first perforate exposes the described first external contact respectively, and described second perforate exposes the described second external contact respectively.
9. according to claim 6,7 or 8 described encapsulation procedures, wherein form a plurality of first perforates and the method for a plurality of second perforates in this packing colloid comprises the laser hole burning.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910174516.7A CN102034798B (en) | 2009-09-28 | 2009-09-28 | Packaging structure and packaging process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910174516.7A CN102034798B (en) | 2009-09-28 | 2009-09-28 | Packaging structure and packaging process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102034798A CN102034798A (en) | 2011-04-27 |
| CN102034798B true CN102034798B (en) | 2013-09-04 |
Family
ID=43887458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910174516.7A Active CN102034798B (en) | 2009-09-28 | 2009-09-28 | Packaging structure and packaging process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102034798B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102412611B1 (en) * | 2015-08-03 | 2022-06-23 | 삼성전자주식회사 | Printed Circuit Board(PCB), method for fabricating the PCB, and method for fabricating semiconductor package using the PCB |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134618A (en) * | 2005-11-14 | 2007-05-31 | Matsushita Electric Ind Co Ltd | Sheet-form electronic circuit module, and method of manufacturing same |
| CN101110398A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | Flip chip and its manufacturing method |
-
2009
- 2009-09-28 CN CN200910174516.7A patent/CN102034798B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007134618A (en) * | 2005-11-14 | 2007-05-31 | Matsushita Electric Ind Co Ltd | Sheet-form electronic circuit module, and method of manufacturing same |
| CN101110398A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | Flip chip and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102034798A (en) | 2011-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100821374B1 (en) | Semiconductor package | |
| US8022555B2 (en) | Semiconductor package and method of forming the same | |
| US8237271B2 (en) | Direct edge connection for multi-chip integrated circuits | |
| KR20120078390A (en) | Stack type semiconductor package and method of fabricating the same | |
| KR101145041B1 (en) | Semiconductor chip package, semiconductor module and fabrication method thereof | |
| US20040046239A1 (en) | Stacked package for integrated circuits | |
| TWI581396B (en) | 3d stacked package structure and method of manufacturing the same | |
| US20120146216A1 (en) | Semiconductor package and fabrication method thereof | |
| US7952205B2 (en) | Injection molded soldering process and arrangement for three-dimensional structures | |
| CN105097750A (en) | Package structure and method for fabricating the same | |
| JP2009506571A (en) | MICROELECTRONIC DEVICE HAVING INTERMEDIATE CONTACTS FOR CONNECTING TO INTERPOSER SUBSTRATE AND METHOD OF PACKAGING MICROELECTRONIC DEVICE WITH INTERMEDIATE CONTACTS RELATED TO THE SAME | |
| JP5394603B2 (en) | A multi-package module comprising a stacked package comprising a die and a mold body arranged asymmetrically. | |
| US20090179318A1 (en) | Multi-channel stackable semiconductor device and method for fabricating the same, and stacking substrate applied to the semiconductor device | |
| US6573461B2 (en) | Retaining ring interconnect used for 3-D stacking | |
| CN104685624B (en) | Recombinate wafer scale microelectronics Packaging | |
| US20030198034A1 (en) | Multi-chip module and fabricating method thereof | |
| JP2006253576A (en) | Semiconductor device and manufacturing method thereof | |
| US20070158805A1 (en) | BGA-scale stacks comprised of layers containing integrated circuit die and a method for making the same | |
| CN102034798B (en) | Packaging structure and packaging process | |
| US6573460B2 (en) | Post in ring interconnect using for 3-D stacking | |
| CN101211792A (en) | Semi-conductor package and its manufacture method and stacking structure | |
| KR102146131B1 (en) | Device of package stacking | |
| JP4639731B2 (en) | Mounting method of semiconductor device | |
| EP1724835A1 (en) | Electronic module comprising a layer containing integrated circuit die and a method for making the same | |
| CN103779298B (en) | Three-dimensional stack encapsulation structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |