CN102034432A - Light-emitting diode (LED) display screen signal cascade system - Google Patents
Light-emitting diode (LED) display screen signal cascade system Download PDFInfo
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Abstract
The invention discloses a light-emitting diode (LED) display screen signal cascade system. The LED display screen signal cascade system comprises a control unit and multistage LED display box bodies, wherein a screen body controller is arranged between the control unit and the multistage LED display box bodies; the screen body controller is connected with the first-stage LED display box body through a digital visual interface (DVI) line signal; the adjacent two-stage LED display box bodies are connected with each other through the DVI line signal; a receiving card for receiving a signal transmitted by the screen body controller is arranged in each LED display box body; and the screen body controller is connected with a DVI video source. The LED display screen signal cascade system effectively overcomes the bottleneck of insufficient transmission bandwidth of the traditional LED screen, solves the problem of difficulty in wiring in the prior art and reduces the transmission delay of the signal to be a value which can be nearly ignored so as to solve the problem of the transmission delay of one LED display box body cascaded to the next LED display box body and guarantee the display quality of multistage LED display screens.
Description
Technical field
The present invention relates to the LED display field, particularly a kind of LED display signal cascade system.
Background technology
The LED electronic display is the novel information display media that develops rapidly in the whole world in the later stage eighties, it is to utilize the lattice module of light emitting diode formation or the display media that pixel cell is formed, it integrates Control Technique of Microcomputer, video technique, photoelectron technology, microelectric technique, the communication technology, digital image processing techniques, is a kind of new high-tech product.It can show from the live image of computing machine, video recorder, video camera and TV, also can show from the still image in computing machine and the storer.It is with the reliability height, long service life, and characteristics such as adaptive capacity to environment is strong, the ratio of performance to price is high, use cost is low, shooting up in the short more than ten years is the main product of flat pannel display, has obtained large tracts of land in all trades and professions and has popularized and use.The LED electronic display system mainly is made up of computing machine, system plays management software, LED display body, control card (sending card and receiving card), panel box, network etc.
At present, most of LED display are based on Gigabit Ethernet technology, and promptly LED display is to carry out the signal transmission by gigabit Ethernet.The transmission card will be gathered the video data and the control information that come and be transferred to the receiving card that shields body by gigabit Ethernet; Between screen body receiving card (placing in the casing) and the screen body receiving card, promptly show casing and show that between the casing also be to carry out signal cascade by gigabit Ethernet, the feedback information of screen body is also by its passback, and the cable of transmission usefulness is to surpass the above netting twine of 5 classes, and its concrete structure as shown in Figure 1.Through the checking of long-term market, based on gigabit Ethernet the LED display cascade system exist many defectives.
At first, because based on the gigabit Ethernet system for transmitting, its signal transmission bandwidth is 1000Mbps, remove the data check position, the actual valid data position 800Mbps that transmits, coming undistorted transmission gray level with it is 1024 grades, and frame rate is the full color video image of 60Hz, and transmission of video resolution is the highest can only to be 1024*384.If wanting to realize resolution is 1920*1080, frame rate is 60Hz, and gray level is 256 grades a full-color LED display screen, and volume of transmitted data reaches 3900Mbps, and this just needs 5 networking lines, and 3 covers send card (every cover sends card two network delivery outlets).The wiring difficulty will be very big like this, makes constructional difficulties because many covers send the asynchronous of card transmission control clock, to cause image flicker when showing, shake easily simultaneously.
Secondly, utilize gigabit Ethernet to carry out the signal transmission, the transmission delay that is cascaded to next casing from a casing reaches 40-70ms.Along with the increase of cascade progression, transmission delay is also along with accumulation.When time-delay is accumulated to a certain degree, human eye will be awared asynchronous that picture shows, has influenced the effect that shows greatly.
The 3rd, in existing LED display system, because the transfer rate height of the speed ratio gigabit Ethernet of video data, institute's video data of wanting carries out frame buffer earlier after passing through and decoding, be organized into certain data layout then, send out through Ethernet again, arrive screen body receiving card at last, during through repeatedly data-switching, data recombination, more or less can cause the loss of signal or interference during this, bring uncertain factor to image displaying quality.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of signal transmission bandwidth height, the signal transmission delay is low and image display effect is good LED display signal cascade system are provided.
Technical scheme of the present invention is: a kind of LED display signal cascade system, comprise that control module and multi-stage LED show casing, be provided with the screen body controller between control module and the multi-stage LED demonstration casing, the screen body controller shows between the casing with first order LED and is connected by DVI (digital visual interface) line signal that the LED of adjacent two-stage shows between the casing and connects by DVI line signal; Each LED shows and is respectively equipped with the receiving card that is used for the signal that the receiving screen body controller sends in casing that the screen body controller also is connected with the DVI video source.
Described screen body controller inside comprises FPGA, DVI receiver, DVI transmitter, data cache module and control information module, DVI receiver, FPGA and DVI transmitter are connected successively, the DVI receiver is connected with the DVI video source by the DVI inlet module, the DVI transmitter shows by DVI outlet module and first order LED that casing is connected and carries out video Data Transmission that the DVI outlet module also is connected the transmission of carrying out control information and shielding the body feedback information with FPGA; FPGA is connected with the data cache module that temporal data is used; FPGA is connected with the control information module, and the control information module is connected with control module by USB interface.
In order to guarantee the stable and continuity of data, described data cache module comprises two SDRAM storeies that are arranged in parallel, and each SDRAM storer is connected with FPGA respectively, and the model of each SDRAM storer is MT48LC4M32B2P-7IT.
Described control information module is that USB changes the UART chip, adopts the USB of Silicon Labs company to change the UART chip, can realize the mutual biography of control information between control module and the screen body controller, and data rate reaches 12Mbps.
In the described screen body controller, it is the receiver of SiI1161CTU that the DVI receiver adopts the model of Silicon Image company, it is the transmitter of SiI164CTG64 that the DVI transmitter adopts the model of Silicon Image company, and the data bandwidth of DVI receiver and DVI transmitter can reach 4.95Gbps; The model of FPGA is Cyclone III FPGA-EP3C16F484C8N, and the LVDS serial communication technology is then adopted in communicating by letter between the receiving card in shielding body controller and LED showing casing, and it is directly to realize the LVDS communication interface by FPGA.At present, LVDS sort signal standard is all supported in the input and output of the FPGA device of companies such as Altera, Xilinx, Lattice, and the present invention adopts the Cyclone IIIFPGA-EP3C16F484C8N of Altera, satisfies the required logical resource requirement of this scheme.
The screen body controller is mainly used in realizes video data acquiring, Video processing, data transmission and control information transmitting-receiving etc.In the native system, the correlation technique of Video processing can comprise Gamma correction, colour temperature processing, real colour reproduction, contrast processing, white balance control or brightness regulation etc.Its principle is: with the transmission of LVDS data layout, then adopt DVI single-link mode transfer from the video data of DVI video source from the control information of control module; But in fact, can adopt dual link DVI cable and connector among the present invention, just transmitting video data has only been used a part of differential pair in the DVI cable, control information then utilizes its remaining differential pair to transmit, like this, the shared DVI interface of the transmission of video data and control information, reduced the quantity of connector and cable, simultaneously, video data, control information has all adopted low-voltage difference of vibration sub-signal to transmit, come compared with normal signal, their anti-common-mode noise interference performances are stronger, and electromagnetic radiation is littler, can not produce ring and signal and switch the spiking that brings, have good EMI characteristic, it is fast also to have a data reversal, advantage such as low in energy consumption.
Described receiving card inside comprises TMDS fan-out switch, DVI receiver, FPGA, SDRAM storer and connector, TMDS fan-out switch, DVI receiver are connected successively with FPGA, TMDS fan-out switch shows that with the LED of screen body controller or upper level casing is connected by the DVI inlet module, and TMDS fan-out switch shows that with the LED of next stage casing is connected by the DVI outlet module; FPGA is connected with the SDRAM storer that temporal data is used; FPGA is connected with the connector that is used to transmit the LED driving data; FPGA also is connected with the DVI outlet module with the DVI inlet module respectively.
In the described receiving card, it is the receiver of SiI1161CTU that the DVI receiver adopts the model of Silicon Image company, and it is the transmitter of SiI164CTG64 that the DVI transmitter adopts the model of Silicon Image company; It is the FPGA of Cyclone III FPGA-EP3C16F484C8N that FPGA adopts the model of altera corp; TMDS fan-out switch is to have 2 of cable driver to advance 4 and go out to change the fan-out switch, it is the conversion fan-out switch of MAX3845 that TMDS fan-out switch adopts the model of MAXIM company, MAX3845 is used for speed and distributes up to the DVI of 1.65Gbps or the multichannel monitor of HDMI signal, its input and output all are the TMDS signals of standard, meet all DVI and HDMI standard, simultaneously, adopt this fan-out switch, have only tens psecs (60ps) from the time-delay that is input to output, compared with the transmission delay that adopts Ethernet, this almost can ignore; The model of SDRAM storer is MT48LC4M32B2P-7IT.
Receiving card is mainly used in and realizes that video data receives, video data distribution, turntable driving that controller information receives to be shown with feedback and screen body etc.Its principle is: receiving card receives from shielding the video data that body controller or upper level receiving card send, the TMDS fan-out switch of receiving card is assigned as two-way to the DVI video data, one the tunnel is that the LED that exports to next stage shows casing, another road is as the video source of the corresponding levels, video data is handled accordingly by FPGA by DVI receiver decoding back, thus the at the corresponding levels required video data of intercepting; At last, FPGA goes the video data that is intercepted to the turntable driving LED display by certain data layout, finishes the demonstration that refreshes of LED display.
The present invention has following beneficial effect with respect to prior art:
Native system adopts the transmission medium of DVI as signal cascade between the LED demonstration casing, and its signal bandwidth reaches 4.95Gbps, efficiently solves the bottleneck of traditional LED screen transmission bandwidth deficiency; Simultaneously, when realizing differentiating LED display equally greatly, native system has an engineering wiring difficult problem still less, can effectively solve the problem of difficult wiring in the prior art.
Receiving card is provided with TMDS fan-out switch in the LED casing of native system, can make the transmission delay of signal be reduced to almost and can ignore; From the video acquisition to the demonstration, reduced the conversion of one stage signal form in the middle of this, promptly video is to the conversion of network data, and this has guaranteed the stability of signal transmission, reduced because of conversion of signals and brought unnecessary extraneous interference, and then improved the quality of display frame.Not only solved from a LED and shown that casing is cascaded to the transmission delay that next LED shows casing, has also guaranteed the display quality of multi-stage LED display screen.
Description of drawings
Fig. 1 is the principle schematic of existing LED display signal cascade system.
Fig. 2 is the principle schematic of this LED display signal cascade system.
Fig. 3 is the principle schematic of screen body controller in this LED display signal cascade system.
Fig. 4 is the principle schematic of receiving card in this LED display signal cascade system.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
Embodiment
A kind of LED display signal cascade of present embodiment system, as shown in Figure 2, comprise that control module and multi-stage LED show casing, be provided with the screen body controller between control module and the multi-stage LED demonstration casing, the screen body controller shows between the casing with first order LED and is connected by DVI (digital visual interface) line signal that the LED of adjacent two-stage shows between the casing and connects by DVI line signal; Each LED shows and is respectively equipped with the receiving card that is used for the signal that the receiving screen body controller sends in casing that the screen body controller also is connected with the DVI video source.
As shown in Figure 3, screen body controller inside comprises FPGA, DVI receiver, DVI transmitter, data cache module and control information module module, DVI receiver, FPGA and DVI transmitter are connected successively, the DVI receiver is connected with the DVI video source by the DVI inlet module, the DVI transmitter shows by DVI outlet module and first order LED that casing is connected and carries out video Data Transmission that the DVI outlet module also is connected the transmission of carrying out control information and shielding the body feedback information with FPGA; FPGA is connected with the data cache module that temporal data is used; FPGA is connected with the control information module, and the control information module is connected with control module by USB interface.
In order to guarantee the stable and continuity of data, data cache module comprises two SDRAM storeies that are arranged in parallel, and each SDRAM storer is connected with FPGA respectively, and the model of each SDRAM storer is MT48LC4M32B2P-7IT.
The control information module is that USB changes the UART chip, adopts the USB of Silicon Labs company to change the UART chip, can realize the mutual biography of control information between control module and the screen body controller, and data rate reaches 12Mbps.
In the screen body controller, it is the receiver of SiI1161CTU that the DVI receiver adopts the model of Silicon Image company, it is the transmitter of SiI164CTG64 that the DVI transmitter adopts the model of Silicon Image company, and the data bandwidth of DVI receiver and DVI transmitter can reach 4.95Gbps; The model of FPGA is Cyclone III FPGA-EP3C16F484C8N, and the LVDS serial communication technology is then adopted in communicating by letter between the receiving card in shielding body controller and LED showing casing, and it is directly to realize the LVDS communication interface by FPGA.At present, LVDS sort signal standard is all supported in the input and output of the FPGA device of companies such as Altera, Xilinx, Lattice, and the present invention adopts the Cyclone IIIFPGA-EP3C16F484C8N of Altera, satisfies the required logical resource requirement of this scheme.
The screen body controller is mainly used in realizes video data acquiring, Video processing, data transmission and control information transmitting-receiving etc.In the native system, the correlation technique of Video processing can comprise Gamma correction, colour temperature processing, real colour reproduction, contrast processing, white balance control or brightness regulation etc.Its principle is: with the transmission of LVDS data layout, then adopt DVI single-link mode transfer from the video data of DVI video source from the control information of control module; But in fact, can adopt dual link DVI cable and connector in the present embodiment, just transmitting video data has only been used a part of differential pair in the DVI cable, control information then utilizes its remaining differential pair to transmit, like this, the shared DVI interface of the transmission of video data and control information, reduced the quantity of connector and cable, simultaneously, video data, control information has all adopted low-voltage difference of vibration sub-signal to transmit, come compared with normal signal, their anti-common-mode noise interference performances are stronger, and electromagnetic radiation is littler, can not produce ring and signal and switch the spiking that brings, have good EMI characteristic, it is fast also to have a data reversal, advantage such as low in energy consumption.
As shown in Figure 4, receiving card inside comprises TMDS fan-out switch, DVI receiver, FPGA, SDRAM storer and connector, TMDS fan-out switch, DVI receiver are connected successively with FPGA, TMDS fan-out switch shows that with the LED of screen body controller or upper level casing is connected by the DVI inlet module, and TMDS fan-out switch shows that with the LED of next stage casing is connected by the DVI outlet module; FPGA is connected with the SDRAM storer that temporal data is used; FPGA is connected with the connector that is used to transmit the LED driving data; FPGA also is connected with the DVI outlet module with the DVI inlet module respectively.
In the receiving card, it is the receiver of SiI1161CTU that the DVI receiver adopts the model of Silicon Image company, and it is the transmitter of SiI164CTG64 that the DVI transmitter adopts the model of Silicon Image company; It is the FPGA of Cyclone III FPGA EP3C16F484C8N that FPGA adopts the model of altera corp; TMDS fan-out switch is to have 2 of cable driver to advance 4 and go out to change the fan-out switch, it is the conversion fan-out switch of MAX3845 that TMDS fan-out switch adopts the model of MAXIM company, MAX3845 is used for speed and distributes up to the DVI of 1.65Gbps or the multichannel monitor of HDMI signal, its input and output all are the TMDS signals of standard, meet all DVI and HDMI standard, simultaneously, adopt this fan-out switch, have only tens psecs (60ps) from the time-delay that is input to output, compared with the transmission delay that adopts Ethernet, this almost can ignore; The model of SDRAM storer is MT48LC4M32B2P-7IT.
Receiving card is mainly used in and realizes that video data receives, video data distribution, turntable driving that controller information receives to be shown with feedback and screen body etc.Its principle is: receiving card receives from shielding the video data that body controller or upper level receiving card send, the TMDS fan-out switch of receiving card is assigned as two-way to the DVI video data, one the tunnel is that the LED that exports to next stage shows casing, another road is as the video source of the corresponding levels, video data is handled accordingly by FPGA by DVI receiver decoding back, thus the at the corresponding levels required video data of intercepting; At last, FPGA goes the video data that is intercepted to the turntable driving LED display by certain data layout, finishes the demonstration that refreshes of LED display.
As mentioned above, just can realize the present invention preferably, the foregoing description is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention; Be that all equalizations of doing according to content of the present invention change and modification, all contained by claim of the present invention scope required for protection.
Claims (7)
1. LED display signal cascade system, comprise that control module and multi-stage LED show casing, it is characterized in that, be provided with the screen body controller between control module and the multi-stage LED demonstration casing, the screen body controller shows between the casing with first order LED and is connected by DVI line signal that the LED of adjacent two-stage shows between the casing and connects by DVI line signal; Each LED shows and is respectively equipped with the receiving card that is used for the signal that the receiving screen body controller sends in casing that the screen body controller also is connected with the DVI video source.
2. according to the described a kind of LED display signal cascade of claim 1 system, it is characterized in that, described screen body controller inside comprises FPGA, DVI receiver, DVI transmitter, data cache module and control information module, DVI receiver, FPGA and DVI transmitter are connected successively, the DVI receiver is connected with the DVI video source by the DVI inlet module, the DVI transmitter shows that with the first order LED casing is connected by the DVI outlet module, and the DVI outlet module also is connected with FPGA; FPGA is connected with the data cache module that temporal data is used; FPGA is connected with the control information module, and the control information module is connected with control module by USB interface.
3. according to the described a kind of LED display signal cascade of claim 2 system, it is characterized in that, described data cache module comprises two SDRAM storeies that are arranged in parallel, and each SDRAM storer is connected with FPGA respectively, and the model of each SDRAM storer is MT48LC4M32B2P-7IT.
4. according to the described a kind of LED display signal cascade of claim 2 system, it is characterized in that described control information module is that USB changes the UART chip.
5. according to the described a kind of LED display signal cascade of claim 2 system, it is characterized in that in the described screen body controller, the model of DVI receiver is SiI1161CTU, the model of DVI transmitter is SiI164CTG64, and the model of FPGA is Cyclone III FPGA-EP3C16F484C8N.
6. according to the described a kind of LED display signal cascade of claim 1 system, it is characterized in that, described receiving card inside comprises TMDS fan-out switch, DVI receiver, FPGA, SDRAM storer and connector, TMDS fan-out switch, DVI receiver are connected successively with FPGA, TMDS fan-out switch shows that with the LED of screen body controller or upper level casing is connected by the DVI inlet module, and TMDS fan-out switch shows that with the LED of next stage casing is connected by the DVI outlet module; FPGA is connected with the SDRAM storer that temporal data is used; FPGA is connected with the connector that is used to transmit the driving LED screen data; FPGA also is connected with the DVI outlet module with the DVI inlet module respectively.
7. according to the described a kind of LED display signal cascade of claim 6 system, it is characterized in that, in the described receiving card, the model of DVI receiver is SiI1161CTU, the model of DVI transmitter is SiI164CTG64, and the model of FPGA is Cyclone III FPGA EP3C16F484C8N, and TMDS fan-out switch is to have 2 of cable driver to advance 4 and go out to change the fan-out switch, the model of TMDS fan-out switch is MAX3845, and the model of SDRAM storer is MT48LC4M32B2P-7IT.
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Application publication date: 20110427 |