CN102033779B - Interrupt processing method and microcontroller - Google Patents
Interrupt processing method and microcontroller Download PDFInfo
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- CN102033779B CN102033779B CN 201010593737 CN201010593737A CN102033779B CN 102033779 B CN102033779 B CN 102033779B CN 201010593737 CN201010593737 CN 201010593737 CN 201010593737 A CN201010593737 A CN 201010593737A CN 102033779 B CN102033779 B CN 102033779B
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Abstract
The embodiment of the invention discloses an interrupt processing method and a microcontroller. The interrupt processing method comprises the following steps of: when a responded interrupt program is provided, executing a long call instruction which comprises seven clock cycles; pushing a value of a current process pointer down to a stack to protect a breaking point; in the second clock cycle and the fourth clock cycle of the long call instruction, transmitting a corresponding interrupt entry address to a program bus; and in the sixth clock cycle of the long call instruction, transmitting the interrupt entry address to the program pointer from the program bus so as to execute the next instruction from the interrupt entry address after the interrupt program is executed. The interrupt processing method is applicable for the interrupt processing of the microcontroller.
Description
Technical field
The present invention relates to the microcontroller technical field, particularly a kind of interruption processing method and microcontroller.
Background technology
At present, computing machine all has real-time processing capacity, relies on interrupt techniques, computing machine can be to external world at random event make timely processing.When CPU processes something, the outside a certain event request CPU that occurs goes rapidly to process, overflow etc. such as: the generation of the variation of a level, a pulse edge or timer counting, so CPU supspends current work, turn and process event.CPU handles after this event, returns original suspended place, continues original work.Such process is interrupted exactly.
It is a machine cycle that 8051 traditional microcontrollers adopt 12 clock period, a machine cycle is comprised of 6 states, each state was comprised of two clock period, and the execution time of an instruction is 1 to 2 machine cycle, and the time of carrying out an instruction is 12 or 24 clock period.CPU is at the S5P2 of each machine cycle state, each interrupt source is sampled and arranges corresponding interrupt identification, at the S6P2 of each machine cycle state, the interrupt identification of sequential query interrupt source according to priority, and the interrupt source of processing request, and the S1 state in the next machine cycle responds five-star interrupt request.
Usually; single-chip microcomputer is in case the response interruption; according to corresponding interrupt priority level; by long call instruction LCALL of hardware implement; the current value of PC (Program Counter, program pointer) is pressed into storehouse, with the protection breakpoint; again PC is sent in the entry address of corresponding interrupt service routine, 8051 microcontrollers then begin from the interrupt service routine porch to carry out.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art:
The long call instruction LCALL of 8051 traditional microcontrollers needs 24 clock period, and instruction operation speed is slow, and the time that response is interrupted is longer, and the efficient of interrupting processing is not high.
Summary of the invention
Embodiments of the invention provide a kind of interruption processing method and microcontroller, can reduce the time that response is interrupted, and improve the efficient of interrupting processing.
The technical scheme that the embodiment of the invention adopts is:
A kind of interruption processing method comprises:
When having the interrupt routine that responds, executive chairman's call instruction, wherein, described long call instruction comprises 7 clock period;
The value that program pointer is current is pressed into storehouse, with the protection breakpoint;
In the 2nd and the 4th clock period of described long call instruction, will interrupt accordingly the entry address and send into program bus;
In the second-to-last clock period of described long call instruction, program pointer is sent into from program bus in described interruption entry address, so that after described interrupt routine executes, carry out next bar instruction from described interruption entry address.
A kind of microcontroller comprises:
Execution module is used for when having the interrupt routine that responds, executive chairman's call instruction, and wherein, described long call instruction comprises 7 clock period;
Be pressed into module, be used for the value that program pointer is current and be pressed into storehouse, with the protection breakpoint;
The first processing module was used in the 2nd and the 4th clock period of described long call instruction, will interrupt accordingly the entry address and send into program bus;
The second processing module is used in the second-to-last clock period of described long call instruction program pointer being sent into from program bus in described interruption entry address, so that after described interrupt routine executes, from next the bar instruction of execution of described interruption entry address.
The interruption processing method that the embodiment of the invention provides and microcontroller; when having the interrupt routine that responds; execution comprises the long call instruction of 7 clock period; the value that program pointer is current is pressed into storehouse; with the protection breakpoint; in the 2nd and the 4th clock period of described long call instruction; to interrupt accordingly the entry address and send into program bus; in the second-to-last clock period of described long call instruction; program pointer is sent into from program bus in described interruption entry address; so that after described interrupt routine executes, carry out next bar instruction from described interruption entry address.Compared with prior art, long call instruction only needs 7 clock period, and the instruction operation speed can reduce the time that response is interrupted, and improves the efficient of interrupting processing.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The interruption processing method process flow diagram that Fig. 1 provides for the embodiment of the invention one;
The microcontroller architecture synoptic diagram that Fig. 2 provides for the embodiment of the invention two.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making all other embodiment that obtain under the creative work prerequisite.
For the advantage that makes technical solution of the present invention is clearer, below in conjunction with drawings and Examples the present invention is elaborated.
Embodiment one
Present embodiment provides a kind of interruption processing method, in the present embodiment, describes as an example of 8051 microcontrollers example.
As shown in Figure 1, described method comprises:
101, carry out interrupt arbitrage in last clock period of every instruction, judge whether to block interrupt response, if do not block interrupt response, then enter the processing of interrupt response.
Particularly, the interrupt timing module is in last clock period that every instruction is carried out, namely during SL=1, carry out interrupt arbitrage, when finding to respond a certain interruption, interrupt flag bit is drawn high, cause in next clock period interrupt request singal to uprise that expression enters the processing of interrupt response.Owing to read next bar instruction before the SL state carries out interrupt arbitrage, next the bar instruction that therefore will read first executes, at the S2L state of next bar instruction of reading, by interrupt request singal mask program storer fetching signal.
Wherein, described interrupt arbitrage specifically can comprise:
Judge whether next bar instruction of getting into is RETI (interrupt return instruction), the instruction of perhaps IE (interrupting allowing register), IP (interrupt priority level register) being read and write, if present instruction is RETI, the instruction of perhaps IE, IP being read and write then can be blocked interrupt response.
Wherein, last state every instruction, get into next bar instruction, if the instruction of getting into is the RETI instruction, then the Reti_decode signal is 1, when in the end a state carries out interrupt arbitrage, Reti_decode 1 will stop interrupt request singal intack to uprise, thereby can not respond interruption.
When IE, IP register selected signal ie_sel or ip_sel were effective, the ieip that will reset was 1, otherwise at the S1 state of every instruction of rising edge of clkb ieip was set to 0.Ieip represents when being high level that present instruction is the instruction to IE, IP register manipulation.When ieip was effective, shielding interrupt response signal intack dragged down it, thereby can not respond interruption.
Further, described interrupt arbitrage can also comprise:
If find to respond the current interruption that monitors, just the confirm signal is put 1, indicate to enter the interrupt response operation;
When processing at the same level the interruption, process according to the natural order of interrupt priority level;
When having high level interrupt responding, the interruption of priority processing high priority;
When interrupt nesting occurring, that is to say, when in commission the interruption of high priority occurring in the disconnected process, preferentially carry out the interruption of high priority, until executing the breakpoint succession that returns again original interrupt routine, carries out high priority.
102, after 8051 microcontrollers receive interrupt request singal intack, in last clock period of the instruction of current execution, it is invalid to be set to for the control signal of the data writing program bus of control program storer, to suspend the data writing program bus in the program storage.
103, put into the operational code of long call instruction LCALL at program bus, because this moment is read opcode from program storage not, therefore program pointer can not change, effectively and in the second-to-last clock period of present instruction suspend the change that PC (program pointer) is worth at interrupt request singal intack, interrupt the entry address until executive chairman's call instruction LCALL jumps to program pointer.
Wherein, long call instruction LCALL comprises 7 clock period, residing 7 clock period when adopting S1, S2, S3, S4, S5, S2L, SL to represent respectively this long call instruction LCALL execution here.
104, executive chairman's call instruction LCALL, the value that program pointer is current is pressed into storehouse, with the protection breakpoint.
105, in the 2nd and the 4th clock period of long call instruction LCALL, the entry address of interrupt routine is placed on the program bus.
106, in second-to-last clock period of described long call instruction LCALL, program pointer is sent into from program bus in described interruption entry address, so that after described interrupt routine executed, 8051 microcontrollers were then from next the bar instruction of execution of described interruption entry address.
The interruption processing method that the embodiment of the invention provides; when having the interrupt routine that responds; execution comprises the long call instruction of 7 clock period; the value that program pointer is current is pressed into storehouse; with the protection breakpoint; in the 2nd and the 4th clock period of described long call instruction; to interrupt accordingly the entry address and send into program bus; in the second-to-last clock period of described long call instruction; program pointer is sent into from program bus in described interruption entry address; so that after described interrupt routine executes, carry out next bar instruction from described interruption entry address.Compared with prior art, long call instruction only needs 7 clock period, and the instruction operation speed can reduce the time that response is interrupted, and improves the efficient of interrupting processing.
Embodiment two
Present embodiment provides a kind of microcontroller, and as shown in Figure 2, described microcontroller comprises:
Be pressed into module 202, be used for the value that program pointer is current and be pressed into storehouse, with the protection breakpoint;
The first processing module 203 was used in the 2nd and the 4th clock period of described long call instruction, will interrupt accordingly the entry address and send into program bus;
The second processing module 204 is used in the second-to-last clock period of described long call instruction program pointer being sent into from program bus in described interruption entry address, so that after described interrupt routine executes, from next the bar instruction of execution of described interruption entry address.
Further, as shown in Figure 3, described microcontroller can also comprise:
Put into module 206, be used on program bus, putting into the operational code of described long call instruction.
Further, as shown in Figure 3, described microcontroller can also comprise:
If do not block interrupt response, then enter the processing of interrupt response.
Further, described interrupt arbitrage module 207, concrete for judging whether next bar instruction of getting into is interrupt return instruction RETI, the perhaps instruction to interrupting allowing register IE, interrupt priority level register IP to read and write;
If present instruction is RETI, the instruction of perhaps IE, IP being read and write then can be blocked interrupt response.
Further, described interrupt arbitrage module 207, concrete being used for processes according to the natural order of interrupt priority level when having interruption at the same level responding; When having high level interrupt responding, the interruption of priority processing high priority; When the interruption of high priority occurring in the in commission disconnected process, carry out first the interruption of high priority, and then return the breakpoint succession execution of former interrupt routine.
The microcontroller that the embodiment of the invention provides; when having the interrupt routine that responds; execution comprises the long call instruction of 7 clock period; the value that program pointer is current is pressed into storehouse; with the protection breakpoint; in the 2nd and the 4th clock period of described long call instruction; to interrupt accordingly the entry address and send into program bus; in the second-to-last clock period of described long call instruction; program pointer is sent into from program bus in described interruption entry address; so that after described interrupt routine executes, carry out next bar instruction from described interruption entry address.Compared with prior art, long call instruction only needs 7 clock period, and the instruction operation speed can reduce the time that response is interrupted, and improves the efficient of interrupting processing.
The above-mentioned embodiment of the method that provides can be provided the microcontroller that the embodiment of the invention provides.The interruption processing method that the embodiment of the invention provides and microcontroller go for the interruption of 8051 microcontrollers and process, but are not limited only to this.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, to come the relevant hardware of instruction to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process such as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or store-memory body (RandomAccess Memory, RAM) etc. at random.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (10)
1. an interruption processing method is characterized in that, comprising:
When having the interrupt routine that responds, executive chairman's call instruction, wherein, described long call instruction comprises 7 clock period;
The value that program pointer is current is pressed into storehouse, with the protection breakpoint;
In the 2nd and the 4th clock period of described long call instruction, will interrupt accordingly the entry address and send into program bus;
In the second-to-last clock period of described long call instruction, program pointer is sent into from program bus in described interruption entry address, so that after described interrupt routine executes, carry out next bar instruction from described interruption entry address.
2. method according to claim 1 is characterized in that, also comprises:
After receiving interrupt request singal, in last clock period of present instruction, it is invalid to be set to for the control signal of the data writing program bus of control program storer, to suspend the data writing program bus in the program storage;
Put into the operational code of described long call instruction on the program bus.
3. method according to claim 1 and 2 is characterized in that, also comprises:
In last clock period of present instruction, carry out interrupt arbitrage, judge whether to block interrupt response;
If do not block interrupt response, then enter the processing of interrupt response.
4. method according to claim 3 is characterized in that, the described interrupt arbitrage of carrying out judges whether to block interrupt response and comprises:
Judge whether next bar instruction of getting into is interrupt return instruction RETI, perhaps the instruction to interrupting allowing register IE, interrupt priority level register IP to read and write;
If present instruction is interrupt return instruction RETI, perhaps the instruction to interrupting allowing register IE, interrupt priority level register IP to read and write then can be blocked interrupt response.
5. method according to claim 3 is characterized in that, the described interrupt arbitrage of carrying out judges whether to block interrupt response and comprises:
When having interruption at the same level responding, process according to the natural order of interrupt priority level;
When having high level interrupt responding, the interruption of priority processing high priority;
When the interruption of high priority occurring in the in commission disconnected process, carry out first the interruption of high priority, and then return the breakpoint succession execution of former interrupt routine.
6. an interrupt processing device is characterized in that, comprising:
Execution module is used for when having the interrupt routine that responds, executive chairman's call instruction, and wherein, described long call instruction comprises 7 clock period;
Be pressed into module, be used for the value that program pointer is current and be pressed into storehouse, with the protection breakpoint;
The first processing module was used in the 2nd and the 4th clock period of described long call instruction, will interrupt accordingly the entry address and send into program bus;
The second processing module is used in the second-to-last clock period of described long call instruction program pointer being sent into from program bus in described interruption entry address, so that after described interrupt routine executes, from next the bar instruction of execution of described interruption entry address.
7. interrupt processing device according to claim 6 is characterized in that, also comprises:
Module is set, be used for after receiving interrupt request singal, in last clock period of present instruction, it is invalid to be set to for the control signal of the data writing program bus of control program storer, to suspend the data writing program bus in the program storage;
Put into module, be used on program bus, putting into the operational code of described long call instruction.
8. it is characterized in that: also comprise according to claim 6 or 7 described interrupt processing devices:
The interrupt arbitrage module was used in last clock period of present instruction, carried out interrupt arbitrage, judged whether to block interrupt response;
If do not block interrupt response, then enter the processing of interrupt response.
9. interrupt processing device according to claim 8 is characterized in that,
Described interrupt arbitrage module, concrete for judging whether next bar instruction of getting into is interrupt return instruction RETI, the perhaps instruction to interrupting allowing register IE, interrupt priority level register IP to read and write;
If present instruction is interrupt return instruction RETI, perhaps the instruction to interrupting allowing register IE, interrupt priority level register IP to read and write then can be blocked interrupt response.
10. interrupt processing device according to claim 8 is characterized in that:
Described interrupt arbitrage module, concrete being used for processes according to the natural order of interrupt priority level when having interruption at the same level responding; When having high level interrupt responding, the interruption of priority processing high priority; When the interruption of high priority occurring in the in commission disconnected process, carry out first the interruption of high priority, and then return the breakpoint succession execution of former interrupt routine.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1490722A (en) * | 2003-09-19 | 2004-04-21 | 清华大学 | Graded task switching method based on PowerPC processor structure |
| CN1783020A (en) * | 2005-09-12 | 2006-06-07 | 浙江大学 | Interrupt managing method for embedded operation system based on PowerPC system structure |
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| US20060218550A1 (en) * | 2005-03-23 | 2006-09-28 | Texas Instruments Inc. | Virtual machine for timing-critical tasks on microprocessors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490722A (en) * | 2003-09-19 | 2004-04-21 | 清华大学 | Graded task switching method based on PowerPC processor structure |
| CN1783020A (en) * | 2005-09-12 | 2006-06-07 | 浙江大学 | Interrupt managing method for embedded operation system based on PowerPC system structure |
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Effective date of registration: 20160728 Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Qingdao Hisense Electric Co., Ltd. Address before: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee before: Qingdao Hisense Xinxin Technology Co., Ltd. |
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Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Hisense Video Technology Co.,Ltd. Address before: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee before: HISENSE ELECTRIC Co.,Ltd. |