CN1783020A - Interrupt managing method for embedded operation system based on PowerPC system structure - Google Patents
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Abstract
The interrupt management method for embedded operation system based on PowerPC system structure includes the following steps: dividing interrupts into two classes of system interrupt and user interrupt and dividing user interrupt service programs into class-I interrupt service program and class-II interrupt service program; first hardware responding the user interrupt; then, maintaining the context, stack switching and interrupt nesting for resuming the interrupted task after interrupt treatment; finding out and calling corresponding interrupt service program from the user interrupt vector list via the interrupt source; and maintaining the interrupt nesting and stack switching, restoring the context for the treater to resume the interrupted task. The present invention has the advantages of raised interrupt executing efficiency, raised interrupt utilizing efficiency, convenient interrupt control and use, raised user stack size controllability and predicting property.
Description
Technical field
The present invention relates to the embedded real-time operating system technology, mainly is the interrupt management method that realizes a kind of embedded OS based on the PowerPC architecture.
Background technology
Interruption is the requisite a kind of mechanism of operating system, interrupts being used for the generation that notification processor has certain incident.In a single day interrupt being identified, processor will be preserved the data (such as numerical value in the register) of reflection current task state, these data are called as " context "; Processor will be carried out the incident that special interrupt service routine responds the initiation interruption after preserving context; Recover context at last, continue to carry out interrupted task.Interrupt mechanism is used to handle the more inside and outside accident that can not expect.Because it can not expect, the robustness of interrupt mechanism just seems particularly important for the especially real-time embedded OS of operating system so.It is directly connected to the stability of operating system and the efficient of operation.Because interrupt mechanism and operating system combine, interrupt mechanism must guarantee the normal operation of task so, and this just need interrupt taking place and interrupt to carry out when withdrawing from work initial and that deal with problems arising from an accident.
Present more popular micro-kernel embedded operating system; such as uC/OS etc.; the encapsulation and the management of interruption are not provided; the user needs the interface, scene protection, on-the-spot recovery of own definition interrupt service routine and with the interrupt source binding etc.; this writes interrupt service routine to the user and brings very big inconvenience; must increase user's development difficulty, prolong the construction cycle, reduced the stability of system.
Interrupt management is different from other mechanism such as task management of operating system, and it and hardware architecture correlativity are big.Therefore consider from the index of stability, execution efficient and this three big embedded system of system overhead that at different architectures, different processor familys needs to realize specific interrupt management method.
Summary of the invention
The invention solves the defective that general interrupt management exists, and a kind of interrupt management method of the embedded OS based on the PowerPC architecture is provided.
The interrupt management method of this embedded OS based on the PowerPC architecture, performing step is as follows:
1), interruption is divided into system break and the user is interrupted two classes, system break is managed concentratedly by system, handles the interruption that is caused by system, such as because that abnormal operation causes is unusual, restart (Reset) interrupts; The external interrupt that user's Interrupt Process user can use is such as serial ports interruption, analog to digital conversion interruption etc.System break is meant all interruptions except external interrupt and maskable external breakpoint.System break will enter unified system break service routine inlet when taking place, only preserve a small amount of registers necessary data before the in commission disconnected service routine.The user interrupts being meant external interrupt and maskable external breakpoint, external interrupt is triggered by external pin, the maskable external breakpoint interrupts being produced by other modules in the sheet, hardware system is not distinguished concrete user and is interrupted, and use unified user interrupt service routine inlet, come dispatched users to interrupt by safeguarding user's interrupt vector table.The present invention is respectively system break and the user interrupts providing access encapsulation, and all system break are unified to adopt a system break to enter the mouth, and all users are interrupted unification and adopted a user to interrupt respectively interruption being operated in these two inlets for entering the mouth.
2), user interrupt service routine is divided into a class interrupt service routine and two class interrupt service routines, do not allow the service of user's calling system in the one class interrupt service routine, do not influence the operation of task scheduling in this class interrupt service routine, interrupt service routine finishes the back system will get back to the place continuation operation of interrupting generation; Allow the calling system service in the two class interrupt service routines, be performed to guarantee the highest task of priority when interrupting to cause task scheduling when service routine finishes;
3), when the user interrupts taking place, at first interrupt by Hardware Response Delay; Preserve then that context, storehouse switch, maintenance breaks is nested, to guarantee that interrupted task can continue to move Interrupt Process is finished after; Interrupt taking place the back and find and call corresponding interrupt service routine by interrupt source in user's interrupt vector table, then nested, the storehouse switching of maintenance breaks once more recovers context at last, and processor continues the original interrupted task of operation; Maintenance breaks is nested to be meant in the process of handling interrupt, and the interruption of shielding low priority prevents the execution of interrupt service routine of the interruption interfere with high priority of low priority; After user's interrupt routine returns, recover conductively-closed again and interrupt.Management interrupt is nested on software layer, the stack space of multistage interrupt nesting using system is preserved context, and the context of task will be stored in the stack space of task, need carry out the switching of system stack and task stack when processor switches between nested interrupt and user task.
4), for two class interrupt service routines, even when when task layer is returned in interruption, carrying out task scheduling to guarantee the task energy operation of high priority; Preserve and when recovering context, interrupt only preserving and recovering the value of volatile register for a class, and interrupt also needing to preserve and recover the value of non volatile register for two classes.
The present invention has following advantage:
1. the present invention will be interrupted classifying with interrupt service routine.Interruption is divided into system break and the user is interrupted, and dissimilar interrupt service routines is used different treatment mechanisms, thereby has improved the execution efficient of interrupting.
2. in the present invention, support the interrupt nesting based on the PowerPC system, maximum can be supported 16 layers nested to have improved the utilization ratio of interrupting, and has made things convenient for control and the use interrupted.
3. the invention provides unified interrupt management interface, the user can be by calling the attribute that these interfaces come the configure interrupt service routine.The present invention has hidden complicated Interrupt Process details, has improved the user develops interrupt service routine in the PowerPC architecture efficient and convenience.
4. drawing-in system storehouse of the present invention is handled nested interrupt, has effectively prevented the storehouse overflow exception that causes owing to nested interrupt, has improved the controllability and the predictability of user stack size, has saved internal memory cost.
This interrupt mechanism through strict test, proves that this mechanism has good performance and stability on the MPC555 of PowerPC architecture hardware platform.
Description of drawings
System break processing flow chart among Fig. 1 the present invention;
A class user Interrupt Process process flow diagram among Fig. 2 the present invention;
Two class user Interrupt Process process flow diagrams among Fig. 3 the present invention.
Embodiment
The invention will be described further below in conjunction with the MPC555 platform of PowerPC architecture:
The present invention is divided into two classes with whole interrupt system, and a class is a system break, and a class is that the user is interrupted, and this two class interrupts having formed jointly the interruption system of PowerPC architecture.
● system break
In the PowerPC architecture, system break is meant all interruptions except external interrupt and maskable external breakpoint.System break will enter unified system break service routine inlet when taking place, only preserve a small amount of registers necessary data before the in commission disconnected service routine.For example the floating number aborted just belongs to system break on the MPC555 hardware platform, and as shown in Figure 1, the processing procedure when this interrupts taking place is as follows:
1. interrupt taking place, hardware finds unified system break inlet from interrupt vector table, begin to carry out following steps from this inlet.
2. preserve the relevant register data, these registers comprise universal integer type register GPR0-GPR13, LR, CR, MSR, SRR0, SRR1, XER, CTR on the MPC555 hardware platform.
3. obtain interrupt source from particular register, according to interrupt source calling system interrupt service routine, what call in this example is floating number pathological system interrupt service routine.
4. recover the register data of preservation in step 2.
5. interrupt returning, therefrom working procedure is continued in the living place of broken hair.
● the user is interrupted
In the PowerPC architecture, the user interrupts being meant external interrupt and maskable external breakpoint.External interrupt is triggered by external pin, and the maskable external breakpoint interrupts being produced by other modules in the sheet.In the present invention, hardware system is not distinguished concrete user and is interrupted, and uses unified user interrupt service routine inlet, and the present invention comes dispatched users to interrupt by safeguarding user's interrupt vector table.User interrupt service routine is divided into a class user interrupt service routine and two class interrupt service routines.
For example in the example on the MPC555 of PowerPC architecture platform, the user has been a serial ports interrupt configuration one section one class interrupt service routine, when this serial ports interrupts taking place, interrupt service routine is responsible for carrying out some simple data processing, as shown in Figure 2, this Interrupt Process process is as follows:
6. interrupt taking place, hardware finds unified user to interrupt inlet from interrupt vector table, begins to carry out following steps from this inlet.
7. preserve return address and a spot of register that will in following steps, use, such as general-purpose register GPR2～GPR3.
8. need switch to system stack from task stack if enter interruption, not switch if nested interrupt does not then need to carry out storehouse from task.
9. the low interruption of this interrupt priority level of shielding ratio.
10. acquisition interrupt source, user interrupt service routine and the execution of finding this serial ports to interrupt from user's interrupt vector table according to this value then.
11. if the task of returning need be switched back task stack from system stack from interrupt, if withdraw from from nested interrupt then do not need to carry out the storehouse switching.
12. recover the register of preservation in step 2.
13. from this interruption, withdraw from, continue to carry out interrupted program.
In same example, the user has been an analog to digital conversion interrupt configuration one two class interrupt service routine, when this interrupts taking place, interrupt service routine can activate an analog-to-digital task of processing with higher priority, to guarantee after interruption is withdrawed from, even this task energy is moved, this Interrupt Process process is as follows:
1. interrupt taking place, hardware finds unified user to interrupt inlet from interrupt vector table, begins to carry out following steps from this inlet.
2. preserve return address and a spot of register that will in following steps, use, such as general-purpose register GPR2～GPR3.
3. need switch to system stack from task stack if enter interruption, not switch if nested interrupt does not then need to carry out storehouse from task.
4. preservation non volatile register, non volatile register comprises universal integer type register GPR14-GPR31, CR, XER, CTR on the MPC555 hardware platform, so preserve when a class is interrupted and recover the more value of multiregister than handling when handling two classes and interrupting.
5. the low interruption of this interrupt priority level of shielding ratio.
6. acquisition interrupt source, from user interrupt service routine and execution that user's interrupt vector table finds this serial ports to interrupt, this program has activated the task of a high priority.
7. if the task of returning need be switched back task stack and recover the value of non volatile register from system stack from interrupt, if withdraw from from nested interrupt then do not need to carry out the storehouse switching.
8. all registers of preserving of recovering step 2 and step 4.
9. from this interruption, withdraw from,, then continue the outage service routine if from nested interrupt, withdraw from; If return task layer,,, move this high-priority task rather than continue to carry out interrupted program so cause scheduler program because the task of a high priority is activated.
Claims (7)
1, a kind of interrupt management method of the embedded OS based on the PowerPC architecture, it is characterized in that: performing step is as follows:
1), interruption is divided into system break and the user is interrupted two classes, system break is managed concentratedly by system, handles the interruption that is caused by system; The external interrupt that user's Interrupt Process user can use;
2), user interrupt service routine is divided into a class interrupt service routine and two class interrupt service routines, do not allow the service of user's calling system in the one class interrupt service routine, do not influence the operation of task scheduling in this class interrupt service routine, interrupt service routine finishes the back system will get back to the place continuation operation of interrupting generation; Allow the calling system service in the two class interrupt service routines, be performed to guarantee the highest task of priority when interrupting to cause task scheduling when service routine finishes;
3), when the user interrupts taking place, at first interrupt by Hardware Response Delay; Preserve then that context, storehouse switch, maintenance breaks is nested, to guarantee that interrupted task can continue to move Interrupt Process is finished after; Interrupt taking place the back and find and call corresponding interrupt service routine by interrupt source in user's interrupt vector table, then nested, the storehouse switching of maintenance breaks once more recovers context at last, and processor continues the original interrupted task of operation;
4), for two class interrupt service routines, even when when task layer is returned in interruption, carrying out task scheduling to guarantee the task energy operation of high priority; Preserve and when recovering context, interrupt only preserving and the value of the volatile register that recovers in this project, to use, and interrupt also needing to preserve and recover the value of non volatile register for two classes for a class.
2, the interrupt management method of the embedded OS based on the PowerPC architecture according to claim 1, it is characterized in that: maintenance breaks is nested to be meant in the process of handling interrupt, the interruption of shielding low priority prevents the execution of interrupt service routine of the interruption interfere with high priority of low priority; After user's interrupt routine returns, recover conductively-closed again and interrupt.
3, the interrupt management method of the embedded OS based on the PowerPC architecture according to claim 1, it is characterized in that: management interrupt is nested on software layer, the stack space of multistage interrupt nesting using system is preserved context, and the context of task will be stored in the stack space of task, need carry out the switching of system stack and task stack when processor switches between nested interrupt and user task.
4, the interrupt management method of the embedded OS based on the PowerPC architecture according to claim 1, it is characterized in that: system break is meant all interruptions except external interrupt and maskable external breakpoint.System break will enter unified system break service routine inlet when taking place, only preserve a small amount of registers necessary data before the in commission disconnected service routine.
5, the interrupt management method of the embedded OS based on the PowerPC architecture according to claim 1, it is characterized in that: the user interrupts being meant external interrupt and maskable external breakpoint, external interrupt is triggered by external pin, the maskable external breakpoint interrupts being produced by other modules in the sheet, hardware system is not distinguished concrete user and is interrupted, and use unified user interrupt service routine inlet, come dispatched users to interrupt by safeguarding user's interrupt vector table.
6, the interrupt management method of the embedded OS based on the PowerPC architecture according to claim 1, it is characterized in that: the user has been a serial ports interrupt configuration one section one class interrupt service routine, when this serial ports interrupted taking place, this Interrupt Process process was as follows:
1), interrupt to take place, hardware finds unified user to interrupt inlet from interrupt vector table, begins to carry out following steps from this inlet;
2), preserve return address and a spot of register that will in following steps, use;
3) need switch to system stack from task stack if enter interruption, not switch if nested interrupt does not then need to carry out storehouse from task;
4), the low interruption of this interrupt priority level of shielding ratio;
5), obtain interrupt source, user interrupt service routine and the execution of finding this serial ports to interrupt from user's interrupt vector table according to this value then;
6) if the task of returning need be switched back task stack from system stack from interrupt, if withdraw from from nested interrupt then do not need to carry out the storehouse switching;
7), recover the register of preservation in step 2;
8), from this interruption, withdraw from the interrupted program of continuation execution.
7, the interrupt management method of the embedded OS based on the PowerPC architecture according to claim 1, it is characterized in that: the user has been an analog to digital conversion interrupt configuration one two class interrupt service routine, when this interrupts taking place, interrupt service routine can activate an analog-to-digital task of processing with higher priority, to guarantee after interruption is withdrawed from, even this task energy is moved, this Interrupt Process process is as follows:
1), interrupt to take place, hardware finds unified user to interrupt inlet from interrupt vector table, begins to carry out following steps from this inlet;
2), preserve return address and a spot of register that will in following steps, use;
3) need switch to system stack from task stack if enter interruption, not switch if nested interrupt does not then need to carry out storehouse from task;
4), preserve non volatile register, non volatile register comprises universal integer type register GPR14-GPR31, CR, XER, CTR on the MPC555 hardware platform;
5), the low interruption of this interrupt priority level of shielding ratio;
6), obtain interrupt source, find the user interrupt service routine that this serial ports interrupts and carry out from user's interrupt vector table, this program has activated the task of a high priority;
7) if the task of returning need be switched back task stack and recover the value of non volatile register from system stack from interrupt, if withdraw from from nested interrupt then do not need to carry out the storehouse switching;
8), all registers of recovering step 2 and step 4 preservation;
9), from this interruption, withdraw from,, then continue the outage service routine if from nested interrupt, withdraw from; If return task layer,,, move this high-priority task rather than continue to carry out interrupted program so cause scheduler program because the task of a high priority is activated.
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| GB2473910A (en) * | 2009-09-10 | 2011-03-30 | Miniweb Technologies Ltd | Backup for user invoked interruptions |
| CN102033779A (en) * | 2010-12-17 | 2011-04-27 | 青岛海信信芯科技有限公司 | Interrupt processing method and microcontroller |
| CN101290591B (en) * | 2008-06-03 | 2011-10-12 | 北京中星微电子有限公司 | Embedded operating system task switching method and unit |
| CN101290590B (en) * | 2008-06-03 | 2012-01-11 | 北京中星微电子有限公司 | Embedded operating system task switching method and unit |
| CN101441609B (en) * | 2007-11-21 | 2012-07-04 | Arm有限公司 | Interrupt jitter suppression |
| CN101639791B (en) * | 2009-08-31 | 2012-12-05 | 浙江大学 | Method for improving interruption delay of embedded type real-time operation system |
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| CN106874072A (en) * | 2015-12-14 | 2017-06-20 | 中国航空工业第六八研究所 | A kind of processing method of the embedded OS subregion virtual interrupt based on Power PC Processor |
| CN110362396A (en) * | 2019-07-23 | 2019-10-22 | 天津国芯科技有限公司 | Based on powerpc framework and support the external interrupt management method and system of interrupt nesting |
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| CN101441609B (en) * | 2007-11-21 | 2012-07-04 | Arm有限公司 | Interrupt jitter suppression |
| CN101290591B (en) * | 2008-06-03 | 2011-10-12 | 北京中星微电子有限公司 | Embedded operating system task switching method and unit |
| CN101290590B (en) * | 2008-06-03 | 2012-01-11 | 北京中星微电子有限公司 | Embedded operating system task switching method and unit |
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| CN101639791B (en) * | 2009-08-31 | 2012-12-05 | 浙江大学 | Method for improving interruption delay of embedded type real-time operation system |
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| CN102033779B (en) * | 2010-12-17 | 2013-04-03 | 青岛海信信芯科技有限公司 | Interrupt processing method and microcontroller |
| CN102033779A (en) * | 2010-12-17 | 2011-04-27 | 青岛海信信芯科技有限公司 | Interrupt processing method and microcontroller |
| CN103412796A (en) * | 2013-08-30 | 2013-11-27 | 北京经纬恒润科技有限公司 | Stack allocation method and stack allocation unit for tasks in operating system |
| CN103676727A (en) * | 2013-11-27 | 2014-03-26 | 南京国电南自美卓控制系统有限公司 | Preemptible and nestable interrupt control method based on embedded chip |
| CN106874072A (en) * | 2015-12-14 | 2017-06-20 | 中国航空工业第六八研究所 | A kind of processing method of the embedded OS subregion virtual interrupt based on Power PC Processor |
| CN110362396A (en) * | 2019-07-23 | 2019-10-22 | 天津国芯科技有限公司 | Based on powerpc framework and support the external interrupt management method and system of interrupt nesting |
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