CN102026499B - Structure of substrate, and manufacturing method thereof - Google Patents

Structure of substrate, and manufacturing method thereof Download PDF

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CN102026499B
CN102026499B CN200910174788A CN200910174788A CN102026499B CN 102026499 B CN102026499 B CN 102026499B CN 200910174788 A CN200910174788 A CN 200910174788A CN 200910174788 A CN200910174788 A CN 200910174788A CN 102026499 B CN102026499 B CN 102026499B
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layer
dielectric layer
patterning
metal level
behind
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CN102026499A (en
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李志成
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

A manufacturing method for the substrate structure comprises the following steps: a substrate is provided with a patterned first metal layer, a patterned second metal layer and a through hole; then a first dielectric layer and a second dielectric layer are formed on a first surface and a corresponding second surface of the substrate; after that, the first dielectric layer and the second dielectric layer are patterned; a first line layer is formed on a surface of the patterned first dielectric layer, then the first line layer is embedded in the patterned first dielectric layer, wherein the both layers are in the same plane; and finally, a second line layer is formed on a surface of the second dielectric layer.

Description

The manufacturing approach of board structure
Technical field
The invention relates to a kind of board structure and manufacturing approach thereof, and particularly have the board structure and the manufacturing approach thereof of different structure relevant for a kind of two surfaces of substrate.
Background technology
At present, for the compact size trend in response to electronic product, circuit board is step by step towards the designs that for example is ultra-fine circuit (Ultrafine line).
The circuit board that at present existing upper and lower surfaces all has the routing layer of ultra-fine circuit is suggested.Yet such circuit board must carry out the technology of twice ultra-fine circuit, and required cost is very high.Therefore, how reducing the circuit board of the routing layer with ultra-fine circuit, is one of problem of endeavouring of industry.
Summary of the invention
The present invention mainly provides a kind of board structure and manufacturing approach thereof, and it has thin thickness, and advantage of low manufacturing cost.
According to the present invention, a kind of manufacturing approach of board structure is proposed, comprise the steps.One substrate is provided, and substrate has the first metal layer behind the patterning, one second metal level and the through hole behind the patterning.Then, form one first dielectric layer and one second dielectric layer a first surface and a corresponding second surface in substrate.Then, patterning first dielectric layer and second dielectric layer.Then, form a surface of first dielectric layer of one first routing layer behind patterning, first routing layer is embedded in first dielectric layer behind the patterning, and with the first dielectric layer copline.Then, form one second routing layer on a surface of second dielectric layer.
According to the present invention, reintroduce a kind of board structure, comprise a substrate, one first dielectric layer, one second dielectric layer, one first routing layer and one second dielectric layer.Substrate has the first metal layer behind the patterning, one second metal level and the through hole behind the patterning.Through hole electrically connects the first metal layer and second metal level.First dielectric layer is disposed at a first surface of substrate.Second dielectric layer is disposed at a second surface of substrate.First surface and second surface are relative.First routing layer is embedded in first dielectric layer, and with first dielectric layer be copline.Second routing layer is disposed on the surface of second dielectric layer.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows:
Description of drawings
Fig. 1 illustrates the sketch map of the board structure of one preferred embodiment according to the present invention.
Fig. 2 illustrates the flow chart of first kind of manufacturing approach of the board structure among Fig. 1.
Fig. 3 A~3F illustrates the schematic flow sheet according to first kind of manufacturing approach of the board structure among Fig. 2.
Fig. 4 illustrates the third flow chart of the manufacturing approach of the board structure among Fig. 1.
Fig. 5 A~5G illustrates the schematic flow sheet according to the third manufacturing approach of the board structure among Fig. 4.
The primary clustering symbol description
100: board structure
110: substrate
111: the first metal layer
112: the second metal levels
113: through hole
110s1: first surface
110s2: second surface
121: the first dielectric layers
121h, 122h: blind hole
121s, 122s: surface
122: the second dielectric layers
131: the first routing layers
131a, 131a ': the 3rd metal level
132: the second routing layers
132a, 132a ': the 4th metal level
141: the first Seed Layer
142: the second Seed Layer
150: photoresist layer
D1, d2, d11, d12, d21, d22: thickness
S201~S211, S201 '~S211 ': process step
Embodiment
Please with reference to Fig. 1, it illustrates the sketch map of the board structure of one preferred embodiment according to the present invention.Board structure 100 comprises a substrate 110, one first dielectric layer 121, one second dielectric layer 122, one first routing layer 131 and one second routing layer 132.
Substrate 110 has the first metal layer 111, one second metal level 112 behind the patterning and the through hole 113 behind the patterning.Through hole 113 electrically connects the first metal layer 111 and second metal level 112.First dielectric layer 121 is disposed at a first surface 110s1 of substrate 110, and second dielectric layer 122 is disposed at a second surface 110s2 of substrate 110.First surface 110s1 is relative with second surface 110s2.First routing layer 131 is embedded in first dielectric layer 121, and with first dielectric layer 121 be copline.Second routing layer 132 is disposed at a surface of second dielectric layer 122 and goes up 122s.
Now the board structure 100 with present embodiment further specifies as follows.In present embodiment, first routing layer 131 has the fine rule road, in order to electrically connect chip.To be electrically connected at the mode of chip for example be to utilize crystalline substance (Flip chip) mode of covering of tin ball or projection (Cu pillar) to first routing layer 131 here.The distance between centers of tracks of walking on fine rule road for example is between 6 to 30 microns, and the thickness of the cabling on fine rule road for example is between 5 to 15 microns.In addition, to be disposed at the thickness on the surface of second dielectric layer 122 for example be between 12 to 20 microns to second routing layer 132.Because first routing layer 131 is embedded in first dielectric layer 121, therefore, the thickness d 1 of first dielectric layer 121 need be kept certain size, to let first routing layer 131 and the routing layer at the first surface 110s1 place certain spacing of being separated by avoid short circuit.And second routing layer 132 is because be not to be embedded in second dielectric layer 122, so the thickness d 2 of second dielectric layer 122 can be designed to the thickness d 1 less than first dielectric layer 121, to reduce the integral thickness of board structure 100.The thickness d 1 of first dielectric layer 121 here can be designed to greater than the thickness d of second dielectric layer 122 2 about 10~20 microns.
In addition, suppose that first routing layer 131 and second routing layer 132 of present embodiment forms with the mode of electroplating, the conductive layer when then board structure 100 can more be formed with first Seed Layer 141 and second Seed Layer 142 and is used as electroplating.First Seed Layer 141 is disposed between first dielectric layer 121 and first routing layer 131, and second Seed Layer 142 is disposed between second dielectric layer 122 and second routing layer 132.First Seed Layer 141 here and the material of second Seed Layer 142 can for example be chemical copper (E ' less Cu).Moreover board structure 100 can more comprise several tin balls, is disposed on second routing layer 132, so that the function of external electric connection to be provided.
Thus; Have under the prerequisite of identical functions; The board structure that all has the routing layer that is embedded in the ultra-fine circuit in the dielectric layer compared to upper surface and lower surface; The board structure 100 of present embodiment in the first surface 110s1 and the second surface 110s2 of substrate 110, can make that the integral thickness of substrate 110 is thinner via the routing layer that disposes different structure.
In present embodiment, board structure 100 can for example utilize three kinds of following manufacturing approaches to process, and below will distinguish explanation at length.
Please be simultaneously with reference to Fig. 2 and Fig. 3 A~3F, Fig. 2 illustrates the flow chart of first kind of manufacturing approach of the board structure among Fig. 1, and Fig. 3 A~3F illustrates the schematic flow sheet according to first kind of manufacturing approach of the board structure among Fig. 2.First kind of manufacturing approach of this of board structure 100 comprises the steps.
In step S201, substrate 110 is provided, substrate 110 has the first metal layer 111 behind the patterning, second metal level 112 and through hole 113 behind the patterning, shown in Fig. 3 A.In present embodiment, through hole 113 electrically connects the first metal layer 111 and second metal level 112.Though it is that example is done explanation that present embodiment has the first metal layer 111, second metal level 112 and through hole 113 with substrate 110, right substrate 110 also can be the substrate (not illustrating) with the metal level more than two layers.
Then, in step S203, form first dielectric layer 121 and second dielectric layer 122 first surface 110s1 and corresponding second surface 110s2, shown in Fig. 3 B in substrate 110.Step S203 for example is that the mode with vacuum pressing-combining (vacuum lamination) forms first dielectric layer 121 and second dielectric layer 122.
Then, in step S205, patterning first dielectric layer 121 and second dielectric layer 122 are shown in Fig. 3 C.Patterning first dielectric layer 121 for example is to utilize PRK (Excimer Laser) to reach; Correspond to the pattern on the fine rule road (Ultrafine line) of first routing layer 131 with formation, and utilize ultraviolet light-Ya chromium laser (UV-YAG Laser) to form the pattern of blind hole (VIA) 121h that corresponds to first dielectric layer 121.In addition, patterning second dielectric layer 122 for example is to utilize ultraviolet light-Ya chromium laser to form the pattern of the blind hole 122h that corresponds to second dielectric layer 122.
Then, in step S207, form the surperficial 121s of first dielectric layer 121 of the 3rd metal level 131a behind patterning, and form the 4th metal level 132a on the surperficial 122s of second dielectric layer 122 behind the patterning, shown in Fig. 3 D.In present embodiment, the thickness d 12 of the 4th metal level 132a on the surperficial 122s that is positioned at second dielectric layer 122 that forms is preferably greater than the thickness d 11 of the 3rd metal level 131a on the formed surperficial 121s that is positioned at first dielectric layer 121.
Then, in step S209, reduce the thickness of the 3rd metal level 131a, and reduce the thickness of the 4th metal level 132a, make remaining the 3rd metal level 131a be embedded in first dielectric layer 121 behind the patterning and form first routing layer 131, shown in Fig. 3 E.In this embodiment, the thickness that has only the 3rd metal level 131a to be higher than first dielectric layer 121 will fully be reduced, and is arranged in the 3rd metal level 131a that is embedded in first dielectric layer 121 only to stay.In Fig. 3 E, the part of the 3rd metal level 131a that is reduced and the 4th metal level 132a that is reduced is represented by dotted lines.The thickness of the 3rd metal level 131a for example reduces with identical process quilt with the thickness of the 4th metal level 132a.Step S209 for example is the thickness that reduces by the 3rd metal level 131a with the mode of etching or grinding, and for example is the thickness that reduces by the 4th metal level 132a with the mode of etching or grinding.In present embodiment, the thickness of the 3rd metal level 131a is for example identical in fact with the amount that thickness reduced of the 4th metal level 132a.
Then, in step S211, patterning the 4th metal level 132a is to form second routing layer 132 on the surperficial 122s of second dielectric layer 122, shown in Fig. 3 F.
In order to be provided in the function of external electric connection, the manufacturing approach of present embodiment can comprise more that several tin balls of formation are on second routing layer 132.
The manufacturing approach of supposing present embodiment forms the 3rd metal level 131a and the 4th metal level 132a with respectively as the part of first routing layer 131 and second routing layer 132 with the mode of electroplating.For the conductive layer when electroplating is provided; Before step S207, the manufacturing approach of board structure 100 more comprises on the surperficial 122s that forms first Seed Layer 141 and second dielectric layer 122 of second Seed Layer 142 (as shown in Figure 1) after the surperficial 121s of first dielectric layer 121 behind the patterning of Fig. 3 C upward reaches patterning respectively.In addition, preferably, after step S211, the manufacturing approach of board structure 100 comprises that the more surperficial 122s that removes second dielectric layer 122 goes up second Seed Layer of exposing via second routing layer 132 142, to avoid short circuit.The mode that removes can be removed via the mode of etching or subordinate's preliminary treatment (downstream pretreatment).
In addition; For the glue slag (smear) of the surperficial 122s that removes the surperficial 121s remain in first dielectric layer 121 and second dielectric layer 122 effectively, the manufacturing approach of the board structure 100 of this enforcement can be in the step of the surperficial 122s of the surperficial 121s of first dielectric layer 121 after more comprising cleaning (desmear) patterning before the step that forms first Seed Layer 141 and second Seed Layer 142 and second dielectric layer 122 after the cleaning patterned.The step of cleaning can for example be to carry out with etched mode.The step of this cleaning can be removed the glue slag of perforation bottom, and the surface roughening that makes dielectric layer is in order to follow-up technology.
This kind manufacturing approach of board structure 100 only needs when patterning first dielectric layer 121, to use PRK.Because it is very expensive using the technology of PRK, therefore, utilize twice PRK to come the manufacturing approach of the board structure of two dielectric layers of patterning respectively compared to need, this kind manufacturing approach of board structure 100 can reduce manufacturing cost effectively.In addition; Because the thickness that only has the 3rd metal level 131a to be higher than first dielectric layer 121 will fully be reduced; And the thin thickness of comparable first dielectric layer 121 of the thickness of second dielectric layer 122, these factors make the required manufacturing cost of present embodiment more can reduce further.
Second kind of manufacturing approach of board structure 100 below then is described.Different with first kind of manufacturing approach is that second kind of manufacturing approach of board structure 100 changed the 3rd metal level and the 4th metal layer thickness is reached.In more detail; Compare with first kind of manufacturing approach; In the another kind of manufacturing approach of board structure 100; Though formed the 4th metal layer thickness is not less than the 3rd metal layer thickness of formation; Yet, the thickness difference of formed the 3rd metal level 131a and the 4th metal level 132a in the 3rd metal level that forms in second kind of manufacturing approach and first kind of manufacturing approach of the 4th metal layer thickness difference less than the board structure among Fig. 2 100, and the 3rd metal layer thickness that reduces is greater than the 4th metal layer thickness that reduces.
For instance, the mode with etching and grinding in second kind of manufacturing approach reduces by the 3rd metal layer thickness, and only reduces the step of the 4th metal layer thickness with etched mode.Thus, based on the design of the 3rd above-mentioned metal level and the 4th metal layer thickness, and other is similar to the flow process among Fig. 3 A~Fig. 3 F, can be made into the board structure 100 among Fig. 1 equally.Second kind of manufacturing approach also can be reached the advantage of similar first kind of manufacturing approach.
Except two kinds of above-mentioned manufacturing approaches, but board structure 100 also the process step of Fig. 4 and Fig. 5 A~5G process.Please be simultaneously with reference to Fig. 4 and Fig. 5 A~5G, Fig. 4 illustrates the flow chart of the third manufacturing approach of the board structure among Fig. 1, and Fig. 5 A~5G illustrates the schematic flow sheet according to the third manufacturing approach of the board structure among Fig. 4.The third manufacturing approach of board structure 100 comprises the steps.
Compare with the process step among Fig. 2, the step S201 ' among Fig. 4 to step S205 ' respectively with Fig. 2 in step S201 identical to step S205.Step S201 ' provides substrate 110 (shown in Fig. 5 A), step 203 ' form first dielectric layer 121 and second dielectric layer 122 (shown in Fig. 5 B), and step S205 ' follows patterning first dielectric layer 121 and second dielectric layer 122 (shown in Fig. 5 C).
Then, in step S206a ', form photoresist layer 150 on the surperficial 122s of second dielectric layer 122 behind the patterning.
Then, in step S206b ', patterning photoresist layer 150 is shown in Fig. 5 D.
Then; In step S207 '; Form the surperficial 121s of first dielectric layer 121 of the 3rd metal level 131a ' behind patterning, and form on the surperficial 122s of second dielectric layer 122 behind the patterning that the photoresist layer 150 of the 4th metal level 132a ' after not being patterned cover, shown in Fig. 5 E.In present embodiment, the thickness d 21 of the 3rd metal level 131a ' that the thickness d 22 of the 4th metal level 132a ' of formation can equal in fact to form.
Then, in step S209 ', reduce the thickness of the 3rd metal level 131a ', make remaining the 3rd metal level 131a ' be embedded in first dielectric layer 121 behind the patterning and form first routing layer 131, shown in Fig. 5 F.The part of the 3rd metal level 131a ' that reduces is represented by dotted lines.Step S207 ' for example is the thickness that reduces by the 3rd metal level 131a ' with the mode of etching and grinding.
Then, in step S211 ', remove the photoresist layer 150 behind the patterning, to form second routing layer 132, shown in Fig. 5 G.
For the function of external electric connection is provided, the manufacturing approach of present embodiment can more comprise and forms several tin balls on second routing layer 132.
Other for example is that the step that cleans first dielectric layer 121 and second dielectric layer 122, the step that reaches formation first Seed Layer 141 and second Seed Layer 142 ought can be carried out no longer repeat specification here according to process requirements.The third manufacturing approach also can be reached the advantage of similar first kind of manufacturing approach.
Board structure that the above embodiment of the present invention disclosed and manufacturing approach thereof, its first routing layer disposes with the mode that is embedded in first dielectric layer, and second routing layer disposes with the mode that is disposed on second dielectric layer.Thus, all have the board structure of the routing layer that is embedded in the ultra-fine circuit in the dielectric layer compared to upper and lower surfaces, the integral thickness of the board structure of a plurality of embodiment of the present invention is thinner, and manufacturing cost is lower.In addition, generally speaking the routing layer of base lower surface in order to as ground plane or Dc bias layer, not too needs ultra-fine circuit can reach desired function usually usually.Therefore, the general routing layer of embodiments of the invention (for example second routing layer 132) is enough as ground plane or Dc bias layer.Therefore, a plurality of embodiment of the present invention can have advantage with low cost simultaneously under the prerequisite that the actual product of reaching industry requires, quite have the market competitiveness.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.

Claims (7)

1. the manufacturing approach of a board structure comprises:
One substrate is provided, and this substrate has a first metal layer, one second metal level behind the patterning and the through hole (Through hole) behind the patterning;
Form one first dielectric layer and one second dielectric layer a first surface and a corresponding second surface in this substrate;
This first dielectric layer of patterning and this second dielectric layer;
Form this surface of this first dielectric layer of one the 3rd metal level behind patterning;
Form one the 4th metal level on this surface of this second dielectric layer behind the patterning, the 4th metal layer thickness that wherein forms is greater than the 3rd metal layer thickness that forms;
Reduce by the 3rd and the 4th metal layer thickness simultaneously; Make remaining the 3rd metal level be embedded in first dielectric layer behind this patterning and form first routing layer, the 4th metal layer thickness that the 3rd metal layer thickness that wherein reduces equals to reduce; And
Remaining the 4th metal level of patterning is to form second routing layer.
2. manufacturing approach as claimed in claim 1 wherein reduces this step of the 3rd metal level and carries out with the mode of etching and grinding, and this step that reduces by the 4th metal level is carried out with etched mode.
3. manufacturing approach as claimed in claim 1, wherein before this step that forms the 3rd metal level, this manufacturing approach more comprises:
Form one first Seed Layer on this surface of this first dielectric layer behind the patterning;
Wherein, before this step that forms the 4th metal level, this manufacturing approach more comprises:
Form one second Seed Layer on this surface of this second dielectric layer behind the patterning;
Wherein, after this step of patterning the 4th metal level, this manufacturing approach more comprises:
Remove this lip-deep this second Seed Layer of this second dielectric layer.
4. the manufacturing approach of a board structure comprises:
One substrate is provided, and this substrate has a first metal layer, one second metal level behind the patterning and the through hole (Through hole) behind the patterning;
Form one first dielectric layer and one second dielectric layer a first surface and a corresponding second surface in this substrate;
This first dielectric layer of patterning and this second dielectric layer;
Form this surface of this first dielectric layer of one the 3rd metal level behind patterning;
Form a photoresist layer on this surface of this second dielectric layer behind the patterning;
This photoresist layer of patterning;
Form on this surface of this second dielectric layer behind the patterning that one the 4th metal level this photoresist layer after not being patterned covers;
Reduce by the 3rd and the 4th metal layer thickness simultaneously; Make remaining the 3rd metal level be embedded in first dielectric layer behind this patterning and form first routing layer, the 4th metal layer thickness that the 3rd metal layer thickness that wherein reduces equals to reduce; And
Remove this photoresist layer behind the patterning, to form second routing layer.
5. manufacturing approach as claimed in claim 4, wherein before this step that forms the 3rd metal level, this manufacturing approach more comprises:
Form one first Seed Layer on this surface of this first dielectric layer behind the patterning;
Wherein, before this step that forms this photoresist layer, this manufacturing approach more comprises:
Form one second Seed Layer on this surface of this second dielectric layer behind the patterning;
Wherein, after this step of this photoresist layer after removing patterning, this manufacturing approach more comprises:
Remove this lip-deep this second Seed Layer of this second dielectric layer.
6. manufacturing approach as claimed in claim 4; Wherein the step of this first dielectric layer of patterning and this second dielectric layer utilizes ultraviolet light-Ya chromium laser (UV-YAG Laser) to reach, to form the pattern of the blind hole (Via) that corresponds to this first dielectric layer and this second dielectric layer respectively.
7. manufacturing approach as claimed in claim 4, wherein this step of this first dielectric layer of patterning utilizes PRK (Excimer Laser) to reach, and corresponds to the pattern on the fine rule road (Ultrafine line) of this first routing layer with formation.
CN200910174788A 2009-09-14 2009-09-14 Structure of substrate, and manufacturing method thereof Active CN102026499B (en)

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Publication number Priority date Publication date Assignee Title
TWI634636B (en) * 2016-09-09 2018-09-01 思鷺科技股份有限公司 Semiconductor structure
CN111862886A (en) * 2020-08-03 2020-10-30 京东方科技集团股份有限公司 Driving substrate, manufacturing method thereof and display device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW453141B (en) * 1998-09-28 2001-09-01 Ibiden Co Ltd Printed circuit board and its manufacture method
CN1458815A (en) * 2002-05-14 2003-11-26 新光电气工业株式会社 Metal core base plate and its producing process
JP2006339483A (en) * 2005-06-03 2006-12-14 Toppan Printing Co Ltd Wiring board and manufacturing method thereof
CN1980540A (en) * 2005-11-30 2007-06-13 全懋精密科技股份有限公司 Circuit board structure and making method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW453141B (en) * 1998-09-28 2001-09-01 Ibiden Co Ltd Printed circuit board and its manufacture method
CN1458815A (en) * 2002-05-14 2003-11-26 新光电气工业株式会社 Metal core base plate and its producing process
JP2006339483A (en) * 2005-06-03 2006-12-14 Toppan Printing Co Ltd Wiring board and manufacturing method thereof
CN1980540A (en) * 2005-11-30 2007-06-13 全懋精密科技股份有限公司 Circuit board structure and making method

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