CN102024819A - SRAM bit cell device vs. CAM bit cell device - Google Patents

Abstract

The present invention provides a device for static random access memory (SRAM) and content addressable memory (CAM) bit cells. In an embodiment, a bit cell portion has a storage transistor with a thick gate oxide layer, and a read portion has a transistor with a thin gate oxide layer. The use of a thick gate oxide layer in the storage cell transistor provides stable data storage and low leakage current. The use of a thin gate oxide layer in the read portion transistor provides a fast read speed and low Vcc, min. The present invention is used to form an SRAM cell with a double gate oxide thickness and is suitable for current semiconductor processes. The embodiments disclose the use of high-k dielectric constants and dual dielectric materials in a single bit cell, and the use of finFETs and planar transistors in a bit cell. The present invention also discloses methods for forming these structures. The SRAM bit cell structure of the present invention is used to reduce standby power consumption and improve access speed without adding significant steps and costs.

Description

SRAM bit cell device vs. CAM bit cell device

technical field

The present invention relates to a static random access memory (Static Random Access Memory, SRAM) bit cell structure and a method for providing a bit cell with improved standby leakage current (Isb) to obtain improved standby action, improved Vcc,min, Reduced supply levels have minimum power, high read times.

The bitcell includes a new layout with multiple thickness gate oxides in the cell transistors. The use of the present invention provides the advantage of using SRAM for integrated circuits with logic circuits or user-specified circuits. In addition to SRAM arrays of SRAM bit cells, SRAM cells also possess improved stability and provide reliable operation in a wide range of conditions. Methods of fabricating SRAM bit cells incorporating features of the present invention are compatible with existing state of the art and planned semiconductor processes.

Background technique

Today's general requirement for electronic circuits, especially for electronic circuits fabricated as integrated circuits in semiconductor processes, is an array of on-substrate or built-in memory storage elements. These elements can be either dynamic random access memory (DRAM) cells or static random access memory (SRAM) cells. DRAM and SRAM memory are called volatile memory cells, in which the stored data disappears if the power supply to the integrated circuit is removed. DRAM cells can provide very dense arrays because a DRAM cell requires only a single access transistor and storage capacitor. However, DRAM circuits have relatively slow read and write times and require more complex control circuits. Each DRAM cell stores data by charging the drain capacitance, so the DRAM array must be refreshed periodically to maintain the state. This requires the processor to periodically stop other operations to perform the refresh cycle, or a dedicated memory controller (more commonly used in current production devices) to perform the refresh cycle. SRAM arrays require more silicon area because each bit cell is typically a phase lock consisting of six or more transistors. However, SRAM cells retain data as long as the supply voltage is present. A further advantage is that the access time of SRAM cells is faster than that of DRAM cells, making SRAM cells particularly attractive for temporary or working data storage (eg, cache memory for processors). Recent system-on-chip (SOC) designs typically incorporate one or more cores. These cores are usually pre-designed flow processors (such as DSPs, ARMs, RISC, or microprocessors) adjacent to or near the processor with a level 1 (L1) cache memory of an SRAM cell, so that The calculation processing speed can be faster.

Integrated circuits are increasingly used in battery-driven devices. For example, an SOC may be used to provide all or most of the circuits used to implement the main functions of a mobile phone, laptop computer, notebook computer, video player, camcorder, camera, smart phone, or PDA. In these devices, customer-defined logic or licensed processor core designs are combined with other predetermined or macro units such as microprocessors, digital signal processors, cores (such as ARM, RISC, or similar core functions), Mobile phone modules, etc.) are integrated together.

In an SRAM bit cell, data is stored in two inversely related storage nodes. A pair of CMOS inverters (composed of four MOS transistors) is configured as a latch unit. In complementary MOS (CMOS) technology, each storage node is formed by the gate terminals of two MOS transistors and receives the output of an inverter consisting of two MOS transistors.

FIG. 1 shows an SRAM bit cell 10 in a typical 6T configuration. In FIG. 1 , a pair of MOS conductive gates PG1 and PG2 are respectively electrically connected to a pair of data lines (also referred to as bit lines BL and BLB) to storage contacts SN1 and SN2 . The conductive gates PG1 and PG2 are generally composed of NMOS transistors in the known technology. The figure shows a positive supply voltage Vdd, which can range from 0.6 volts to 3.0 volts or higher, depending on the technology. The pull-up transistors PU1 and PU2 are composed of PMOS transistors and electrically connect the positive supply voltage to one or the other storage node, depending on the state of the SRAM cell 10 . Also shown is a second supply voltage Vss, typically grounded.

Two pull-down transistors PD1 and PD2 (also NMOS transistors) electrically connect negative or ground voltage Vss to one or the other storage node SN1 and SN2, depending on the state of the bit cell. The bit cell is a phase locker that holds the data state indefinitely as long as the supplied power is sufficient to operate the circuit correctly. Two CMOS inverters composed of PU1 , PD1 and PU2 , PD2 are interleavedly coupled to each other, and their operation is used to continuously enhance the charges stored in the storage nodes SN1 and SN2 . The two storage nodes are shown as inverse phases of each other in the figure. When SN1 is logic state 1 (usually high), SN2 will be logic 0 (usually low) at the same time, and vice versa.

When the SRAM bit cell 10 is written, the complementary write data will be input into the bit line pair BL and BLB respectively. A positive control signal on the word line WL is electrically connected to the gates of the two conductive gates PG1 and PG2. The dimensions of transistors PU1 , PD1 and PU2 , PD2 enable data on the bit lines to overwrite stored data, thereby being written into the SRAM bit cell 10 .

When the SRAM bit cell 10 is read, a positive voltage is applied to the word line WL, and the conductive gates PG1 and PG2 allow the bit lines BL and BLB to be electrically connected to the storage nodes SN1 and SN2 to receive data. Unlike dynamic memory cells, SRAM bit cells do not lose their stored state during reads if the power supply Vdd is maintained at a sufficiently high level. Therefore, after the reading operation is completed, there is no need to perform a write back (write back) action.

The bit lines BL and BLB form a complementary pair of data lines. The two paired data lines can be electrically connected to a differential sense amplifier (not shown in the figure), and the differential voltage can be sensed and amplified, which is a design well known to those skilled in the art. This amplified and sensed output signal can be used as a data output to other logic circuits in the device.

Figure 2 shows another form of conventional SRAM bit cell 12 in which eight transistors (8T) are used and the read port 14 is configured with additional functionality. In FIG. 2 , there is a unit 10 of 6T shown in FIG. 1 . The SRAM bit cell 12 additionally has a read port 14 composed of two NMOS transistors, the two transistors being the read port pull-down transistor RPD and the read port pass-gate transistor RPG respectively. The read port 14 also has a read word line RWL for read only. The word line WL previously in FIG. 1 is a write-only write word line WWL in cell 12 of 8T in FIG. 2 . The advantage of separating the read port is that the chance of read disturb is reduced, because the data stored in the bit cell will be affected by the read operation. In contrast, the read pull-down transistor RPD is turned on or off according to the storage node SN2 electrically connected to its gate. Since the NMOS transistor has a gain, the data signal stored at the node SN2 will be amplified by the gain of the transistor RPD. Therefore, when the read word line RWL is applied with a positive voltage, the read conduction gate RPG is turned on and electrically connects the read bit line RBL to the read pull-down transistor, so that the read port outputs a corresponding data bit at read on bit line RBL. In many applications, SRAM arrays of many bit cells are used to store data or programs for retrieval and later use. SRAM cells experience more read operations than write operations in the same period of time. It is therefore helpful to separate the read operation from the bit cell through the read port 14, even though the 8T cell uses more silicon layout area to accomplish. Also, when trying to save power (Vdd), the smallest characteristic measurement becomes more important for reading the circuit since that is the part of the circuit that is most active.

Figure 3 shows another known SRAM bit cell 20 in which 10 transistors (10T) are used. In this configuration, the circuit has two read ports electrically connected to the storage nodes SN1 and SN2 of the 6T cell 10, respectively. Read ports 22 and 24 have respective control lines RWL1 and RWL2 and pull-down NMOS transistors and pass-gate NMOS transistors, respectively. The two read bit lines RBL1 and RBL2 are electrically connected to the pull-down transistors RPD1 and RPD2 through the conduction gates RPG1 and RPG2 respectively. The pull-down transistors respectively have a gate connected to the storage nodes SN1 and SN2. The reading actions can be performed independently or simultaneously. Using two read ports provides additional flexibility and enables two outputs to be read from the unit simultaneously.

As the demand for low power consumption integrated circuits continues and increases (especially for more complex battery powered portable devices), SRAM cells need to have good power saving characteristics. One of the limiting methods of power consumption must rely on the standby leakage current (hereinafter expressed as Isb). When the SRAM cells are not being used, the SRAM array is in standby mode. The leakage current Isb in standby must be reduced. In the known technology, it is widely known to reduce the positive power supply in the standby mode as much as possible to reduce the power consumption of the CMOS circuit. The metric used to determine the Vcc level is Vcc,min. It is clearly advantageous to provide an SRAM cell with a low Vcc,min value. This is difficult to implement effectively for 6T memory cells because of increasing process variations and other constraints due to shrinking device dimensions and process advancements.

However, the circuit described above still has excellent timing (read speed) and can operate efficiently without generating read disturb errors. The last characteristic can be called the stability of the circuit. One way to maintain stability is to reduce the Vcc,min applied to the SRAM memory cell. With the advancement of semiconductor technology, the device size continues to shrink. The use of smaller devices has resulted in an extremely wide range of performance of the devices. In order to maintain operational reliability of these devices, a low Vcc,min is necessary. Although lowering Vcc, min is a good way to reduce power consumption, lowering Vcc, min is also necessary for SRAM arrays.

Therefore, we need an improved SRAM bit cell structure, which has lower standby leakage current Isb, improved Vcc, min to reduce standby power consumption, and improved access speed (especially during read operations), and at the same time The compatibility of known semiconductor process technologies for manufacturing integrated circuits is maintained without adding significant steps and costs.

Contents of the invention

These and other problems are generally solved or circumvented, and technical advantages are achieved by embodiments of the present invention. The invention provides a SRAM bit cell with a thicker gate oxide layer in the storage unit transistor and a thinner gate oxide layer in the read port transistor. Thick gate oxide for memory cell transistors provides stable data storage and low standby current. The thin gate oxide used for the read port transistors provides fast read times and allows for lower Vcc,min. The power supplied to the read port can be electrically connected to the logic portion of the device, while the power supplied to the memory cell transistors can be relatively high to improve reliability. The method is used to form SRAM cells with double gate oxide thickness and its process steps are compatible with the current step flow for semiconductor manufacturing.

In one embodiment, an SRAM bit cell device includes: a semiconductor substrate; and at least one SRAM bit cell formed on a portion of the semiconductor substrate. Wherein said at least one SRAM bit cell further comprises a transistor with a first gate dielectric layer thickness, and an additional transistor with a thinner second gate dielectric layer thickness, said thinner second gate dielectric layer thickness between 75% and 99% of the thickness of the first gate dielectric layer.

In another embodiment, an integrated circuit of an SRAM bit cell includes: a logic portion formed on a first portion of a semiconductor substrate and having a plurality of transistors, some of which have thinner gate dielectrics layer; and an SRAM array. Wherein the SRAM array includes a plurality of SRAM bit cells, and each SRAM bit cell is formed on the second portion of the semiconductor substrate. The SRAM bitcell also includes a transistor having a thicker gate dielectric layer thickness and an additional transistor having a second thinner gate dielectric layer thickness electrically connected to the transistor having a thicker gate dielectric layer thickness. layer thickness of the transistor. The thickness of the thinner second gate dielectric layer is between 75%-99% of the thickness of the first gate dielectric layer.

In another embodiment, a CAM bit cell device includes: a semiconductor substrate; and at least one CAM bit cell formed on a portion of the semiconductor substrate. Wherein said at least one CAM bit cell further comprises a transistor having a first gate dielectric layer thickness, and an additional transistor having a thinner second gate dielectric layer thickness, said thinner second gate dielectric layer thickness between 75% and 99% of the thickness of the first gate dielectric layer.

The SRAM bit cell structure of the present invention has lower standby leakage current Isb, improved Vcc, min to reduce standby power consumption, and improved access speed (especially when reading), while maintaining the known semiconductor process technology for Manufacture IC compatibility without adding significant steps and costs.

The summary of the present invention describes some embodiments of the present invention, but does not limit the present invention. Additional features and advantages of the invention will be described hereinafter, and the contents of the description form the subject of the claims of the application. Those skilled in the art can understand that the viewpoints and embodiments of this application can be used as a basis to modify or design other structures or processes to implement the same purpose as this application. Therefore, those skilled in the art should understand that similar structures do not deviate from the spirit and scope of the present invention, and the scope of the present invention will be defined by the following claims.

Description of drawings

FIG. 1 shows a conventional SRAM bit cell circuit.

FIG. 2 shows a conventional 8T SRAM bit cell circuit.

FIG. 3 shows a conventional 10T SRAM bit cell circuit.

FIG. 4 is an embodiment of the present invention, showing a circuit diagram of an 8T SRAM bit cell incorporating features of the present invention.

Figure 5 shows a floor plan of an 8T SRAM bit cell using a conventional gate dielectric.

FIG. 6 shows a cross-sectional view taken from the plan layout of FIG. 5 .

FIG. 7 shows a plan layout diagram of an 8T SRAM bit cell using the double gate dielectric layer of the present invention.

FIG. 8 shows a cross-sectional view taken from the plan layout of the embodiment of FIG. 7 .

Figure 9 shows a cross-sectional view of a read bit line connection configuration using conventional circuit metallization techniques.

FIG. 10 shows a cross-sectional view of a read bit line structure according to an embodiment of the present invention.

FIG. 11 shows the results of an electrical simulation comparison between the conventional read bit line metallization of FIG. 9 and the inventive embodiment of FIG. 10 .

FIG. 12 shows a layout diagram of configuring four 8T bit cells according to an embodiment of the present invention.

FIG. 13 shows a layout diagram of a 10T bit cell according to an embodiment of the present invention.

FIG. 14 shows the layout of the embodiment of FIG. 13 using metal 1 .

Figure 15 shows a circuit diagram of a content addressable memory bit cell.

FIG. 16 shows a CAM cell layout diagram of an embodiment of the present invention.

Figure 17 shows the three-dimensional structure of a finFET transistor device.

FIG. 18 shows a cross-sectional view of the finFET of FIG. 17 .

Figure 19 shows an embodiment of a dual port 8T SRAM bit cell with a read section using finFET transistors and another section using planar transistors.

The drawings of the present invention are not intended to be limiting, but rather represent examples of various embodiments of the present invention. The drawings are simplified for convenience of description, and therefore are not in actual scale.

Wherein, the reference signs are explained as follows:

10, 20, 42, 72-6T SRAM bit cells;

12, 40, 70-8T SRAM bit cells;

14, 22, 24, 44, 74 ~ read port;

20. 60-10T SRAM bit cells;

61, 62～gate dielectric layer;

73～CAM unit;

91～write part;

92～reading part;

93～Planar MOS transistors;

95 ~ finFET transistor;

PU1, PU2 ~ pull-up transistors;

PD1, PD2 ~ pull-down transistors;

PG1, PG2 ~ MOS conduction gate;

BL, BLB, WBL, WBLB ~ bit line;

WL, WWL～word line;

RBL ~ read bit line;

RWL ~ read word line;

RPG, RPG1, RPG2 ~ read port conduction gate transistor;

RPD, RPD1, RPD2 ~ read port pull-down transistor;

SN1, SN2～storage nodes;

OD～active area;

PO ~ polysilicon gate;

M1～Metal 1;

M2～only belongs to 2;

V1～channel;

CO ~ contact layer.

Detailed ways

The method of making and using the preferred embodiment of the present invention will be described in detail as follows. The many inventive application concepts provided by the present invention can be implemented in a wide variety of specific contexts. The specific embodiments discussed below are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

FIG. 4 is an embodiment of the present invention showing a circuit diagram of an 8T SRAM bit cell 40 incorporating the features of the double gate oxide layer of the present invention. In FIG. 4, the 6T memory cell part 42 has two PMOS pull-up transistors PU1 and PU2 as shown in FIGS. 1-3, and four NMOS transistors PG1, PG2, PD1 and PD2 as shown in FIGS. 1-3. . In this invention, thick gate dielectric layers are used to form the four NMOS transistors. By using a thick gate dielectric layer, the standby current Isb of the SRAM memory cell portion 42 is reduced and the stability is improved. As for the read port portion 44 of the 8T SRAM bit cell, a thin gate oxide dielectric is used instead. A thin gate dielectric will result in faster reading and lower Vcc,min. In fact, in an integrated circuit with a logic core, the readout portion 44 can be produced together with the logic and use the logic's thin gate dielectric and power. Therefore, the NMOS read port transistors RPG and RPD have a faster response time to make the read cycle faster, and allow a lower Vcc, min to reduce power consumption during the read operation.

The gate dielectric layer can be silicon oxide layer, silicon dioxide, silicon nitride, silicon oxynitride and other silicon-containing dielectrics known in the conventional art. High-k gate dielectrics may be used, for example, in some embodiments of the invention, dielectrics including hafnium, zirconium with or without silicate and oxygen may be used. The ratio of the thickness of the thin gate dielectric layer of the memory cell portion 42 to the thickness of the thick gate dielectric layer of the read portion 44 may be 0.75-0.99, preferably 0.85-0.95, and most preferably 0.85 -0.90. In one non-limiting example, the thick gate dielectric layer is formed of silicon dioxide in a 45 nm semiconductor process. The gate dielectric thickness of 2.43nm is formed by thermal oxidation in this example. But the invention applies to any semiconductor process and is beneficial to current and planned 45nm, 28nm, 22nm and even smaller size processes.

In an embodiment of the SRAM bit cell, the layout of the SRAM bit cell is also modified to further achieve the advantages of the dual gate oxide thickness of the present invention.

To illustrate these advantages, a conventional bit cell with a single gate dielectric thickness is first shown. FIG. 5 shows a planar layout of a SRAM 8T bit cell 40 with a constant thickness of the gate dielectric layer. In FIG. 5, the active region is denoted OD, which is formed between isolation fields (such as shallow trench isolation STI or LOCOS isolation). As is well known to those skilled in the art, the active region includes a diffusion region which extends into the semiconductor substrate and which may be doped to form an N or P type field and a lightly doped drain field, while the active region may also contain additional implanted to form source or drain regions. The active region may be located on the surface of the semiconductor wafer or in a silicon layer formed epitaxially on insulator (SOI). Transistors are formed in the bit cell region using a gate conductor deposited or patterned on a dielectric material overlying the active region. The gate dielectric cannot be seen in this plan view, but the polysilicon gate is indicated by PO. A complete transistor would utilize a PO layer to electrically connect the common gate terminals together and would use metal layer 1. Metal layer 1 is denoted as M1. In the embodiment, metal layer 2 is also used and is denoted as M2, according to the shaded key in Fig. 5, metal layer 2 is shaded to distinguish it from other areas. Each transistor in FIG. 2 is, for example, on a silicon substrate. The active region OD forms the source and drain regions of the MOS transistor. The memory cell transistors PG1, PG2, PU1, PU2, PD1, PD2 are shown in the figure and constitute a 6T SRAM bit cell layout. Read port transistors RPD and RPG are also shown and form the read port circuit of FIG. 2 .

Figure 6 shows a cross-sectional view of line segment 6-6' in Figure 5. The active area OD is separated by an isolation domain, and a gate dielectric layer 61 overlies the active area and underlies the transistor gate polysilicon PO. In the known cross-sectional structure of FIG. 6 , the gate dielectric layer 61 has the same thickness in the reading part and in the 6T memory cell. The formation of the contact layer CO connects the portion M1 of the metal layer 1 to the polysilicon. The metal layers are isolated from each other and also from the polysilicon by spacers formed by one or more interlayer dielectric layers (ILD, not shown). Oxide, nitride, oxynitride, and carbon including interlayer dielectrics can be used here. The metal layers M1 and M2 may be formed of aluminum, aluminum alloy, copper, or copper alloy, etc., using deposition techniques. When copper or copper alloys are used, single damascene or dual damascene and CMP techniques can be used to form the conductors, as is well known in the art. Also in the known technology, liner substances (or so-called BARC and ARC layers) and interlayer dielectrics can be used to form metal layers and spacers.

The read bit line RBL of metal 2 overlays the read port of the 8T bit cell. When configured in such a conventional layout, metal 2, channel (channel V1 on metal 1), portion M1 of metal 1, contact layer CO are required to connect the read bit line RBL to the bit cell.

FIG. 7 shows a plan layout of an 8T bit cell 70 using the technical features of the present invention. FIG. 7 is a plan view showing a non-limiting layout of the circuit embodiment of FIG. 4 . Of course, other layouts can also be used for the circuit, and these varied layouts can be regarded as additional embodiments of the present invention. In FIG. 7, a 6T memory cell 72 is laid out together with an active region formed in the OD layer, and the range of the cell is defined by an isolation field such as STI. The gate of the transistor is formed of polysilicon and overlies a gate dielectric layer (not visible in the figure). The NMOS motor poles PG1 , PD1 , PD2 and PG2 are electrically connected to two PMOS pull-up transistors PU1 and PU2 . The read port 74 of the cell is arranged adjacent to and electrically connected to the 6T cell 72 as shown in the circuit diagram of FIG. 4 . The two NMOS transistors in the read port are the read pull-down transistor RPD and the read pass gate RPG, both of which are NMOS transistors.

In addition to the use of two gate dielectric layers of different thicknesses (the thick gate dielectric layer is used in the read NMOS transistor of the memory cell 72 of 6T, and the thin gate dielectric layer is used in the read NMOS transistor in the read part 74 port NMOS transistors), the cell layout embodiment shown in FIG. 7 also includes an improved read bit line configuration. In this embodiment, read bit line RBL is formed by metal layer 1 (indicated by M1). As will be explained below, by restricting the metallization of the read bit line to only metal 1 connected to the read port of the read cell (like the read conduction gate transistor RPG has only one contact layer and nothing else in between channel), the capacitance and read speed of the read bit line RBL are greatly improved compared with the traditional bit cell layout.

Fig. 8 shows a cross-sectional view of line 8-8' in the layout diagram of Fig. 7 . In FIG. 8, the active region OD is defined by an isolation oxide. Overlying the bit cell region 6T above the active region is a gate dielectric layer 61 having a first thickness. Overlying in the readout portion above the active area is a gate dielectric layer 62 having a second thinner gate thickness. The ratio of the thin gate dielectric layer to the thick gate dielectric layer can vary in many ways and is considered as a different embodiment here. The thin gate thickness may be 0.75-0.99 times the thick gate thickness. Preferably, the ratio is 0.85-0.99, 0.85-0.95, or even 0.85-0.90 times. Other examples may include 0.75-0.95, 0.75-0.90, 0.75-0.80 times. An important advantage of a thin dielectric layer in the read port is to allow the read port transistors to switch at higher speeds and operate at lower Vcc,min. This is more important for the read port of the 8T circuit. The use of a thick dielectric layer in the 6T memory cell portion is important for cell stability and also provides lower standby leakage current Isb for the write portion of the SRAM cell (including the storage node). Combining two NMOS transistors of different dielectric thicknesses in one SRAM bit cell provides significant power saving and performance advantages over the same cell implemented conventionally. In addition, the power supplied to the SRAM cell portion of 6T can operate at a higher Vcc,min level compared to transistors with thin dielectric thickness. Because reading is much more frequent than writing, reading Vcc, min is more important. The higher Vcc, min level supply to the 6T storage array improves the stability and reliability of the storage part of the circuit.

However, the cross-sectional view of FIG. 8 shows the metal 1 read bit line RBL overlying the read portion of the circuit. A single contact layer CO is also located between the metal layer 1 and the polysilicon gate of the read pass transistor RPG.

Another figure better shows the advantages of using a single metal layer to read the bitlines compared to the traditional 8T bitcell layout. FIG. 9 shows a layout cross-section of a conventional metal 2 read bit line, and also shows that the connection to the active area requires the metal 2 read bit line to be electrically connected to the drain terminal of the read conductive gate. In a conventional configuration, the metal 2 read bit line is electrically connected to the metal layer 1 through the channel 1 (the channel on the metal 1). It is then electrically connected to the active region through the contact layer CO, and the active region corresponds to a terminal of the read conduction gate (RPG) transistor. Therefore, the capacitive path includes metal 2, the channel of the V1 layer, metal 1, the contact layer CO, and the contact resistance on the active area OD.

FIG. 10 shows a cross-sectional view of the read bit line structure of the embodiment. In FIG. 10 , the read bit line RBL of the metal layer 1 covers and contacts a single contact layer CO, and the contact layer CO contacts the surface of the active region OD. Therefore, the impedance path only includes the metal 1M1, the single contact layer CO, and the contact impedance on the active area.

FIG. 11 shows the results of an electrical simulation comparison between the connection configuration of the metal 2 read bit line in FIG. 9 formed by a conventional semiconductor process and the embodiment of the metal 1 structure of the present invention (eg, as shown in FIG. 10 ). As shown in FIG. 11 , the structure of the embodiment has a 28% improvement in resistance reduction compared to the conventional method, and has a corresponding increase in read speed.

FIG. 12 shows a layout diagram of an embodiment where four 8T bit cells 70 are arranged together. As shown in FIG. 12 , bit cells 70 can be efficiently packed together by overlapping vertically from left to right and horizontally from top to bottom. This configuration makes the thinner gate dielectric layer device RPD and RPG of each unit in the common area in the center of the array, while the thicker gate dielectric layer device of the 6T memory cell shares the active area OD and is formed in the array. tail end. When performing the process of the dielectric layer deposition step, it is easier to use photomask and photoresist techniques to isolate the blocks. In a simple implementation, the process can first deposit the gate dielectric layer in one area, and then deposit it in another area, thereby forming different thicknesses of the gate dielectric layer.

Also, as another embodiment of the present invention (instead of a thick dielectric layer formed in one portion of the SRAM array, a thin dielectric layer is formed in the read portion of the same array), two different gate dielectric layers can be Use higher and lower dielectric constants. Higher-k dielectric layers can be used for 6T memory cells to provide high stability and low standby leakage current. A lower k dielectric layer can be used in the read portion of the bit cell to provide low Vcc, min and faster read speed. The use of metal 1 read bit data lines in the read portion, coupled with the use of two gate dielectric layers of different thicknesses, results in an embodiment that provides additional performance advantages over conventional techniques.

FIG. 13 shows a layout diagram of an embodiment of a 10T bit cell 60 . In FIG. 13, the configuration of the layout section 64 is similar to that of the aforementioned 6T bit cell. The 10T cell has two read ports, which are located at both ends of the cell, and both are similar to the read ports of the aforementioned 8T bit memory cell. The gate dielectric thickness in portion 62 is thinner than in portion 64, the same as the previous 8T bitcell. Therefore the read transistor has a faster speed and lower Vt than the write transistor.

FIG. 14 shows a layout diagram of a 10T cell corresponding to FIG. 13 using metal 1 ( M1 ). In FIG. 14, it can be seen that metal 1 (M1) read bit lines RBL0 and RBL1 are at both ends of the 10T cell. As mentioned above, by restricting the metal 1 read bit line to the read part so that there is only one contact layer space between it and the cell and no other channels, the capacitance of the read path is reduced and the read time of the SRAM cell is reduced. will also improve.

Figure 15 shows a bit cell configuration that also benefits from the use of embodiments of the present invention. A content addressable memory (CAM) unit 73 is shown in FIG. 15 . The selection of a CAM cell is performed by providing a data word to the memory, and then the memory returns the address where the matching data word was found. The circuit has 6T transistors and is quite similar to a 6T SRAM cell from a transistor and layout standpoint. In FIG. 15, the CAM cell has a pair of complementary select lines SL and SL (which act similarly to the read bit line RBL in the SRAM array), and an output line ML. Two sides of the CAM unit 73 respectively have a pair of inverters, which are formed by two pull-up (PMOS) devices and two pull-down (NMOS) devices, which are connected to maintain the data of the storage node. There is also a read pull-down transistor (NMOS M3 or M4) and a select gate transistor (NMOS M1 or M2) on both sides of the CAM cell 73, respectively. Therefore, those skilled in the art can understand that the CAM cell has the same characteristics as the SRAM 10-bit cell, wherein the storage part is composed of pull-up and pull-down transistors, the two are electrically connected to latch data, and the read part is composed of transistors connected in series 2 NMOS transistors. Because of these similarities, using a thick gate oxide for the memory inverter portion and using a thin gate oxide for transistors M1 , M2 , M3 , M4 will achieve similar advantages to the SRAM bit cell application described above.

FIG. 16 shows an embodiment of the layout of the CAM cell of FIG. 15 using active area OD, polysilicon conductor PO, metal 1M1 and contact layer CO. The gate conductors of the read transistors M1 , M2 , M3 , M4 in FIG. 15 are shown at portion 75 on the right. Like the aforementioned 10T cell and 8T cell, in this embodiment, the transistors in the readout section 75 have a thinner gate dielectric layer or thinner equivalent oxide thickness than the transistors in the readout and store section 71 . The NMOS transistor of the storage portion 71 has a thicker gate dielectric layer, or a thicker equivalent oxide thickness in other embodiments. The advantages of this configuration are equivalent to the advantages of using this configuration for the aforementioned SRAM cells: faster access time, lower standby leakage current, improved Vcc,min.

The above-mentioned embodiments are related to the category of SRAM bit cells using planar MOS transistors. In other embodiments also considered part of the present invention, multiple gate transistors (eg finFETs) may be used in the circuits described above. A three-dimensional structure of finFET device 80 is shown in FIG. 17 . FinFETs are formed on a semiconductor fin that includes source, drain and LDD diffusion regions, thereby forming the channel and source and drain terminals of the MOS device. The gate dielectric layer can be formed on the vertical plane (forming a double gate device) or over the entire exposed fin surface (forming a triple gate device). With the gate width extending over the height or width of the fin, the device can have a large aspect ratio without consuming silicon area. Multiple fin devices can also be formed and connected together, thereby increasing the size of the semiconductor. The gate conductor is generally formed vertically across the fin and covers the gate dielectric layer, thereby completing the gate structure of the MOS device.

In FIG. 18, a cross-sectional view of the finFET of FIG. 17 is shown. The gate (polysilicon or other unknown gate conductor material) has spacer spacers SW. The fin includes source, drain implants and a lightly doped drain diffusion region with silicide over the doped region. It should be noted that when the finFET used has a larger size than the planar transistor of the embodiment per silicon area, the gate dielectric layer can be the same thickness or a different thickness. This is because finFETs have better performance characteristics than planar transistors for the same silicon area.

In FIG. 19, an embodiment of a dual-port 8T bitcell is shown, and the figure shows how finFETs are used to improve the performance characteristics of the bitcell. Layout 90 shows the active area and polysilicon gate of the aforementioned 8T SRAM cell. Area 91 is the storage node and the write part, and area 92 is the read port. In the previous embodiments, the write part of the planar transistor has a thicker gate dielectric layer, and the read part has a thinner gate dielectric layer for fast read time. In this embodiment, read port transistors RPG and RPD form finFET device 95 . In this case, a SRAM bit cell with two different transistor forms can also obtain the advantages of fast read time, low Vcc,min, etc. The planar MOS transistor 93 is used for the storage node transistor and the write part 91, and the finFET transistor 95 is used for the read port of the 8T bit cell.

Of course, this non-limiting embodiment can also be extended and applied to the aforementioned 10T SRAM bit cell and CAM bit cell. FinFET applications can have a uniform gate dielectric thickness and use the same gate dielectric material as planar transistors. The finFETs used in the embodiments are advantageously formed in the SOI layer because the silicon fins extend vertically above the surface and the source and drain regions are formed in the fins themselves.

Still other embodiments include the use of different gate dielectric thicknesses in finFET devices compared to planar MOS devices. Other embodiments include using high-k dielectric constant for either or both planar MOS devices or finFET devices. In addition, finFET devices can be double-gate, triple-gate, or multi-gate, and can include multiple fins (as shown in Figure 19). Of course, a device with a single fin is also regarded as an embodiment of the present invention.

In one embodiment, a device is provided having a semiconductor substrate in which at least one 8T SRAM bit cell has a double gate oxide thickness NMOS transistor and a read port.

In another embodiment, an integrated circuit is provided, comprising: a semiconductor substrate; at least one 8T SRAM bit cell having a double gate oxide thickness NMOS transistor and a read port. This embodiment also provides a layout in which the read bit lines of the read ports are confined to the first level of metallization on the ILD with no other intervening channels. This embodiment thus provides the additional performance advantage of incorporating a dual gate oxide SRAM bitcell.

In another embodiment, an integrated circuit is provided, comprising: a semiconductor substrate; at least one 10T SRAM bit cell having a double gate oxide thickness NMOS transistor and a double read port. The NMOS transistors in the dual read port have an oxide thickness thinner than that of the memory cell transistors.

In another embodiment, a layout diagram includes a 10T SRAM bit cell with dual gate oxide thickness, wherein the read bit line of the dual read port is limited to the metallization of the first layer and the ILD layer with no other intervening channels. This embodiment therefore provides additional performance advantages for SRAM bit cells incorporating dual gate oxide 10T.

In another embodiment, a method is provided, comprising defining an 8T SRAM bit cell layout on a semiconductor substrate; forming a 6T SRAM portion with six transistors in a portion of the SRAM bit cell area, the portion comprising two NMOS conduction gate and two NMOS pull-down transistors; a read port is formed in the read part of the bit cell area, including an NMOS conduction gate and an NMOS pull-down transistor; the gates of the 4 NMOS transistors in the 6T bit cell part are oxidized The layer thickness is thicker than the gate oxide thickness of the two transistors of the read part; and the first metal layer is formed to cover the read bit line and contact the read part without any other channels in between, thereby providing reduced capacitance and Enhanced performance characteristics.

In another embodiment, a method is provided, comprising defining a 10T SRAM bit cell layout on a semiconductor substrate; forming a 6T SRAM memory cell portion having six transistors in a portion of the SRAM bit cell area, the portion comprising Two NMOS conduction gates and two NMOS pull-down transistors; a read port is respectively formed in the first read part and the second read part of the bit cell area, including an NMOS conduction gate and an NMOS pull-down transistor; the 6T bit The thickness of the gate oxide layer of the four NMOS transistors in the unit part is thicker than the thickness of the gate oxide layer of the transistors in the two reading parts; and the first metal layer is respectively formed to cover and contact the two reading parts with the reading bit line covering and contacting the two reading parts. There are no other channels, thereby providing reduced capacitance and improved performance characteristics.

In another embodiment, an SRAM bitcell having two different gate dielectric materials is provided. The memory cell and the write portion in the 8T SRAM bit cell have a first gate dielectric layer (equivalent to a first oxide thickness). The read portion in the SRAM bitcell has a second gate dielectric (equivalent to a thinner second oxide thickness). In another embodiment, the material of one of the gate dielectric layers may be oxide. In another embodiment, the material of one of the gate dielectric layers is a high-k gate dielectric material. In another embodiment, the read bit line is formed in the first metal layer and connected to the read portion of the 8T SRAM cell with only one contact layer without any other channels in between.

In another embodiment, a CAM bit cell having a first storage node portion and a second read portion is provided. In one embodiment of the CAM bitcell, the storage node portion includes a transistor having a first thicker gate dielectric and the read portion includes a transistor having a second thinner gate dielectric. In another embodiment, the read bit line of the CAM bit cell is formed in the first metal layer and connected to the read part through a contact layer without any other channel or other metal layer in between. In another embodiment, the transistors in the read portion of the CAM bitcell are multiple gate transistors. In another embodiment, the transistor of the CAM bit cell has a high-k gate dielectric and other dielectric layers.

In another high-speed bit cell configuration, an 8T SRAM bit cell, a 10T SRAM bit cell or a CAM cell has two parts: a bit cell storage part and a read part. In the storage section, planar CMOS transistors are provided, and in the read section, finFET transistors are provided. The transistors of the read section give the read section the advantage of a higher operating speed. FinFET transistors include (not limited to): double gate, triple gate and multiple gate cells.

In another embodiment, SRAM bit cells (whether 8T, 10T, other or CAM bit cells) are formed on an epitaxial Silicon over insulator (SOI) layer. In this embodiment, the features of any other embodiment can be followed. That is, in one embodiment, an 8T bit cell has a read portion (including a storage node) and a write portion formed in the SOI layer. The transistors of the write portion have a first gate dielectric layer thickness. The transistors of the read portion have a second thinner gate dielectric thickness. In another embodiment, the write portion has a high-k gate dielectric (equivalent to the first oxide thickness), and the read portion has a high-k gate dielectric (etc. effect on the second oxide layer thickness, which is thinner than the first oxide layer thickness), in another embodiment, the read portion has an oxide dielectric layer and the write portion has a high-k dielectric constant gate dielectric layer, and vice versa The same is true. In another embodiment, the gate dielectrics of the write portion and the read portion may have the same thickness but be formed of different materials. In another embodiment, the write portion has a first transistor form and the read portion has a second transistor form. In this non-limiting example of an SOI cell, the second transistor form may be a finFET transistor.

Although the embodiments of the present invention and their advantages have been described in detail, various changes, substitutions and changes are possible without departing from the spirit and scope of the present invention as defined in the claims. For example, those skilled in the art can easily understand that there are many variations within the scope of the present invention.

Furthermore, the viewpoint of application of the present invention is not limited to the specific method or step embodiments described in the specification. Anyone skilled in the art can understand the current or future developed processes and steps from the disclosure of the present invention, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can all be used in the present invention . Therefore, the protection scope of the present invention includes the above-mentioned processes and steps.

Claims (10)

1. the device of a SRAM bit location comprises:

The semiconductor substrate; And

At least one SRAM bit location is formed at a part of described semiconductor substrate;

Wherein said at least one SRAM bit location also comprises the transistor that possesses the first grid medium thickness, with the extra transistor that possesses thin second grid medium thickness, described thin second grid medium thickness is between the 75%-99% of described first grid medium thickness.

2. the device of SRAM bit location as claimed in claim 1, wherein said thin second grid medium thickness is between the 85%-95% of described first grid medium thickness.

3. the device of SRAM bit location as claimed in claim 1, wherein said thin second grid medium thickness is between the 85%-90% of described first grid medium thickness.

4. the device of SRAM bit location as claimed in claim 1, wherein said at least one SRAM bit location comprises a 6T memory cell, formed by nmos pass transistor with described first grid medium thickness, the device of described SRAM bit location also comprises a read port, is formed by having the described nmos pass transistor of thin second grid medium thickness.

5. the device of SRAM bit location as claimed in claim 1, SRAM bit location that wherein said SRAM bit location is 8T and the SRAM bit location of 10T one of them.

6. the device of SRAM bit location as claimed in claim 4 also comprises:

First and second metal level is deposited on described substrate and is separated by the interlayer dielectric layer, with at least some described transistor electrically connects of described SRAM bit location together; And

One reading bit line, do not cover described substrate with described the first metal layer formation and not see through other metal levels, described reading bit line is used a contact layer and is not had to see through the described read port that other any metal level raceway grooves are connected to described SRAM bit location.

7. the device of SRAM bit location as claimed in claim 4, SRAM bit location that wherein said SRAM bit location is 8T and the SRAM bit location of 10T one of them,

Described read port comprises at least one finFET transistor.

8. the integrated circuit of a SRAM bit location comprises:

One logical gate is formed at the first of semiconductor substrate, and possesses a plurality of transistors, and described transistorized some of them have thin gate dielectric;

One SRAM array possesses a plurality of SRAM bit locations, and each SRAM bit location is formed on the second portion of described semiconductor substrate, and described SRAM bit location also comprises:

The 6T memory cell is made up of the nmos pass transistor with described thicker gate dielectric layer thickness;

One read port is formed by having the described nmos pass transistor of thin gate dielectric layer thickness;

Wherein said thin gate dielectric layer thickness is between the 75%-99% of described thicker gate dielectric layer thickness;

First and second metal level is deposited on described substrate and is separated by the interlayer dielectric layer, with at least some described transistor electrically connects of described SRAM bit location together; And

One reading bit line, do not cover described substrate with described the first metal layer formation and not see through other metal levels, described reading bit line is used a contact layer and is not had to see through the described read port that other any metal level raceway grooves are connected to described SRAM bit location.

9. the device of a CAM bit location comprises:

The semiconductor substrate; And

At least one CAM bit location is formed at a part of described semiconductor substrate;

Wherein said at least one CAM bit location also comprises the transistor that possesses the first grid medium thickness, with the extra transistor that possesses thin second grid medium thickness, described thin second grid medium thickness is between the 75%-99% of described first grid medium thickness.

10. the device of CAM bit location as claimed in claim 9 comprises also that comprising the described part of the described semiconductor substrate of described at least one CAM bit location insulator covers silicon layer.

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