CN102024819A - Apparatus for providing SRAM and CAM bit cell - Google Patents
Apparatus for providing SRAM and CAM bit cell Download PDFInfo
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- CN102024819A CN102024819A CN 201010288041 CN201010288041A CN102024819A CN 102024819 A CN102024819 A CN 102024819A CN 201010288041 CN201010288041 CN 201010288041 CN 201010288041 A CN201010288041 A CN 201010288041A CN 102024819 A CN102024819 A CN 102024819A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Abstract
The invention provides circuits and methods for providing an SRAM and CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.
Description
Technical field
The present invention relates to static RAM (Static Random Access Memory, SRAM) determined bit position structure and the method that the bit location of the standby leakage current (Isb) with improvement is provided, with the standby action that is improved, the Vcc that improves, the supply level of min, reduction has minimum power, high speed time for reading.
Bit location comprises a new layout and the multiple thickness grid oxic horizon in the cell transistor.Purposes of the present invention provides the advantage that SRAM is used in the integrated circuit of the circuit that possesses logical circuit or user's appointment.Except the SRAM array of SRAM bit location, sram cell also possesses the stability of improvement and provides in the situation that operates in reliably widely.Making comprises that the method for the SRAM bit location of feature of the present invention can be compatible to the existing technology status and the semiconductor technology of plan.
Background technology
Generally to the demand of electronic circuit, particularly being made as the demand of the electronic circuit of integrated circuit in the semiconductor technology now, is on the substrate or built-in memory storage element arrays.These elements can be dynamic random access memory (DRAM) unit, also can be static RAM (SRAM) unit.DRAM and SRAM memory are called volatile memory unit, if wherein remove the power supply of supply integrated circuit, the data of storage will disappear.The DRAM unit can provide the array of very dense, because the DRAM unit only needs single access transistor and storage capacitance.Yet the DRAM circuit has relatively slow reading and the write time, and needs complicated control circuit.Each DRAM unit is stored data to charge in the mode of drain capacitance, so the DRAM array must be updated periodically the state of keeping.This needs processor periodically to stop other computings to carry out and upgrade circulation, or special-purpose memory controller (more often being used in the device of present production) is carried out and upgraded circulation.The SRAM array needs more silicon area, because each bit location is generally by 6 or the phase locking unit formed of multiple transistor more.Yet as long as supply voltage exists, sram cell will keep data.Further advantages are that the access time of sram cell is fast compared with the DRAM unit, make that sram cell (as memory cache of processor) in the storage of temporary or operational data is attractive especially.One or more cores are incorporated in nearest chip system (SOC) design usually into.These cores are the processor (as DSPs, ARMs, RISC or microprocessor) of flow process of design in advance normally, with this processor in abutting connection with or disposed the 1st grade of (L1) memory cache of a sram cell nearby, make that calculation process speed can be faster.
The situation that integrated circuit is used in battery powered device day by day improves.For example, SOC may be used to provide all or major part is used for realizing mobile phone, laptop computer, notebook computer, audio and video player, take the photograph the circuit of video recorder, camera, intelligent telephone or PDA major function.In these devices, the processor core design of the logic OR permission of client definition can combine to other unit (as microprocessor, numerical digit signal processor, core (as ARM, RISC or similar Core Feature), mobile telephone module etc.) predetermined or huge collection.
In the SRAM bit location, data can be stored in the memory node of two inversely relateds.A pair of CMOS inverter (being made up of four MOS transistor) is configured to fasten lock unit as one.In complementary MOS (CMOS) technology, each memory node is that the gate terminal by two MOS transistor is formed, and receives the output of the inverter of being made up of two MOS transistor.
Fig. 1 shows the SRAM bit location 10 of a typical 6T configuration.In Fig. 1, a pair of MOS conduction grid PG1, PG2 electrically connect pair of data lines (being also referred to as bit line BL and BLB) respectively to storing contact SN1 and SN2.Conduction grid PG1 and PG2 generally are made up of nmos pass transistor in known technology.Show a positive supply voltage Vdd among the figure, its scope 0.6 volt to 3.0 volts or higher, mainly decide on technology.Pull up transistor PU1 and PU2 is made up of the PMOS transistor, and positive supply voltage can be electrically connected to one or another memory node, decides according to the state of sram cell 10.Also show one the 2nd supply voltage Vss, normally ground connection among the figure.
Two pull-down transistor PD1 and PD2 (also being nmos pass transistor) will bear or earthed voltage Vss is electrically connected to one or another memory node SN1 and SN2, decides according to the state of bit location.Bit location is a phase locking unit, as long as power supply is enough to function circuit correctly, data mode was preserved on ground when this phase locking unit meeting was unlimited.Formed the coupling interlaced with each other of CMOS inverter by PU1, PD1 and PU2, PD2 respectively for two, and their operation is used for strengthening continuously the electric charge that is stored in memory node SN1 and SN2.Show inverting each other among two memory nodes such as the figure.When SN1 is logic state 1 (being generally high potential), SN2 can be logic state 0 (normally electronegative potential) at one time, and vice versa.
When SRAM bit location 10 is written into, complementary write data and can distinguish input bit line BL and BLB.Character line WL goes up the grid that positive control signal can be electrically connected to two conduction grid PG1 and PG2.The ordered size of transistor PU1, PD1 and PU2, PD2 can make the data on the bit line override the data of storage, writes whereby in the SRAM bit location 10.
When SRAM bit location 10 is read, positive voltage puts on character line WL, and conduction grid PG1 is with PG2 permission bit line BL and BLB is electrically connected to memory node SN1 and SN2 receives data.Be different from the dynamic memory unit, if power supply supply Vdd maintains under enough high level, the SRAM bit location can not be lost the state of its storage during reading.Therefore just do not need to write back the action of (write back) after reading release.
It is right that bit line BL and BLB constitute the data wire of a pair of complementation.These two paired data wires can be electrically connected to a differential induction amplifier (not being shown among the figure), and differential voltage can be sensed and be amplified, and this is the known designs of those skilled in the art of the present technique.This had both amplified and the output signal responded to can be as the output of data other logical circuit in this device.
Fig. 2 shows traditional SRAM bit location 12 of another kind of form, has wherein used the additional function that disposes of 8 transistors (8T) and read port 14.In Fig. 2, has the unit 10 of 6T shown in Figure 1.SRAM bit location 12 has a read port 14 of being made up of two nmos pass transistors in addition, and these two transistors are respectively read port pulldown transistor RPD and read port conduction gate transistor RPG.This read port 14 also has one only for reading with reading character line RWL.Previous character line WL in Fig. 1 only writes character line WWL for what write.The benefit that read port is separated is to have lowered the probability that reads interference because be stored in the data of bit location can be read the action influence.Relatively, reading pull-down transistor RPD can come conducting or end according to the memory node SN2 that is electrically connected to its grid.Because nmos pass transistor has gain, the data-signal that is stored in node SN2 can be amplified by the gain of transistor RPD.Therefore when reading character line RWL and be applied in positive voltage, read that conduction grid RPG understands conducting and reading bit line RBL is electrically connected to and read pull-down transistor, so read port can be exported the data bit of a correspondence on reading bit line RBL.In the middle of many application, the SRAM array of many bit locations is used to recovery of stomge and uses and data or the formula used after a while.Sram cell experienced in the same time, and to read the action meeting more than write activity.Therefore seeing through read port 14, will to read that action separates with bit location be quite helpful, finishes even if the unit of 8T will use more silicon cloth situation to amass.In addition, when attempt saving electric power (Vdd), minimum feature measurement becomes even more important to reading circuit, because that is the part of Chang Zuodong in the circuit.
Fig. 3 shows another kind of known SRAM bit location 20, has wherein used 10 transistors (10T).In this configuration, circuit possesses two read ports, is electrically connected to the memory node SN1 and the SN2 of 6T unit 10 respectively.Read port 22 and 24 has control line RWL1 and RWL2 and pull-down NMOS transistor AND gate conduction grid nmos pass transistor separately respectively.Article two, reading bit line RBL1 and RBL2 see through conduction grid RPG1 and RPG2 respectively and are electrically connected to pull-down transistor RPD1 and RPD2.Pull-down transistor has a grid that is connected to memory node SN1 and SN2 respectively.Reading action can independently or side by side carry out.Use two read ports that additional elasticity is provided and two outputs are read out from the unit simultaneously.
Because continuing and increase (particularly more complicated battery powered carrying device) of low power consumption integrated circuit demand, sram cell need have good electricity-saving characteristic.One of the method for limiting of power consumption must lean on standby leakage current (after this representing with Isb).When sram cell does not use, the SRAM array can be in standby mode.Leakage current Isb during standby must be reduced.In technique known, the method that the power consumption of cmos circuit is lowered in the positive supply supply when reducing standby mode is as much as possible widely known.With the metric system that decides the Vcc level is Vcc, min.Provide one to possess low Vcc, the sram cell of min value is clearly favourable.And this is difficult to go effectively to implement for the 6T memory cell, this be because plant bulk dwindle and the process variations that progress caused and other restrictions of technology cumulative.
Yet above-mentioned circuit still has the outstanding time (reading speed) and can not produce to read and disturbs wrong and operation effectively.Last characteristic can be called the stability of circuit.A method of keeping stability is to reduce the Vcc that is applied to the SRAM memory cell, min.And along with the progress of semiconductor technology, plant bulk continues to dwindle.The use of littler device causes the performance of device that great amplitude of fluctuation is arranged.In order to keep the operating reliability of these devices, a lower Vcc must be arranged, min.Though reduce Vcc, min is a good method that reduces power consumption, reduces Vcc, and min also is necessary to the SRAM array.
Therefore, we need the SRAM determined bit position structure of an improvement, this structure has the Vcc of low standby leakage current Isb, improvement, min in order to reduce standby power consumption, with the access speed of improving (when particularly reading action), keep the compatibility that known semiconductor process techniques is used for making integrated circuit simultaneously, and do not increase tangible step and cost.
Summary of the invention
These or other problems are roughly solved or are avoided, and have reached technical advantages by embodiments of the invention.The invention provides a kind of SRAM bit location and possess thicker grid oxic horizon, possess thin grid oxic horizon at the read port transistor at memory cell transistor.Thick grid oxic horizon is used in memory cell transistor stable data storage and lower standby current is provided.Thin grid oxide layer is used in the read port transistor the fast time for reading Vcc lower with permission, min is provided.The electric power that is supplied to read port can be electrically connected to the logical gate of device, and the electric power that is supplied to memory cell transistor simultaneously can be than the higher reliability of improving.This method is to be used for forming sram cell and its processing step with double gate oxidated layer thickness can be compatible to the existing steps flow chart that semiconductor is made that is used for.
In one embodiment, a kind of device of SRAM bit location comprises: the semiconductor substrate; And at least one SRAM bit location, be formed at a part of above-mentioned semiconductor substrate.Wherein above-mentioned at least one SRAM bit location also comprises the transistor that possesses the first grid medium thickness, with the extra transistor that possesses thin second grid medium thickness, above-mentioned thin second grid medium thickness is between the 75%-99% of above-mentioned first grid medium thickness.
In another embodiment, a kind of integrated circuit of SRAM bit location comprises: a logical gate, and be formed at the first of semiconductor substrate, and possess a plurality of plural transistors, above-mentioned transistorized some of them have thin gate dielectric; With a SRAM array.Wherein the SRAM array comprises a plurality of SRAM bit locations, and each SRAM bit location is formed on the second portion of semiconductor substrate.The SRAM bit location also comprises the transistor that possesses thicker gate dielectric layer thickness, and with the extra transistor that possesses thin second grid medium thickness, above-mentioned extra transistor is electrically connected to the transistor that possesses thicker gate dielectric layer thickness.Above-mentioned thin second grid medium thickness is between the 75%-99% of above-mentioned first grid medium thickness.
In another embodiment, a kind of device of CAM bit location comprises: the semiconductor substrate; And at least one CAM bit location, be formed at a part of above-mentioned semiconductor substrate.Wherein above-mentioned at least one CAM bit location also comprises the transistor that possesses the first grid medium thickness, with the extra transistor that possesses thin second grid medium thickness, above-mentioned thin second grid medium thickness is between the 75%-99% of above-mentioned first grid medium thickness.
SRAM determined bit position structure of the present invention has the Vcc of low standby leakage current Isb, improvement, min in order to reduce standby power consumption, with the access speed of improving (when particularly reading action), keep the compatibility that known semiconductor process techniques is used for making integrated circuit simultaneously, and do not increase tangible step and cost.
Content description of the present invention the embodiment of the present invention part, and non-limiting the present invention.Other additional features of the present invention and advantage will be in illustrating that after this content of this explanation constitutes the target of the application's claim.The viewpoint that those skilled in the art can understand the application and embodiment can revise or design other structures or technology is implemented the identical purpose with the application as the basis.Therefore know this skill personage and should be able to understand similar structure and do not take off and carry spirit of the present invention and category, category of the present invention will be defined by claim described later.
Description of drawings
Fig. 1 shows the SRAM bit cell circuit of a known technology.
Fig. 2 shows the SRAM bit cell circuit of the 8T of a known technology.
Fig. 3 shows the SRAM bit cell circuit of the 10T of a known technology.
Fig. 4 is one embodiment of the invention, shows a circuit diagram that has comprised the 8T SRAM bit location of feature of the present invention.
Fig. 5 shows the plane figure of the SRAM bit location of a 8T who uses traditional gate dielectric.
Fig. 6 shows the profile of taking from Fig. 5 plane figure.
Fig. 7 shows the plane figure of the SRAM bit location of a 8T who uses bigrid dielectric layer of the present invention.
Fig. 8 shows the profile of the plane figure of taking from Fig. 7 embodiment.
Fig. 9 shows that the reading bit line of using the traditional circuit metallization technology connects the profile of configuration.
Figure 10 shows the profile of the reading bit line structure of the embodiment of the invention.
Figure 11 shows that one electrically simulates result relatively, and this comparison other is the traditional reading bit line metallization of Fig. 9 and the embodiment of the invention of Figure 10.
Figure 12 shows the layout of the bit location of 4 8T of embodiment of the invention configuration.
Figure 13 shows the 10T bit location layout of the embodiment of the invention.
Figure 14 shows that use metal 1 is in the layout of the embodiment of Figure 13.
The circuit diagram of Figure 15 displaying contents addressing memory bit location.
Figure 16 shows the figure of CAM cell layout of the embodiment of the invention.
Figure 17 shows the three-dimensional structure of a finFET transistor unit.
Figure 18 shows the profile of the finFET of Figure 17.
Figure 19 has shown that the SRAM bit location of dual-port 8T has possessed the embodiment that uses the transistorized reading section of finFET and use another part of planar transistor.
Of the present invention graphic be not to be used for limiting, but with the case representation various embodiments of the present invention.Each graphic simplification is for convenience of description, therefore not according to actual ratio.
Wherein, description of reference numerals is as follows:
10,20,42, the SRAM bit location of 72～6T;
12,40, the SRAM bit location of 70～8T;
14,22,24,44,74～read port;
20, the SRAM bit location of 60～10T;
61,62～gate dielectric;
73～CAM unit;
91～write part;
92～reading section;
93～plane MOS form transistor;
95～finFET transistor;
PU1, PU2～pull up transistor;
PD1, PD2～pull-down transistor;
PG1, PG2～MOS conducts grid;
BL, BLB, WBL, WBLB～bit line;
WL, WWL～character line;
RBL～reading bit line;
RWL～read character line;
RPG, RPG1, RPG2～read port conduction gate transistor;
RPD, RPD1, RPD2～read port pulldown transistor;
SN1, SN2～memory node;
OD～active area;
PO～polysilicon gate;
M1～metal 1;
M2～only belong to 2;
V1～raceway groove;
CO～contact layer.
Embodiment
The making of preferred embodiment of the present invention and using method will details are as follows.Many invention application concepts provided by the present invention can be implemented on kind widely in the certain content.Specific embodiment discussed below only is to describe to make the unrestricted category of the present invention with using ad hoc approach of the present invention.
Fig. 4 is one embodiment of the invention, shows the circuit diagram of a 8T SRAM bit location 40, has wherein comprised the feature of double gate oxide layer of the present invention.6T memory cell part 42 possesses 2 PMOS as shown in Figure 1-Figure 3 pull up transistor PU1 and PU2 and 4 nmos pass transistor PG1, PG2, PD1 and PD2 as shown in Figure 1-Figure 3 in Fig. 4.In this invention, thick gate dielectric is used to form this four NMOS transistors.By the use of thick gate dielectric, the standby current Isb of SRAM memory cell part 42 descends and stability promotes.As for the read port part 44 of 8T SRAM bit location, then adopt thin gate oxidation dielectric layer on the contrary.Thin gate dielectric can make and read very fast and lower Vcc, min are arranged.In fact possess in the logic core integrated circuit partly at one, the thin gate dielectric and the electric power of this logical gate can be produced and use to reading section 44 with this logical gate.Therefore NMOS read port transistor RPG has faster with RPD that the reaction time makes read cycle very fast, and allows lower Vcc, min to make power consumption reduction when reading action.
Gate dielectric can be that silicon oxide layer, silicon dioxide, silicon nitride, silicon oxynitrides known to the conventional well known technology and other comprise the dielectric of silicon.The gate dielectric of high k value may be used, and for example in some embodiments of the invention, dielectric comprises that the hafnium, the zirconium that possess or do not possess silicate and oxygen can be used.The thick gate dielectric layer thickness ratio of the thin gate dielectric layer thickness of memory cell part 42 and reading section 44 can be at 0.75-0.99, and preferable selection is 0.85-0.95, and best choice is 0.85-0.90.In a hard-core example, how thick gate dielectric is formed by silicon dioxide in the semiconductor technology of rice 45.2.43 how the gate dielectric layer thickness of rice is formed by thermal oxidation.But the present invention be applied to any semiconductor technology and help now with planning in 45 rice, 28 rice, 22 technologies of rice even smaller szie how how how.
In the embodiment of SRAM bit location, the layout of SRAM bit location also can change for the advantage that further reaches double gate oxidated layer thickness of the present invention.
In order to describe these advantages, show that at first a tradition has the bit location of single gate dielectric layer thickness.Fig. 5 shows the plane figure of a SRAM 8T bit location 40, and it possesses gate dielectric layer thickness is definite value.Among Fig. 5, active area represents that with OD this active area is formed between the isolation field (for example shallow-layer trench isolation STI or LOCOS isolate).As well-known to those skilled in the art, active area comprises the diffusion region, and it extends to semiconductor substrate and can mix and forms N or P V-neck V territory and lightly doped drain electrode field, forms source electrode or drain electrode field and active area also can comprise additional transplanting.Active area can be positioned at the surface of semiconductor crystal wafer or being positioned at extension is formed in the middle of the silicon layer on the insulator (SOI).Transistor is formed in the bit location zone, and it uses the grid conductor that deposits or be patterned on the dielectric material (being covered on the active area) to form.Gate dielectric can't be seen in this plane graph, but polysilicon gate can be represented with PO.Complete transistor can utilize the PO layer that the common grid terminal is electrically connected, and can use metal level 1.Metal level 1 is denoted as M1.In an embodiment, metal level 2 also is used and is denoted as M2, and according to the shade key among Fig. 5, metal level 2 uses shade and other zone differences.Each transistor is for example on silicon substrate among Fig. 2.Active area OD forms the source electrode and the drain electrode field of MOS transistor.Memory cell transistor PG1, PG2, PU1, PU2, PD1, PD2 are shown among the figure and form the SRAM bit location layout of 6T.Read port transistor RPD and RPG also are shown among the figure and form the read port circuit of Fig. 2.
The profile of 6-6 ' line segment in Fig. 6 displayed map 5.Active area OD is separated by the isolation field, and gate dielectric 61 covers on the active area and is positioned under the transistor gate polysilicon PO.In the profile construction of known Fig. 6, gate dielectric 61 all is identical thickness in reading section with memory cell at 6T.The formation of contact layer CO is connected to polysilicon with the part M1 of metal level 1.Metal level is isolated from each other through the formed slider of one or more interlayer dielectric layers (ILD shows) and also isolates with polysilicon.Oxide, nitride, nitrogen oxide and comprise that the carbon of interlayer dielectric can be used in this.Metal level M1 and M2 can use deposition technique to be formed by aluminium, aluminium alloy, copper or copper alloy etc.When using copper or copper alloy, known as known technology, singly inlay or dual damascene and CMP technology can be used for forming conductor.In known technology, dielectric medium can be used for forming a metal level and a separator between liner material (or so-called BARC and ARC layer) and multilayer equally.
The reading bit line RBL of metal 2 covers on the read port of 8T bit location.When with such conventional in layout configuration, need part M1, the contact layer CO of metal 2, raceway groove (the raceway groove V1 on the metal 1), metal 1 that reading bit line RBL is connected to bit location.
Fig. 7 shows the plane figure of the bit location 70 of a 8T who uses the technology of the present invention feature.The plane graph of Fig. 7 is an infinite layout type of the circuit embodiments of displayed map 4.This circuit also can use other layout type certainly, and the layout of these variations all can be considered the embodiment that the present invention adds.Among Fig. 7, the active area layout of the memory cell 72 of 6T in being formed at the OD layer, the scope of unit is defined by isolation field such as STI.Transistorized grid forms and covers on the gate dielectric with polysilicon (can't be found out among the figure).The NMOS motor is endured PG1, PD1, PD2 and PG2 and is electrically connected to two PMOS pull up transistor PU1 and PU2.The configuration of the read port 74 of unit in abutting connection be electrically connected to 6T unit 72, as the circuit diagram of Fig. 4.Two nmos pass transistors in the read port are respectively to read pull-down transistor RPD and read conduction grid RPG, and both are all nmos pass transistor.
(thick gate dielectric is used in the memory cell 72 of 6T and reads in the nmos pass transistor except the use of the gate dielectric of two different-thickness, the read port nmos pass transistor that thin gate dielectric is used in the reading section 74 is interior), the embodiment of cell layout shown in Figure 7 has also comprised the reading bit line structure that improves.In this embodiment, reading bit line RBL is formed by metal level 1 (representing with M1).As following explanation soon, metallization by the restriction reading bit line, make its read port that only is metal 1 is connected to reading unit (have only a contact layer as reading conduction gate transistor RPG, do not have other intervenient raceway grooves), the electric capacity of reading bit line RBL and reading speed have improvement significantly compared with the layout of traditional bit unit.
The profile of 8-8 ' line segment in the layout of Fig. 8 displayed map 7.Among Fig. 8, active area OD is defined by isolation oxide.Cover in the bit location zone of active area top 6T is the gate dielectric 61 with the 1st thickness.Covering in the reading section of active area top is gate dielectric 62, has the 2nd thin gate.The ratio of thin gate dielectric and thick gate dielectric can have a variety of variations, is considered as different embodiment at this.Thin gate can be a 0.75-0.99 thick gate doubly.Preferably this ratio be 0.85-0.99,0.85-0.95 or even 0.85-0.90 doubly.Other example can comprise 0.75-0.95,0.75-0.90,0.75-0.80 doubly.The significant advantage of thin dielectric layer is to allow the read port transistor to switch with higher speed in the read port, and with lower Vcc, the min operation.This read port for the 8T circuit is even more important.Thick dielectric layer is used in the 6T memory cell part quite important, and also provides the low standby leakage current Isb that writes part of sram cell (comprising memory node) the stability of unit.With respect to the practiced same unit of conventional method, in conjunction with the nmos pass transistor of two different dielectric layer thicknesses in a SRAM bit location provide tangible power saving with performance on advantage.In addition, compared to the transistor of thin dielectric layer thickness, the electric power that is supplied to the sram cell part of 6T can operate in higher Vcc, the min level.Because it is frequent more many than writing to read action, read Vcc, min is even more important.Higher Vcc, min level are supplied to stability and the reliability that the 6T storage array has improved the circuitry stores part.
And the profile of Fig. 8 shows that metal 1 reading bit line RBL covers on the reading section of circuit.Single contact layer CO is also at metal level 1 and read between the polysilicon gate of conduction transistor RPG.
An other figure demonstrates better and uses the advantage of single metal level reading bit line compared with the bit location layout of traditional 8T.Fig. 9 has shown the layout profile of conventional metals 2 reading bit line, and has shown that also being connected to active area need be electrically connected to metal 2 reading bit line the drain terminal that reads the conduction grid.Metal 2 reading bit line see through raceway groove 1 (raceway groove on the metal 1) and are electrically connected to metal level 1 in traditional configuration.Then see through contact layer CO and be electrically connected to active area, this active area correspondence reads the transistorized terminal of conduction grid (RPG).Therefore, capacitance path comprise metal 2, V1 layer raceway groove, metal 1, contact layer CO, with active area OD on contact impedance.
Figure 10 shows the profile of the reading bit line structure of embodiment.Among Figure 10, metal level 1 reading bit line RBL covers and contacts single contact layer CO, the surface of contact layer CO contact active area OD.Therefore, impedance path include only metal 1M1, single contact layer CO, with active area on contact impedance.
Figure 11 shows that one electrically simulates result relatively, and this comparison other is that conventional semiconductor processing forms the connection configuration of Fig. 9 metal 2 reading bit line and the embodiment (for example shown in Figure 10) of metal of the present invention 1 structure.As shown in figure 11, the structure of embodiment has 28% improvement with respect to conventional method in the attenuating of resistance, and the increase of corresponding reading speed is arranged.
Figure 12 shows the layout of the embodiment that the bit location 70 with 4 8T fits together.As shown in figure 12, bit location 70 can see through by left-to-right and vertically overlappingly and flatly overlapping from top to bottom effectively be packaged together.This configuration makes the common zone that gate dielectric bed device RPD that each unit is thin and RPG are in array central authorities, and the shared active area OD of thicker gate dielectric bed device of the memory cell of 6T and be formed on the tail end of array.When carrying out the technology of dielectric layer deposition step, using photomask and photoresist technology to isolate block is easy method.In a simple method carried out therewith, technology can deposit gate dielectric earlier in a zone, and then is deposited on the another one zone, forms different gate dielectric layer thickness whereby.
In addition, as another embodiment of the present invention (replace the part that thick dielectric layer is formed at the SRAM array, thin dielectric layer is formed at the reading section of identical array), two different gate dielectrics can use higher and lower dielectric constant.The memory cell that the dielectric layer of high dielectric constant can be used for 6T provides high stability and low standby leakage current.The reading part that can be used for bit location than the dielectric layer of low-k assigns to provide low Vcc, min and reading speed faster.Use metal 1 to read position datawire, add the gate dielectric that uses two different-thickness, formed the embodiment that additional performance advantages can be provided for conventional art in reading section.
Figure 13 shows the embodiment layout of 10T bit location 60.In Figure 13, the structure of layout part 64 is similar to the structure of aforementioned 6T bit location.The unit of 10T has two read ports, and both lay respectively at the two ends of unit, and both are all similar to the read port of the position memory cell of aforesaid 8T.Gate dielectric layer thickness in part 62 is thin than the gate dielectric layer thickness in the part 64, and is identical with the bit location of previous 8T.Therefore read transistor and have fast speeds and lower Vt compared with writing transistor.
Figure 14 shows that use metal 1 (M1) is in the layout of the 10T unit of corresponding Figure 13.Among Figure 14, can see metal 1 (M1) reading bit line RBL0 and RBL1 two ends in the 10T unit.As mentioned above, by to reading section restriction metal 1 reading bit line, making only has a contact layer at interval and do not have other raceway grooves between itself and the unit, and the electric capacity of read path can reduce, and the time for reading of sram cell also can be improved.
Figure 15 shows the configuration of a bit location, and the use of the embodiment of the invention is also benefited from this configuration.(content addressable memory, CAM) unit 73 is shown among Figure 15 content-addressed storage.The selection of CAM unit is by providing the data character to memory, following the memory answer and find the address of paired data character to carry out.This circuit has the transistor of 6T, and is from the viewpoint of transistor AND gate layout, quite similar to the sram cell of 6T.In Figure 15, the CAM unit has the selection wire SL and the SL (its action is similar to the reading bit line RBL in the SRAM array) of a pair of complementation, with an output line ML.The both sides of CAM unit 73 have a pair of reverser respectively, draw (PMOS) device and two drop-down (NMOS) device to form on two, and its connection is used for keeping the data of memory node.The both sides of CAM unit 73 also have one to read pull-down transistor (NMOS M3 or M4) and a selection gridistor (NMOS M1 or M2) respectively.Therefore, those skilled in the art can understand the CAM unit to have and the identical feature of SRAM 10 bit locations, wherein storage area by on draw with pull-down transistor and form, both come latch data at electric connection, and reading section comprises 2 nmos pass transistors that are cascaded.Because these similitudes, use thick grid oxic horizon in storage reverser part and use thin grid oxic horizon in transistor M1, M2, M3, M4, can obtain advantage with the applications similar of above-mentioned SRAM bit location.
Figure 16 shows that use active area OD, polysilicon conductor PO, metal 1M1 and contact layer CO are in the layout embodiment of the CAM unit of Figure 15.The grid conductor that reads transistor M1, M2, M3, M4 among Figure 15 is presented at the part 75 on right side.As aforementioned 10T unit and 8T unit, in this embodiment, with respect to the transistor that reads with storage area 71, the transistor of reading section 75 possesses thin gate dielectric or thin equivalent oxide thickness.The nmos pass transistor of storage area 71 possesses thicker gate dielectric, or possesses thicker equivalent oxide thickness in other embodiment.The advantage of this configuration is equivalent to the advantage that aforementioned sram cell uses this configuration: comparatively fast get the Vcc of time, low standby leakage current, improvement, min.
The above embodiments are to be related to the category that the SRAM bit location uses the plane MOS transistor.In the middle of other also were considered as the embodiment of a part of the present invention, multiple grid transistor (as finFET) can be used in the middle of the foregoing circuit.The finFET device 80 of a three-dimensional structure is shown in Figure 17.FinFET is formed on the semiconductor fin (fin), and this fin comprises source electrode, drain electrode and LDD diffusion region, forms the raceway groove of mos device and source electrode, drain terminal whereby.Gate dielectric can be formed on the vertical plane (formation double gate device) or on the fin surface of whole exposure (forming triple gate devices).Grid width on height that extends in fin or the width, this device can have bigger breadth length ratio, and the area of consume silicon not.A plurality of fin apparatus also can form and link together, and increases semi-conductive size whereby.Grid conductor generally forms in mode vertical and that streak fin, and covers on the gate dielectric, finishes the grid structure of mos device whereby.
Among Figure 18, shown the profile of the finFET of Figure 17.Grid (polysilicon or other unknown gate conductor materials) possesses slider side wall SW.Fin comprises the injection and the lightly doped drain diffusion regions of source electrode, drain electrode, and has silicide above doped region.Be noted that working as the employed finFET of each silicon area has the size bigger than the planar transistor of embodiment, gate dielectric can be same thickness or different-thickness.This is that the performance characteristic of finFET is run well than flat crystal because under identical silicon area.
In Figure 19, shown the embodiment of dual-port 8T bit location, and how expression is used for finFET to improve the performance characteristic of bit location among this figure.Layout 90 has shown the active area and the polysilicon gate of the sram cell of aforementioned 8T.Zone 91 is memory nodes and writes part that zone 92 is read ports.Embodiment formerly, the planar transistor that writes part possesses thicker gate dielectric, and reading section then is to obtain quick time for reading than thin gate dielectric.In the present embodiment, read port transistor RPG and RPD form finFET device 95.Under this situation, a SRAM bit location has two kinds of different crystal form of tubes also can obtain quick time for reading, low Vcc, advantages such as min.Its midplane MOS form transistor 93 is used in the memory node transistor AND gate and writes part 91, and finFET transistor 95 is used in the read port of 8T bit location.
Certainly this infinite embodiment also can extend in the SRAM bit location and CAM bit location that is applied to aforesaid 10T.The application of finFET can possess uniform gate dielectric layer thickness and use identical grid dielectric material as planar transistor.And the finFET that uses among the embodiment can be comparatively favourable when being formed in the soi layer, because silicon fin can extend vertically that the surface is gone up and source electrode and drain region can be formed at fin itself.
Other embodiment comprises the different gate dielectric layer thickness situation of (compared to the plane mos device) in the middle of the finFET device of using in addition.Other embodiment comprises and uses high k dielectric coefficient in plane mos device or finFET device both or one of them.In addition, the finFET device can be double gate, triple grid or multiple grid, and can comprise a plurality of fins (as shown in figure 19).The device of certain single fin also is considered as one embodiment of the present of invention.
In one embodiment, propose a device that possesses semiconductor substrate, wherein the SRAM bit location of at least one 8T possesses double gate oxidated layer thickness nmos pass transistor and a read port.
In another embodiment, provide an integrated circuit, comprising: a semiconductor substrate; The SRAM bit location of at least one 8T, it possesses double gate oxidated layer thickness nmos pass transistor and a read port.A this embodiment and layout is provided, wherein the reading bit line of read port be limited in first stratum metallization on interlayer dielectric layer, and do not have other intervenient raceway grooves.Therefore this embodiment provides the additional performance advantages that combines double gate oxide layer SRAM bit location.
In another embodiment, provide an integrated circuit, comprising: a semiconductor substrate; The SRAM bit location of at least one 10T, it possesses double gate oxidated layer thickness nmos pass transistor and a two read port.The oxidated layer thickness that nmos pass transistor in two read ports has is thinner than the oxidated layer thickness of memory cell transistor.
In another embodiment, the SRAM bit location that comprises 10T in layout with double gate oxidated layer thickness, the metallization that the reading bit line of wherein two read ports is limited in ground floor and does not have other intervenient raceway grooves on interlayer dielectric layer.Therefore this embodiment provides the additional performance advantages of the SRAM bit location that combines double gate oxide layer 10T.
In another embodiment, provide a kind of method, be included in the SRAM bit location layout that defines 8T on the semiconductor substrate; A part in SRAM bit location zone forms possesses six transistorized 6T SRAM parts, and this part comprises two NMOS conduction grid and two NMOS pull-down transistors; The reading section of unit area on the throne forms a read port, comprises NMOS conduction grid and a NMOS pull-down transistor; Make the thickness of grid oxide layer of 4 nmos pass transistors of bit location part of 6T thicker than two transistorized thickness of grid oxide layer of reading section; And form covering of the 1st metal level reading bit line and contact reading section,, provide the electric capacity of reduction and the performance characteristic of lifting whereby therebetween without any other raceway groove.
In another embodiment, provide a kind of method, be included in the SRAM bit location layout that defines 10T on the semiconductor substrate; A part in SRAM bit location zone forms possesses six transistorized 6T SRAM memory cell parts, and this part comprises two NMOS conduction grid and two NMOS pull-down transistors; First reading section of unit area on the throne and second reading section form a read port respectively, comprise NMOS conduction grid and a NMOS pull-down transistor; Make the thickness of grid oxide layer of 4 nmos pass transistors of bit location part of 6T thicker than the transistorized thickness of grid oxide layer of two reading section; And form the covering of the 1st metal level reading bit line respectively and contact two reading section,, provide the electric capacity of reduction and the performance characteristic of lifting whereby therebetween without any other raceway groove.
In another embodiment, provide a SRAM bit location, it possesses two kinds of different grid dielectric materials.Memory cell in the SRAM bit location of 8T with write part and have a first grid dielectric layer (being equivalent to first oxide thickness).Reading section in the SRAM bit location has second grid dielectric layer (being equivalent to the second thin oxide thickness).In another embodiment, one of them material of these gate dielectrics can be an oxide.In another embodiment, one of them material of these gate dielectrics is the grid dielectric material of high k dielectric coefficient.In a further embodiment, reading bit line forms with the 1st metal level, and only is connected to the reading section of the sram cell of 8T with 1 contact layer, therebetween without any other raceway groove.
In another embodiment, provide a CAM bit location, it possesses first memory node part and second reading section.In the embodiment of a CAM bit location, memory node partly comprises the transistor with first thicker gate dielectric, and reading section comprises the transistor with second thin gate dielectric.In another embodiment, the reading bit line that the CAM bit location possesses forms with the 1st metal level, and sees through a contact layer and be connected to reading section, therebetween without any other raceway groove or other metal levels.In another embodiment, the CAM bit location is the multiple grid transistor at the transistor of reading section.In another embodiment, the transistor of CAM bit location possesses gate dielectric and other dielectric layers of high k dielectric coefficient.
In the middle of the configuration of another high speed bit location, the SRAM bit location of 8T, the SRAM bit location of 10T or CAM unit have two parts: bit location storage area and reading section.In storage area, the planar CMOS transistor is provided, in reading section, provide finFET transistor.The transistor of reading section brings the advantage of higher service speed to reading section.The finFET transistor comprises (non-limiting): double gate, triple grid and multiple grid unit.
In another embodiment, SRAM bit location (no matter 8T, 10T, other or the CAM bit location) insulating barrier that is formed on an extension covers silicon (Silicon over insulator is SOI) on the layer.In this embodiment, can continue to use the feature of any other embodiment.That is to say that in the middle of an embodiment, the 8T bit location possesses reading section (comprising memory node) and is formed at soi layer with the write section branch.The transistor that writes part has the first grid medium thickness.The transistor of reading section has the second thin gate dielectric layer thickness.In another embodiment, write the gate dielectric (being equivalent to first oxidated layer thickness) that part has high k dielectric coefficient, the gate dielectric that reading section has high k dielectric coefficient (is equivalent to second oxidated layer thickness, thin than first oxidated layer thickness), in another embodiment, reading section has the oxidation dielectric layer and writes the gate dielectric that part has high k dielectric coefficient, and vice versa.In another embodiment, writing part can have same thickness with the gate dielectric of reading section, but forms with unlike material.In another embodiment, write part and have the first transistor form and reading section has the transistor seconds form.In this infinite example in SOI unit, the transistor seconds form can be the finFET transistor.
Though embodiments of the invention and its advantage illustrate with describing in detail, yet do not breaking away under defined spirit of the present invention such as claim and the category, multi-form change, displacement are all practicable with change.For example, those skilled in the art can understand easily still have many variable places under category of the present invention.
Moreover the viewpoint that the present invention uses is not limited to the embodiment of ad hoc approach described in the specification or step.Any those skilled in the art can understand the existing or following technology and the step that of developing from disclosure of the present invention, identical result all can be used among the present invention as long as implement substantially identical function in can described herein embodiment or obtain substantially.Therefore, protection scope of the present invention comprises above-mentioned technology and step.
Claims (10)
1. the device of a SRAM bit location comprises:
The semiconductor substrate; And
At least one SRAM bit location is formed at a part of described semiconductor substrate;
Wherein said at least one SRAM bit location also comprises the transistor that possesses the first grid medium thickness, with the extra transistor that possesses thin second grid medium thickness, described thin second grid medium thickness is between the 75%-99% of described first grid medium thickness.
2. the device of SRAM bit location as claimed in claim 1, wherein said thin second grid medium thickness is between the 85%-95% of described first grid medium thickness.
3. the device of SRAM bit location as claimed in claim 1, wherein said thin second grid medium thickness is between the 85%-90% of described first grid medium thickness.
4. the device of SRAM bit location as claimed in claim 1, wherein said at least one SRAM bit location comprises a 6T memory cell, formed by nmos pass transistor with described first grid medium thickness, the device of described SRAM bit location also comprises a read port, is formed by having the described nmos pass transistor of thin second grid medium thickness.
5. the device of SRAM bit location as claimed in claim 1, SRAM bit location that wherein said SRAM bit location is 8T and the SRAM bit location of 10T one of them.
6. the device of SRAM bit location as claimed in claim 4 also comprises:
First and second metal level is deposited on described substrate and is separated by the interlayer dielectric layer, with at least some described transistor electrically connects of described SRAM bit location together; And
One reading bit line, do not cover described substrate with described the first metal layer formation and not see through other metal levels, described reading bit line is used a contact layer and is not had to see through the described read port that other any metal level raceway grooves are connected to described SRAM bit location.
7. the device of SRAM bit location as claimed in claim 4, SRAM bit location that wherein said SRAM bit location is 8T and the SRAM bit location of 10T one of them,
Described read port comprises at least one finFET transistor.
8. the integrated circuit of a SRAM bit location comprises:
One logical gate is formed at the first of semiconductor substrate, and possesses a plurality of transistors, and described transistorized some of them have thin gate dielectric;
One SRAM array possesses a plurality of SRAM bit locations, and each SRAM bit location is formed on the second portion of described semiconductor substrate, and described SRAM bit location also comprises:
The 6T memory cell is made up of the nmos pass transistor with described thicker gate dielectric layer thickness;
One read port is formed by having the described nmos pass transistor of thin gate dielectric layer thickness;
Wherein said thin gate dielectric layer thickness is between the 75%-99% of described thicker gate dielectric layer thickness;
First and second metal level is deposited on described substrate and is separated by the interlayer dielectric layer, with at least some described transistor electrically connects of described SRAM bit location together; And
One reading bit line, do not cover described substrate with described the first metal layer formation and not see through other metal levels, described reading bit line is used a contact layer and is not had to see through the described read port that other any metal level raceway grooves are connected to described SRAM bit location.
9. the device of a CAM bit location comprises:
The semiconductor substrate; And
At least one CAM bit location is formed at a part of described semiconductor substrate;
Wherein said at least one CAM bit location also comprises the transistor that possesses the first grid medium thickness, with the extra transistor that possesses thin second grid medium thickness, described thin second grid medium thickness is between the 75%-99% of described first grid medium thickness.
10. the device of CAM bit location as claimed in claim 9 comprises also that comprising the described part of the described semiconductor substrate of described at least one CAM bit location insulator covers silicon layer.
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| US24394109P | 2009-09-18 | 2009-09-18 | |
| US61/243,941 | 2009-09-18 | ||
| US12/748,098 | 2010-03-26 | ||
| US12/748,098 US8294212B2 (en) | 2009-09-18 | 2010-03-26 | Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed |
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| CN102024819A true CN102024819A (en) | 2011-04-20 |
| CN102024819B CN102024819B (en) | 2013-06-19 |
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Also Published As
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| TWI499039B (en) | 2015-09-01 |
| TW201112404A (en) | 2011-04-01 |
| CN102024819B (en) | 2013-06-19 |
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