TWI226682B - Method for forming dual-port DRAM and the memory cell layout - Google Patents

Abstract

The present invention provides a process for dual-port DRAM, which uses the chemical mechanical polishing process (CMP) for shallow trench isolation (STI) on the wafer substrate in normal logic process, and then keep the hydride layer on the wafer to add an additional crown mask step for producing the embedded DRAM with shortened random cycle time. Moreover, the present invention provides two innovative dual-port DRAM memory cell layout methods, which uses the design rule of logic process to produce the dual-port DRAM with the smallest unit memory cell area.

Description

1226682 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor memory process, especially a method for forming an embedded dynamic random access memory (DRAM) and a dual output terminal based on a logic process. (Dua 1-ρ rt) memory cell layout method, this layout method is based on the design principle of the logic process (designru 1 e) to produce a dual output DRAM memory with a minimum unit memory cell area. BACKGROUND OF THE INVENTION The computer and electronics industries not only require an increase in their overall performance, but also must consider the reduction in the cost of manufacturing integrated circuits. As far as computers are concerned, undoubtedly, the size of the equipped memory will not only affect the performance of the computer, but also the unit price of the memory will also affect the price of the computer. Among the types of volatile memory, due to the high density (the number of RAMs per unit area) and the large capacity of dynamic random access memory (DRAM), the market has greatly used it. In recent years, with the rapid increase of the accumulation density of integrated circuits and the significant reduction in component volume, researchers in many related fields have continuously improved or updated DRAM and its processes in order to improve the electrical operation speed of components and the yield of products. And reduce its production costs. When manufacturing dynamic random access memory (DRAM), a process including transistors and capacitors is used to store the digital information in the capacitors by making the capacitors make electrical contact with the source / drain of the transistors. And then by the transistor

1226682 V. Description of the invention (2) Word word line (word 1 i ne) array and bit line (b i t 1 i ne) access the capacitor's digital data. Figure 1 shows two types of DRA M memory cells (mem ryce 1 1) and their bit line operation (bi 11 ine 〇perati οn). Among them, Figure 1 a is a traditional single-port. DRA M memory, that is, a memory cell is composed of a transistor and a capacitor, and its read, write, or refresh action (active) and precharge (precharge) operate through a bit line wheel Figure 1B shows a dual-output (dUa 1 -port) DRAM memory, that is, a memory cell is composed of two transistors and a capacitor, and the two transistors are connected to Two bit lines (BLa / BLb) and two word lines (WLa / WLb) ° In the DRAte memory of the double-wheeled output, the two bit lines of the memory cell can be staggered according to the operation command Take, for example, as shown in FIG. 1B, 'When the bit line of the a output terminal is operating, the bit line of the b output terminal is precharged, and when the bit line of the b output terminal is operating, the The bit line is pre-charged, so when the dual output DRAM (Random cycle time) shortened to only half of the tradition single random cycle time of an output of DRAM, and therefore, the output speed of the dual-end of DRAM memory becomes faster.

1226682 V. Description of the invention (3) Off, the larger the capacitance, the longer the renewal time will be, but relatively it will occupy more silicon substrate area and reduce the degree of component aggregation. Therefore, how to generate the largest capacitance with the smallest unit area has always been the goal pursued by the industry. In addition, the compatibility of the embedded memory cell process in which the memory cell and the logic circuit are fabricated on the same chip is also a key consideration, because it is related to the complexity of the process, in other words, the cost. However, the conventional manufacturing method of DRAM memory, whether it is a DRAM memory with trench capacitors or traditional stacked capacitors, is not completely compatible with general logic processes, so that if the DRAM memory cells and logic circuits are to be fabricated on the same chip There is no doubt that the process steps will be complicated and costly. Therefore, 'how to improve and update the current process of embedded DRAM memory' can effectively solve the above problems and simultaneously produce a post-entry DRAM with a short random cycle time, which is suitable for modern multimedia Applications, personal computers, 3D graphics, and web applications have become an important topic. Summary of the invention: The main purpose of the present invention is to provide a novel process method for embedding DRAM memory, especially dual-port DRAM memory, in a logic process. Make an embedded DRAM with fast random cycle time (r and 0m cy c 1 etime).

1226682 V. Description of the invention (4) Another object of the present invention is to provide an embedded dual output terminal by adding an additional crown mask step in a logic process. -port) DRAM memory manufacturing process 0 Another object of the present invention is to provide a trench side wall (srench low trench capacitor) of a DRAM memory using nitrogen, argon or other inert gas. side wall) performing an ion implantation step, or using a step of initial voltage ion implantation (Vt i mp 1 an tat on) on the side wall of the trench to form a shallow trench capacitance of the DRAM memory with uniform electrical properties. Another object of the present invention is to provide two types of dual-port cell layouts of dual-port DRAM memory manufactured by a design rule of a logic process. The invention discloses a method for forming a dual-port DRA M memory. In a first embodiment of the present invention, first, an oxide layer pad and a nitride layer are sequentially deposited on a semiconductor substrate; then, a plurality of shallow trench isolations (STIs) are formed in the semiconductor substrate and defined. Out of the active area of the component; then, a chemical mechanical polishing process (CMP)

1226682

V. Description of the invention (5) The surface of the plurality of shallow trench isolations is ground flat, and the nitride layer is exposed on the semiconductor substrate; then, one of the plurality of shallow trench isolations is subjected to a crown lithographic etching (croWn photo). / crown etch) step to predetermine a shallow trench capacitance as one of the dual output DRAM memories. After that, the nitride layer and the oxide layer pad are sequentially removed; a sacrificial oxide layer is formed; and an N-type well and / or a P-well implantation step is performed on the semiconductor substrate; and then the sacrificial oxide layer is removed. Then, an oxide layer is formed to serve as a dielectric layer between the transistor oxide layer and the predetermined shallow trench capacitor; then, a plurality of transistor gates and the predetermined shallow trench capacitor upper plate are synchronized to form ^ ^ In addition to the plurality of transistors on the left and right sides of the predetermined shallow trench capacitor, the present invention also discloses a second embodiment of a method for forming a dual output DRAM memory. First, an oxide pad and a nitride layer are sequentially deposited on a semiconductor substrate; then, a plurality of shallow trench isolations (STI) are formed in the semiconductor substrate, and an active area of the element is defined; then, a chemical mechanical process is performed. A grinding process (CMP), smoothing the surfaces of the plurality of shallow trench isolations, and exposing the nitride layer on the semiconductor substrate, and then performing a crown lithography on one of the plurality of shallow trench isolations. A crown photo / crown etch step is used to predetermine a shallow trench capacitance as one of the dual output DRAM memories. After that, the nitride layer and the oxide layer pad are sequentially removed; a sacrificial oxide layer is formed, and an N-type well and / or a P-type implantation step is performed on the semiconductor substrate; and then the sacrificial oxide layer is removed; Next, an oxide layer is formed as a transistor gate oxide layer.

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And the predetermined shallow trench capacitor dielectric layer; then, a plurality of transistor gates and the predetermined shallow trench capacitor upper plate are formed simultaneously, wherein each of the plurality of front and rear sides of the predetermined shallow trench capacitor has the plurality of One of the transistors. Detailed description of the invention: In view of the fact that the conventional technology makes DRA M memory cells and logic circuits on the same chip, there will be a problem that the process steps are complicated and the cost is high. For the purpose of this invention, a novel method process is proposed. That is, after performing shallow trench isolation (STI) CMP in general logic systems, the nitride layer on the wafer is retained and an additional crown mask step is added to achieve the DRAM memory system process and logic. Purpose of process compatibility. Furthermore, the present invention proposes two novel dual-output (dual-= 0rt) DRAM memory cell layout methods. This layout method is based on the design rule of a logic process to produce a device with a minimum unit memory cell area. Dual output DRAM memory. See Figures 2 to 12 for details. This is an example of an embedded dual dua port DRAM memory that is mainly based on a CMOS logic process. Step cross-section diagram. First, as shown in FIG. 2, a p-type semiconductor substrate 10 is prepared, and the p semiconductor substrate 10 is divided into a logic core region 10 and a DRAM memory cell.

1226682 V. Description of the invention (7) The region 102 and an I / O region 103 form a shallow trench isolation region (STI) 2 22 and 23 in the P-type semiconductor substrate 10 to define an active region of the element. Generally, shallow trenches are formed by using lithography and etching to form trenches in a wafer substrate, and then backfilling the shallow trenches with a chemical vapor deposition oxide layer. Before forming a shallow trench isolation region, an oxide layer pad (pad ox i de) 11 and a nitride layer with a thickness of about 1800-150 angstroms are deposited on the P-type semiconductor substrate 10 respectively. (Nitride) 12, followed by etching, deposition, and chemical mechanical polishing (CMP) procedures to form the shallow trench isolation regions 22, 22, and 23, wherein after the CMP step of ST I, the nitrided layer (Nitride) 12 has a thickness of about 100-800 angstroms, and acts as a barrier for the substrate 10 during a subsequent crown photo / crown etch step. Then, perform the crown photo / crown etch step in the DRAM memory cell area 102. As shown in FIG. 3, except for the shallow trench isolation region 22, which is intended to be a shallow trench capacitor of the memory cell, and the vicinity of the vicinity of the DRAM memory cell region 102, the surface of the p-type semiconductor substrate 丄 is marked with A photoresist 30 is covered, this is the corona lithography step. After that, 'the etching selection characteristic is used again (that is, only the oxide is etched, and no effect on the nitride is used)', and the oxide in the shallow trench isolation region 22 is etched and removed, as shown in FIG. Because the surface around the shallow trench isolation zone 22 is covered by the edge gasification layer 2, only the oxides in the present *: cold and Mogan isolation zone 22 are removed, leaving other exposed The p-type ^ $ 体 ^

1226682 V. Description of the invention (8) The board 10 is prevented from being damaged 'so that the junction junction leakage current can be reduced. At this time, the entire area around the top of the trench, the bottom of the Han trench, and the side wall of the trench in the shallow trench isolation zone 22a can be used as the electrode plate under the shallow trench capacitance of the memory cell. This 3D space capacitor structure is helpful Dramatically reduce memory cell size. Then, in order to form a shallow trench capacitor with uniform electrical DRAM memory, it may optionally be before (not shown) or after the photoresist 30 is stripped (as shown in Fig. 5), which is scheduled as the The shallow trench isolation region 22a of the memory cell shallow trench capacitance is subjected to an ion implantation step of a self-align trench side wall. This self-aligned ion implantation step can have the following two methods: (1) Ion implantation of nitrogen, argon, or other inert gas on the side wall of the trench in the shallow trench isolation zone 22a, which can suppress The growth rate of the oxide layer on the side wall of the trench makes the subsequent thickness of the capacitor oxide layer on the side wall of the trench, the bottom surface of the trench, and the top surface around the trench uniform and uniform, that is, this method is suitable for the production depth With a deep cr0wn depth and a very small memory cell, or (2) performing a cell Vt implantation on the sidewall of the trench in the shallow trench isolation area 22a In order to adjust the starting voltage of the trench sidewall (its capacitive oxide layer is thicker)

Page 13 1226682 V. Description of the invention (9) The value should be the same as the starting voltage value of the bottom surface of the trench and the top surface around the trench. Moreover, in the ion implantation step of the self-aligned trench sidewall, the nitride layer 12 remains on the surface of the p-type semiconductor substrate 10, so even if the photoresist 30 is stripped 'and No additional masking step is required for this self-aligned ditch sidewall implantation. Then, the nitride layer 12 and the oxide layer pad 11 are sequentially removed as shown in FIG. 5, and then grown on the silicon surface (except the stI region) of the p-type semiconductor substrate 10 to a thickness of about The M0—150 Å sacrificial oxide layer (SAC ο X ide) 13 is used as a buffer layer for the ion implantation step performed next to the formation of N wells and / or P wells on the side P-type semiconductor substrate 10. Depending on the type of MOS actually needed, N wells are formed in the logic core area 101, the DRAM memory cell area 102, and the I / O area 103 (as shown in Figure 6) 4b 42 and 43 and / After the P well (not shown), the sacrificial oxide layer 13 is removed, and the gate oxide layer of the transistor and the capacitor dielectric layer of the memory cell are formed. In this preferred embodiment, an example is described in which oxide layers of different thicknesses are formed in three regions (ie, the logic core region 101, the DRAM memory cell region 102, and the I / O region 103). First, on the logic core region 101, the DRAM memory cell region 102, and the I / O region 103, a first oxide layer 0X1 having a thickness of t1 is deposited and formed, as shown in FIG. Next, a photoresist is covered on the logic core area 101 and the I / 0 area 103, and the first oxide layer in the DRAM memory cell area 102 is removed.

Page 14 1226682 V. Description of the invention (0) X1, strip the photoresist, and deposit a second oxide layer 0X2 with a thickness of ΐ 2 in the three areas, as shown in Figure 8. After that, a photoresist is covered on the dr AM memory cell region 102 and the I / 0 region 103, and the first and second oxide layers 0X1 + 0X2 in the logic core region 101 are removed, and then the strip is removed. Photoresist, and a third oxide layer χ3 with a thickness of 13 is deposited on the three areas, as shown in FIG. 9, then in the logic core area 101, the DRAM memory cell area 102, and The I / 0 region 1 0 3 forms three oxide layers with different thicknesses to serve as the gate oxide layer of the transistor and the capacitor dielectric layer of the memory cell. Then, as shown in FIG. 10, polycrystalline stone deposition, lithography, and poly deposition / photo / etch steps are performed to form the gate electrodes 6 1, 6 2 a, 6 2 b, and 6 of the transistor. 3 and the upper plate of the memory cell 7 0. At this time, the gates 62a and 62b of the two transistors of the dual-port DRA M memory and a shallow trench capacitor 62c have been formed. Afterwards, lightly doped drain (LDD) implantation steps can be performed on the logic core region 101, the D r AM memory cell region 102, and the I / 〇 region 103 separately. ^ It is shown that an LDD implantation step is performed on the DRAM memory cell region 102, and the logic core region 101 and the I / 〇 region 1 03 are covered with a photoresistor 80, and then are placed in the transistor. A spacer is formed on both sides of the gates 6, 6 2 a, 6 2 b, and 63. Then, the logic core region 101, the DRAM memory cell region 102, and the 1/0 region 10 are subjected to general Other steps in the logic process, such as forming source / drain (S / D), auto-aligned salicide, internal metal dielectric (IMD), and interconnect metal layers

Page 15 1226682 V. Description of Invention (11) and so on. Figure 12 shows a schematic cross-sectional view of the logic core region 10, the DR AM memory cell region 102, and the I / O region 103 after the source / drain (s / D) is completed. Furthermore, Fig. 13 and Fig. 14 show that the present invention uses a design rule of a logic process to design a minimum active area distance and a polysilicon gate distance to produce a unit cell with a minimum unit (un 丨 t ce 1 1) The area of two dual output ports (dual ~ port) dr AM memory cell layout plan (cel 1 layout top view). Figure 13 The dual output DRAM memory cell layout is easy to control the operation of the circuit, and Figure 10 The layout of the dual-output DRAM memory cells is suitable for the poly process margin of the polysilicon process. In FIG. 13, a circuit layout of four unit memory cells (unitce 1 1) 2 0 0 is shown, in which the two transistors 201 and 2 0 2 (corresponding to the two output DRAM unit memory cells 2 0 2 (corresponding to The transistors formed by the component numbers 6 2 a and 6 2 b in FIG. 12 are respectively located on the two diagonal sides of the shallow trench capacitor 2 0 3 (corresponding to the component number 62 c in FIG. 12). The left and right ends of the shallow trench capacitor 203 are connected to the drains D of the transistors 201 and 202 respectively, and the two word lines WL1 and WL2 are connected to or extend from the transistors 201 and 1 respectively. 2 0 2 gates 6 2 a and 6 2 b, and the gates 62 a and 62 b are respectively located on the active area 2 05 and 2 5 5 ′, and the transistors 2 0 1 and 2 0 2 are The source S is connected to the bit lines BL1 and BL2 (as shown in Fig. 12) through contact windows (c ο ntact window) 2 0 4 and 2 0 4 ', respectively.

Page 161226682 V. Description of the invention (12) In Fig. 14, the circuit layout of four unit memory cells (unitce 1 1) 3 0 0 is also shown. Among them, the dual output end DRAM unit memory cells 3 0 0 The two transistors 3 0 1 and 3 0 2 are located on one side of the shallow trench capacitor 3 0 3 and are aligned in front and back. The front and back ends of the shallow trench capacitor 2 0 3 are respectively connected to the transistor 3 0 1. Is connected to the drain D of 3 02, the two word lines WL1 'and WL2' share the same wire and are connected to the gates 6 2a 'and 6 2b' of the transistors 301 and 3 02, and The gates 62a 'and 6 2b' are located on the active regions 305 and 3 05 ', respectively, and the sources S of the transistors 301 and 30 2 are respectively provided through contact windows ((: 〇11 七3 (^ ~ 111 (1 (^) 3 0 4 and 3 0 4 'are connected to the bit line 6 [1 and 2 (not shown). The above description uses a preferred embodiment to describe the present invention in detail, Rather than limiting the scope of the invention, and those skilled in the art will understand that appropriate changes and adjustments will still be made without departing from the spirit of the invention and without departing from the spirit and scope of the invention. Wai.

Page 171226682 Schematic illustrations of the diagrams: The above-mentioned technical content and many advantages of the present invention can be easily understood through the following detailed description in conjunction with the accompanying drawings, of which: Figure 1A and Figure 1 B, which shows two kinds of DRA MM memory cells and their bit line operation (bi 11 ineoperati ο η); Figures 2 to 12 are diagrams of a logical process performed by an embodiment of the present invention The schematic diagram of the steps of the embedded dual-port (DRA) 1-port DR AM memory; and Figures 13 and 14 show the design rule of the logical process of the present invention. Two types of dual-wheel-out DR (memory) DR AM memory cell layout top views were produced with the smallest unit memory area (unit cel 1). Description of drawing number: semiconductor substrate 10 logic core area 1 0 1 DRAM memory cell area 102 I / O area 103 oxide layer pad 11 nitride layer 1 2

Page 181226682 Schematic illustration of photoresist 30, 80 sacrificial oxide layer 13 Shallow trench isolation area 21, 22, 23 N well 4 1, 4 2, 4 3 Thickness t1, t2, t3 27 Photoresist mask first oxidation Layer 0X1 Second oxide layer 0X2 Gate 61, 62a, 62b, 63, 62a ', 62b' Shallow trench capacitance 6 2 c Unit memory cell 2 0 0, 3 0 0 Transistor 201, 202, 301, 302 Drain capacitance 203,303 Word line WL1, WL2, WLa, WLb, WL1 ', WL2' active area 205, 205 ', 305, 305' contact window 204, 204 ', 304, 304' bit line BL 1, BL2, BLa, BLb memory Cell capacitor upper plate 7 0

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Claims (1)

1226682 6. Scope of patent application 1. A method for forming a dual-port DRAM memory, including the following steps: a. Sequentially depositing an oxide layer pad and a nitride layer on a semiconductor substrate; b Forming a plurality of shallow trench isolation (STI) in the semiconductor substrate, and defining the active area of the component; c. Performing a chemical mechanical polishing process (CMP), smoothing the surfaces of the plurality of shallow trench isolations and exposing them The nitride layer is on the semiconductor substrate; d. Performing a crown photo / crown etch step on one of the plurality of shallow trench isolations, as a predetermined shallow one of the dual-output DRAM memory; Trench capacitor, wherein the corona lithography etching step removes the insulation in the shallow trench isolation; e. Performing an N-type and / or P-type implantation step on the semiconductor substrate; f. Forming a An oxide layer as a dielectric layer of the transistor gate oxide layer and the predetermined shallow trench capacitor; and g. Forming a plurality of transistor gates and the predetermined shallow trench capacitor plate simultaneously, wherein Left and right sides of each of such plurality of capacitor canal one electrical crystals. 1226682 6. Application for Patent Scope 2 · The method as described in item 1 of the patent application scope, wherein, after the above step d, a self-aligned ion implantation step is performed on the trench side wall of the predetermined shallow trench capacitor so that The predetermined shallow trench capacitance has uniform electrical properties. 3. The method according to item 2 of the scope of patent application, wherein the self-aligned ion implanted dopant is selected from the group consisting of nitrogen, argon or other inert gas. 4. The method according to item 2 of the scope of patent application, wherein the self-aligned ion implantation is an initial voltage ion implantation. 5. The method according to item 1 of the scope of patent application, wherein the surface area of the predetermined shallow trench capacitor includes the trench side wall, the trench bottom surface and the trench surrounding top surface. 6. The method according to item 1 of the scope of patent application, wherein after the above step d, the nitrided layer and the oxide layer pad are sequentially removed. 7. The method according to item 6 of the scope of patent application, wherein after removing the nitride layer and the oxide layer 塾, a sacrificial oxide layer is formed, and the N-type well and / or the P-type well are implanted. After the step, the sacrificial oxide layer is removed. 8 · —A way to form a dual-port DRAM memory Page 21! 226682 Going through includes the following steps: a • sequentially depositing an oxide pad and a nitride layer on a semiconductor substrate; ^ forming a plurality of shallow trench isolation (STI) in the semiconductor substrate, and defining the active area of the device; C · Perform a chemical mechanical polishing process (CMP), smooth the surface of the plurality of shallow trench isolations, and expose the nitride layer on the semiconductor substrate / · d · Perform one of the plurality of shallow trench isolations A crown lithography / crown etch step is used as a pre-prediction of the dual-input ^ DRAM memory; t shallow trench capacitance, wherein the crown lithography step is to isolate the shallow trench Removing the insulator; ^ e. Performing an N-well and a well-implanting step on the semiconductor substrate; f. Forming an oxide layer as a dielectric layer of the capacitor; and a gate oxide layer and the predetermined The shallow trench g · synchronously forms a plurality of transistor gates and a predetermined predetermined niobium plate, in which one of the predetermined shallow trench capacitors and one of the plurality of transistors are each on the wood. Each of these 1226682 6. Application for Patent Scope 9 · The method as described in item 8 of the patent application scope, wherein, after step d, a self-aligned ion implantation step is performed on the trench side wall of the predetermined shallow trench capacitor to make the The electrical properties of the shallow trench capacitors are expected to be uniform. 1 0. The method according to item 9 of the scope of the patent application, wherein the self-aligned ion implanted dopant is selected from the group consisting of nitrogen, argon, or other inert gas. 1 1 · The method according to item 9 of the scope of patent application, wherein the self-aligned ion implantation is an initial voltage ion implantation. 12. The method according to item 8 of the scope of patent application, wherein the surface area of the predetermined shallow trench capacitor includes the trench side wall, the trench bottom surface, and the trench surrounding top surface. 1 3. The method according to item 8 of the scope of patent application, wherein the nitrided layer and the oxide layer pad are sequentially removed after step d above. 14. The method according to item 13 of the scope of patent application, wherein after removing the nitride layer and the oxide layer 塾, a sacrificial oxide layer is formed, and the N-type well and / or P-type well are performed After the implantation step, the sacrificial oxide layer is removed. 15.—a dual output port (dua port) DRAM memory layout structure, which Page 231226682 6. The scope of patent application includes a plurality of memory cells. Among them, the dual-output DRAM unit memory cell is made by a logic process and includes: a shallow trench capacitor; two transistors, which are respectively located in the The left and right diagonal sides of the shallow trench capacitor, and the drains of the transistors are connected to the left and right ends of the shallow trench capacitor respectively; two word lines (word 1 i ne) are respectively from the transistors The gate extends; and two bit lines (bit 1 in) are connected to the sources of the transistors, respectively. 16. A dual-port DRAM memory layout structure, which includes a plurality of memory cells, wherein the dual-output DRAM unit memory cell is made by a logical process and includes: Page 24