CN102024401A - Driving device, display panel, display device and electronic system - Google Patents
Driving device, display panel, display device and electronic system Download PDFInfo
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- CN102024401A CN102024401A CN2009101775410A CN200910177541A CN102024401A CN 102024401 A CN102024401 A CN 102024401A CN 2009101775410 A CN2009101775410 A CN 2009101775410A CN 200910177541 A CN200910177541 A CN 200910177541A CN 102024401 A CN102024401 A CN 102024401A
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Abstract
The invention provides a driving device, which is used for outputting a plurality of driving signals, and the driving signals are enabled in sequence. The driving device comprises a shift register, a buffer cell and a plurality of switching circuits, wherein the shift register comprises shift register units which are in multi-level series connection; the shift register units respectively generate a plurality of shift signals which are enabled in sequence; the buffer cell is used for receiving at least one input signal; the input signal is enabled regularly; the buffer cell outputs the input signal in a buffering mode; the switching circuits are respectively coupled with the shift register units so as to receive the shift signals; the switching circuits are coupled with the buffer cell together so as to receive the input signals; and the switching circuits output the input signals in sequence so as to use the input signals as the driving signals in accordance with the enabling of the shift signals.
Description
Technical field
The invention relates to a kind of drive unit, particularly relevant for a kind of scanning driving device that is applicable to display panel.
Background technology
Fig. 1 is the scanning driving device in the known display panel of expression.Consult Fig. 1, scanning driving device 1 output drive signal S
1-S
N(N is a positive integer), and pass through the multi-strip scanning line with drive signal S
1-S
NBe sent to the array of display of display panel.Scanning driving device 1 comprises multi-stage shift registering units connected in series 10
1-10
NAnd a plurality of buffering output units 11
1-11
NShifting deposit unit 10
1-10
NEach comprise switch element 100 and 101 and rp unit 102 and 103, and switch element 100 receives an initial signal.Shifting deposit unit 10
1-10
NProduce shift signal VSR respectively
1-VSR
N, and shift signal VSR
1-VSR
NBe enabled in order.Except shifting deposit unit 10
NIn addition, shifting deposit unit 10
1-10
N-1The shift signal VSR that is produced
1-VSR
N-1Also as next stage shift register shifting deposit unit 10
2-10
NStart signal, and shifting deposit unit 10
1Start signal be by other the device imported.
Buffering output unit 11
1-11
NReceive shift signal VSR respectively
1-VSR
NBuffering output unit 11
1-11
NEach comprise logic gate 110 and impact damper 111.For each output buffer cell, logic gate 110 receives corresponding shift signal, shift signal and the enable signal ENBV that the next stage shifting deposit unit is produced.Logic gate 111 produces the input end of logical signal V110 to impact damper 111.Impact damper 111 buffering output logic signal V110 are to produce corresponding drive signal.
According to the framework of the known scanning driving device 1 of Fig. 1, each shifting deposit unit needs a buffering output unit produce drive signal.If output buffer cell 11
1-11
NUse has the impact damper 111 of big driving force, and then integrated buffer device 111 shared areas increase.Therefore, if display panel is designed to the frame that narrows, each buffering output unit then can't use the impact damper with big driving force because of being subject to area among Fig. 1.
Summary of the invention
The invention provides a kind of drive unit, in order to exporting a plurality of drive signals, and these drive signals are enabled in order.This drive unit comprises shift register, buffer cell and a plurality of on-off circuit.Shift register comprises multi-stage shift registering units connected in series.These shifting deposit units produce a plurality of shift signals respectively, and these shift signals are enabled in order.Buffer cell receives at least one input signal.Be enabled to this input signal cycle, and buffer unit buffers output input signal.A plurality of on-off circuits couple shifting deposit unit respectively to receive shift signal.These on-off circuits couple buffer cell jointly with receiving inputted signal.These on-off circuits are according to the activation of shift signal and export input signal in order and be used as drive signal.
The present invention also provides a kind of display panel, comprising: an array of display; The one scan drive unit comprises above-mentioned drive unit, in order to producing a plurality of drive signals, and by the multi-strip scanning line these drive signals is provided to this array of display, and wherein, these drive signals are enabled in order; And a data driven unit, in order to provide a plurality of data-signals to this array of display by many data lines.
Description of drawings
Fig. 1 represents the scanning driving device of known display panel;
Fig. 2 represents the display panel according to the embodiment of the invention;
Fig. 3 represents scanning driving device according to an embodiment of the invention;
Fig. 4 is illustrated in the signal timing diagram of scanning driving device among Fig. 3;
Fig. 5 is illustrated in an embodiment of the shift register of scanning driving device among Fig. 3;
Fig. 6 is illustrated in the signal timing diagram of shift register among Fig. 5;
Fig. 7 A is illustrated in another embodiment of the shift register of scanning driving device among Fig. 3;
Fig. 7 B is illustrated in the signal timing diagram of shift register among Fig. 7 A;
Fig. 8 is illustrated in another embodiment of the shift register of scanning driving device among Fig. 3;
Fig. 9 is illustrated in the another embodiment of the shift register of scanning driving device among Fig. 3;
Figure 10 represents scanning driving device according to another embodiment of the present invention;
Figure 11 is illustrated in the signal timing diagram of scanning driving device among Figure 10;
Figure 12 is illustrated in an embodiment of the shift register of scanning driving device among Figure 10;
Figure 13 represents the signal timing diagram of the shift register of Figure 12.
Figure 14 is illustrated in another embodiment of the shift register of scanning driving device among Figure 10; And
Figure 15 represents the electronic system according to the embodiment of the invention.
[main element label declaration]
Fig. 1
1～scanning driving device; 10
1-10
N～shifting deposit unit;
11
1-11
N～buffering output unit;
100,101～switch element; 102,103～rp unit;
110～logic gate; 111～impact damper;
ENBV～enable signal; S
1-S
N～drive signal;
V110～logical signal; VSR
1-VSR
N～shift signal.
Fig. 2
2～display panel; 20～array of display;
21～scanning driving device; 22～data driven unit;
D
1-D
M～data-signal; DL
1-DL
M～data line;
S
1-S
N～drive signal; SL
1-SL
N～sweep trace.
Fig. 3
3～scanning driving device; 30～shift register;
31～buffer cell; 32
1-32
N～on-off circuit;
300
1-300
N～shifting deposit unit; 310,311～rp unit;
320-322～on-off element; N30～node;
VSR3
1-VSR3
4～shift signal; BVSR3
1-VSR3
4～reverse phase shift signal;
GND～earth terminal; S
1-S
4～drive signal;
P1～input signal.
Fig. 5
5～shift register; 50
1-50
4～shifting deposit unit;
500～switch element; 501,502～rp unit;
503～capacitor; 504～output unit;
505～switch element; 506～rp unit;
507～transistor; N50, N51, N53～node;
N52～output node; Vout
1-Vout
4～output signal;
STV～start signal; GND～earth terminal;
CKV, XCKV～clock signal.
Fig. 7
7～output unit; 70～Sheffer stroke gate;
71～rp unit.
Fig. 8
8～shift register; 80
1-80
4～shifting deposit unit;
800～switch element; 801～capacitor;
802-804～rp unit; 805～output unit;
806～switch element; 807～rp unit;
808～transistor; GND～earth terminal;
N80, N81, N82, N84～node; N83～output node;
Vout
1-Vout
4～output signal; CKV, XCKV～clock signal;
STV～start signal; V802
1-V802
4～control signal.
Fig. 9
9～output unit; 90～Sheffer stroke gate;
91～rp unit.
Figure 10
1000～scanning driving device; 1001～shift register;
1002～buffer cell;
1002a, 1002b, 1002c, 1002d～rp unit;
1003
1-1003
N～on-off circuit; 1004
1-1004
N～shifting deposit unit;
1005,1006,1007～on-off element; VSR10
1-VSR10
4～shift signal;
BVSR10
1-BVSR10
4～reverse phase shift signal; S
1-S
N～drive signal;
P2, P4～input signal; GND～earth terminal.
Figure 12
12～shift register; 120
1-120
4～shifting deposit unit;
1200～switch element; 1201～capacitor;
1202,1203～rp unit; CKV, XCKV～clock signal;
N120, N121～node; N122～output node;
STV～start signal.
Figure 14
14～shift register; 140
1-140
4～shifting deposit unit;
1400～switch element; 1401～capacitor;
1402-1404～rp unit; N140, N141, N142～node;
N143～output node; STV～start signal;
CKV, XCKV～clock signal.
Figure 15
15～electronic system; 150～input block;
160～display device; 161～controller.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Fig. 2 is the display panel of expression according to the embodiment of the invention.Consult Fig. 2, display panel 2 comprises array of display 20, scanning driving device 21 and data driven unit 22.Scanning driving device 21 produces a plurality of drive signal S that are enabled in regular turn
1-S
N(N is a positive integer), and by multi-strip scanning line SL
1-SL
NWith drive signal S
1-S
NProvide to array of display 20.Data driven unit 22 is by many data line DL
1-DL
M(M is a positive integer) provides a plurality of data-signal D
1-D
MTo array of display 20.The detailed circuit of scanning driving device 21 of the present invention will be in hereinafter explanation.
Fig. 3 represents scanning driving device according to an embodiment of the invention.Consult Fig. 3, scanning driving device 3 is applicable in the display panel 2 of Fig. 2 that it produces drive signal S
1-S
N Scanning driving device 3 comprises shift register 30, buffer cell 31 and multiple-pole switch circuit 32
1-32
N Shift register 30 comprises multi-stage shift registering units connected in series 300
1-300
NFor convenience of description, in the embodiments of figure 3, will produce four drive signal S with scanning driving device 3
1-S
NFor example illustrates, i.e. N=4.Under this example, scanning driving device 3 has four shifting deposit units 300
1-300
4And four on-off circuits 32
1-32
4Shifting deposit unit 300
1-300
4Produce a plurality of shift signal VSR3 respectively
1-VSR3
4And shift signal VSR3
1-VSR3
4Inversion signal BVSR3
1-BVSR3
4Buffer cell 31 receives at least one input signal.In this embodiment, be that to receive an input signal P1 with buffer cell 31 be that example illustrates, and buffer cell 31 comprise the rp unit 310 and 311 of two serial connections.Buffer cell 31 buffering output input signal P1.On-off circuit 32
1-32
4Couple shifting deposit unit 300 respectively
1-300
4To receive shift signal VSR3
1-VSR3
4And reverse phase shift signal BVSR3
1-BVSR3
4
Consult Fig. 3, each on-off circuit 32
1-32
4Comprise on-off element 320-322.Hereinafter will be with on-off circuit 32
1Circuit framework illustrate.The control end of on-off element 320 receives corresponding shift signal VSR3
1, its first termination receives input signal P1 and its second end couples node N30.The control end of on-off element 321 receives corresponding reverse phase shift signal BVSR3
1, its first termination receives input signal P1 and its second end couples node N30.The control end of on-off element 322 receives corresponding shift signal VSR3
1, its first end couples node N30 and its second end couples earth terminal GND.In this embodiment, on-off element 320 is according to low level signal and conducting, and on-off element 321 and 322 is conductings according to high level signal.In addition, on-off element 320 and 322 is to be controlled by shift signal VSR3
1And on-off element 321 is to be controlled by reverse phase shift signal BVSR3
1Therefore on-off element 320 is identical with 321 state, and the state of on-off element 320 and 322 is different.
Fig. 4 is the signal timing diagram of scanning driving device 3 in the presentation graphs 3.Consult Fig. 4, input signal P1 periodically is enabled.Shifting deposit unit 300
1-300
4The shift signal VSR3 that is produced
1-VSR3
4(promptly being in low level) and shift signal VSR3 in regular turn are enabled
1-VSR3
4Activation during can not overlap each other.Because shift signal VSR3
1-VSR3
4Be enabled in order, therefore, on-off circuit 32
1-32
4On-off element 320 be switched in order and on-off circuit 32
1-32
4On-off element 322 not conductings in order so that on-off circuit 32
1-32
4The node N30 that input signal P1 is exported to separately is used as drive signal S in order
1-S
4, i.e. drive signal S
1-S
4Be enabled in order.At this moment, on-off circuit 32
1-32
4On-off element 321 also according to reverse phase shift signal BVSR3
1-BVSR3
4And be switched in order.In addition, for shift signal VSR3
1-VSR3
4Each, when it is in the state of not being enabled (being in high level), on-off element 320 and the 321 not conductings and on-off element 322 conductings of corresponding on-off circuit, so that corresponding on-off circuit is used as corresponding drive signal with the node N 30 that the voltage signal of earth terminal GND exports to separately, promptly drive signal is not enabled.
Produce shift signal VSR3
1-VSR3
4With reverse phase shift signal BVSR3
1-BVSR3
4Shift register 30 have several implementation methods.Consult Fig. 5, the on-off circuit 32 that provides to Fig. 3 is provided shift register 5
1-32
4Shift signal VSR3
1-VSR3
4With reverse phase shift signal BVSR3
1-BVSR3
4Shift register 5 comprises shifting deposit unit 50
1-50
4, and each shifting deposit unit has identical framework.In order to clearly demonstrate, below will be with shifting deposit unit 50
2For example describes.Shifting deposit unit 50
2Comprise switch element 500, rp unit 501 and 502, capacitor 503 and output unit 504.The input end of switch element 500 receives an initial signal and its output terminal couples node N50.Switch element 500 is controlled by clock signal CKV and clock signal XCKV, and wherein, clock signal CKV and clock signal XCKV are anti-phase each other.The input end of rp unit 501 couples node N50 and its output terminal couples node N51.Capacitor 503 is coupled between node N50 and the earth terminal GND.Output unit 504 is coupled between node N51 and the output node N52 and produces corresponding shift signal VSR3 on output node N52
2Output unit 504 also produces reverse phase shift signal BVSR3
2The input end of rp unit 502 couples node N51 and its output terminal produces output signal Vout
2Can learn according to Fig. 5, except shifting deposit unit 50
4In addition, shifting deposit unit 50
1-50
3The output signal Vout that is produced
1-Vout
3Respectively as next stage shift register shifting deposit unit 50
2-50
4Start signal, and shifting deposit unit 50
1Then received signal STV is as its start signal.
Consult Fig. 5, output unit 504 comprises switch element 505, rp unit 506 and transistor 507.The input end of switch element 505 couples node N51 and its output terminal couples node N53.Switch element 505 is controlled by the shifting deposit unit 50 of previous stage
1The output signal Vout that is produced
1And the shifting deposit unit 50 of back one-level
3The output signal Vout that is produced
3The grid of transistor 507 receives the shifting deposit unit 50 of back one-level
3The output signal Vout that is produced
3, its drain electrode couple node N53 and and its source electrode couple earth terminal GND.According to the operation of switch element 505 with transistor 507, reverse phase shift signal BVSR3
2Result from the node N53.Rp unit 506 couples node N53 and receives reverse phase shift signal BVSR3
2, and in the last shift signal VSR3 that produces of output node N52
2By shifting deposit unit 50
2The shift signal VSR3 that is produced
2Then be sent to on-off circuit 32 among Fig. 3
2On-off element 320 and 322 control end, and reverse phase shift signal BVSR3
2Then be sent to on-off circuit 32
2The control end of on-off element 321.Shifting deposit unit 50
1And 50
3-50
4Then carry out and shifting deposit unit 50 according to clock signal CKV and XCKV
2Identical operations.
In the embodiment of Fig. 5, shifting deposit unit 50
1 Switch element 505 be controlled by start signal STV and the back one-level shifting deposit unit 50
2The output signal Vout that is produced
2, and shifting deposit unit 50
1The grid of transistor 507 also receive output signal Vout
2Shifting deposit unit 50
4 Switch element 505 be controlled by the shifting deposit unit 50 of previous stage
3The output signal Vout that is produced
3An and external input signal, and shifting deposit unit 50
4The grid of transistor 507 also receive this outside input signal.
Fig. 6 is the signal timing diagram of the shift register 5 of presentation graphs 5.Consult Fig. 6, for the shift signal VSR3 that can know that expression shift register 5 is produced
1-VSR3
4And reverse phase shift signal BVSR3
1-BVSR3
4With on-off circuit 32
1-32
4The drive signal S that is produced
1-S
4Between relation, draw input signal P1 among Fig. 6, with can set up and the signal timing diagram of Fig. 4 between association.
In certain embodiments, each shifting deposit unit 50 of shift register 5
1-50
4 Interior output unit 504 can logic gate be realized.In order to clearly demonstrate, below will be with shifting deposit unit 50
2For example describes.Consult Fig. 7 A, output unit 7 is coupled between node N51 and the output node N52 and produces shift signal VSR3 on output node N52
2Output unit 7 also produces reverse phase shift signal BVSR3
2Output unit 7 comprises Sheffer stroke gate 70 and rp unit 71.One input end of Sheffer stroke gate 70 couples the shifting deposit unit 50 that node N51, its another input end couple previous stage
1Node N51 and its output terminal produce shift signal VSR3
2Rp unit 71 receives shift signal VSR3
2, and produce reverse phase shift signal BVSR3
2
In the embodiment of Fig. 7 A, shifting deposit unit 50
1An input end of Sheffer stroke gate 70 couple itself N51 node, and its another input end receives the inversion signal of start signal STV.
Fig. 7 B is the signal timing diagram of the shift register 7 of presentation graphs 7A.Consult Fig. 7 B, for the shift signal VSR3 that can know that expression shift register 7 is produced
1-VSR3
4And reverse phase shift signal BVSR3
1-BVSR3
4With on-off circuit 32
1-32
4The drive signal S that is produced
1-S
4Between relation, draw input signal P1 among Fig. 7 B, with can set up and the signal timing diagram of Fig. 4 between association.
Fig. 8 is the embodiment of another shift register of expression.Consult Fig. 8, the on-off circuit 32 that provides to Fig. 3 is provided shift register 8
1-32
4Shift signal VSR3
1-VSR3
4With reverse phase shift signal BVSR3
1-BVSR3
4Shift register 8 comprises shifting deposit unit 80
1-80
4, and each shifting deposit unit has identical framework.In order to clearly demonstrate, below will be with shifting deposit unit 80
2For example describes.Shifting deposit unit 80
2Comprise switch element 800, capacitor 801, rp unit 802-804 and output unit 805.The input end of switch element 800 couples start signal, and its output terminal couples node N80.Switch element 800 is controlled by clock signal CKV and clock signal XCKV, and wherein, clock signal CKV and clock signal XCKV are anti-phase each other.Capacitor 801 is coupled between node N80 and the N81.The input end of rp unit 802 couples node N81 and its output terminal couples node N82.Rp unit 802 is gone up in node N82 and is produced control signal V802
2The input end of rp unit 803 couples node N82 and its output terminal couples node N81.Output unit 805 is coupled between node N82 and the output node N83, in order to produce corresponding shift signal VSR3 on output node N83
2The input end of rp unit 804 couples node N82, and its output terminal couples node N84.Rp unit 804 produces output signal Vout on node N84
2Can learn according to Fig. 8, except shifting deposit unit 80
4In addition, shifting deposit unit 80
1-80
3The output signal Vout that is produced
1-Vout
3Respectively as the start signal of next stage shift register, and shifting deposit unit 80
1Then received signal STV is as its start signal.
Consult Fig. 8, output unit 805 comprises switch element 806, rp unit 807 and transistor 808.The input end of switch element 806 couples node N84, and its output terminal couples output node N83.Switch element 806 is controlled by the control signal V802 on the node N82
2And the shifting deposit unit 80 of back one-level
3The control signal V802 that is produced
3The grid of transistor 808 receives the shifting deposit unit 80 of back one-level
3The control signal V802 that is produced
3, its drain electrode couple output node N83 and and its source electrode couple earth terminal GND.According to the operation of switch element 806 with transistor 808, shift signal VSR3
2Result from the node N83.Rp unit 807 couples output node N83 and receives shift signal VSR3
2, and produce reverse phase shift signal BVSR3
2By shifting deposit unit 80
2The shift signal VSR3 that is produced
2Then be sent to on-off circuit 32 among Fig. 3
2On-off element 320 and 322 control end, and reverse phase shift signal BVSR3
2Then be sent to on-off circuit 32
2The control end of on-off element 321.Shifting deposit unit 80
1And 80
3-80
4Then carry out and shifting deposit unit 80 according to clock signal CKV and XCKV
2Identical operations.
In Fig. 8, shifting deposit unit 80
4 Switch element 806 be controlled by control signal V802
4And an external input signal, and the grid of transistor 808 also receives this outside input signal.
The signal timing diagram of the shift register 8 of Fig. 8 is shown in Fig. 7 B.
In certain embodiments, each shifting deposit unit 80 of shift register 8
1-80
4 Interior output unit 805 can logic gate be realized.In order to clearly demonstrate, below will be with shifting deposit unit 80
2For example describes.Consult Fig. 9, output unit 9 is coupled between node N82 and the output node N83 and produces shift signal VSR3 on output node N83
2Output unit 9 also produces reverse phase shift signal BVSR3
2Output unit 9 comprises Sheffer stroke gate 90 and rp unit 91.One termination of Sheffer stroke gate 90 is received the control signal V802 on the node N82
2, its other end receives the shifting deposit unit 80 of previous stage
1The control signal V802 that is produced
1, and its output terminal produces shift signal VSR3
2Rp unit 91 receives shift signal VSR3
2, and in producing reverse phase shift signal BVSR3
2
In Fig. 9, shifting deposit unit 80
1An input end receiving node N82 of Sheffer stroke gate 90 on control signal V802
1, and its another input end receives an external input signal.
Figure 10 represents scanning driving device according to another embodiment of the present invention.Consult Figure 10, scanning driving device 1000 is applicable in the display panel 2 of Fig. 2 that it produces drive signal S
1-S
N Scanning driving device 1000 comprises shift register 1001, buffer cell 1002 and multiple-pole switch circuit 1003
1-1003
N Shift register 1001 comprises multi-stage shift registering units connected in series 1004
1-1004
NFor convenience of description, in the embodiment of Figure 10, will produce four drive signal S with scanning driving device 1000
1-S
NFor example illustrates, i.e. N=4.Under this example, scanning driving device 1000 has four shifting deposit units 1004
1-1004
4And four on-off circuits 1003
1-1003
4Shifting deposit unit 1004
1-1004
4Produce a plurality of shift signal VSR10 respectively
1-VSR10
4And shift signal VSR10
1-VSR10
4Inversion signal BVSR10
1-BVSR10
4Buffer cell 1002 receives two input signal P2 and P3, and wherein, input signal P2 and P3 alternately are enabled.Buffer cell 1002 comprises the rp unit 1002a of serial connection and the rp unit 1002c and the 1002d of 1002b and two serial connections, wherein, the rp unit 1002a and the 1002b of serial connection form a buffer element with receiving inputted signal P2, and the rp unit 1002c and the 1002d of serial connection form another buffer element with receiving inputted signal P3.Buffer cell 1002 is exported input signal P2 by the buffer element buffering that rp unit 1002a and 1002b are formed, and exports input signal P3 by the buffer element buffering that rp unit 1002c and 1002d are formed.On-off circuit 1003
1-1003
4Couple shifting deposit unit 1004 respectively
1-1004
4To receive shift signal VSR10
1-VSR10
4And inversion signal BVSR10
1-BVSR10
4
Consult Figure 10, each on-off circuit 1003
1-1003
4Comprise on-off element 1005-1007.Hereinafter will be with on-off circuit 1003
1Circuit framework illustrate.The control end of on-off element 1005 receives corresponding shift signal VSR10
1, its first termination receives input signal P2 and its second end couples node N100.The control end of on-off element 1006 receives corresponding reverse phase shift signal BVSR10
1, its first termination receives input signal P1 and its second end couples node N100.The control end of on-off element 1007 receives corresponding shift signal VSR10
1, its first end couples node N100 and its second end couples earth terminal GND.In this embodiment, on-off element 1005 is according to low level signal and conducting, and on-off element 1006 and 1007 is conductings according to high level signal.In addition, on-off element 1005 and 1007 is to be controlled by shift signal VSR10
1And on-off element 1006 is to be controlled by reverse phase shift signal BVSR10
1Therefore on-off element 1005 is identical with 1006 conducting state, and the conducting state of on-off element 1005 and 1007 is different.
Need pay special attention at this, consult Figure 10, at the on-off circuit 1003 of odd level
1And 1003
3In, first termination of on-off element 1005 is received input signal P2; And the on-off circuit 1003 of even level
2And 1003
4In, first termination of on-off element 1005 is received input signal P3.
Figure 11 is the signal timing diagram of scanning driving device 1000 among expression Figure 10.Consult Figure 11, input signal P2 and P3 all periodically are enabled in addition, and input signal P2 and P3 also alternately are enabled.Shifting deposit unit 1004
1-1004
4The shift signal VSR10 that is produced
1-VSR10
4Be enabled in regular turn (being in low level), and can partly overlap during the activation of the shift signal of front and back stages.Because shift signal VSR10
1-VSR10
4Be enabled in order, therefore, on-off circuit 1003
1-1003
4On-off element 1005 be switched in order and on-off circuit 1003
1-1003
4On-off element 1007 not conductings in order.At this moment, on-off circuit 1003
1-1003
4On-off element 1006 also according to reverse phase shift signal BVSR10
1-BVSR10
4And be switched in order.When the on-off circuit 1003 that provides to odd level
1And 1003
3Shift signal VSR10
1And VSR10
3One when being enabled, corresponding on-off circuit 1003
1/ 1003
3The node N100 that then input signal P2 is exported to separately is used as corresponding drive signal S
1/ S
3, i.e. drive signal S
1/ S
3Be enabled.When the on-off circuit 1003 that provides to even level
2And 1003
4Shift signal VSR10
2And VSR10
4When being enabled, corresponding on-off circuit 1003
2/ 1003
4Then the node N100 that input signal P 3 is exported to separately is used as drive signal S
2/ S
4, i.e. drive signal S
2And S
4Be enabled.In addition, to shift signal VSR10
1-VSR10
4Each, when it is in the state of not being enabled (being in high level), on-off element 1005 and the 1006 not conductings and on-off element 1007 conductings of corresponding on-off circuit, so that corresponding on-off circuit is used as corresponding drive signal with the node N100 that the voltage signal of earth terminal GND exports to separately, promptly drive signal is not enabled.
Produce shift signal VSR10
1-VSR10
4With reverse phase shift signal BVSR10
1The shift register 1001 of-BVS104 has several implementation methods.Consult Figure 12, the on-off circuit 1003 that provides to Figure 10 is provided shift register 12
1-1003
4Shift signal VSR10
1-VSR10
4With reverse phase shift signal BVSR10
1-BVSR10
4Shift register 12 comprises shifting deposit unit 120
1-120
4, and each shifting deposit unit has identical framework.In order to clearly demonstrate, below will be with shifting deposit unit 120
1For example describes.Shifting deposit unit 120
1Comprise switch element 1200, capacitor 1201 and rp unit 1202 and 1203.The input end of switch element 1200 receives start signal, and its output terminal couples node N120.Switch element 1200 is controlled by clock signal CKV and clock signal XCKV, and wherein, clock signal CKV and clock signal XCKV are anti-phase each other.Capacitor 1201 is coupled between node N120 and the earth terminal GND.The input end of rp unit 1202 couples node N120, and its output terminal couples node N121.Rp unit 1202 is gone up in node N121 and is produced corresponding reverse phase shift signal BVSR10
1The input end of rp unit 1203 couples node N121, and its output terminal couples output node N122.Rp unit 1203 produces corresponding shift signal VSR10 at output node N122
1Can learn according to Figure 12, except shifting deposit unit 120
4In addition, shifting deposit unit 120
1-120
3The shift signal VSR10 that is produced
1-VSR10
3Respectively as the start signal of next stage shift register, and shifting deposit unit 120
1Received signal STV is with as its start signal.
By shifting deposit unit 120
1The shift signal VSR10 that is produced
1Then be sent to on-off circuit 1003 among Figure 10
1On- off element 1005 and 1007 control end, and reverse phase shift signal BVSR10
1Then be sent to on-off circuit 1003
1The control end of on-off element 1006.Shifting deposit unit 120
2-120
4Carry out and shifting deposit unit 120
1Identical operations.
Figure 13 is the signal timing diagram of the shift register 12 of expression Figure 12.Consult Figure 13, for the shift signal VSR10 that can know that expression shift register 12 is produced
1-VSR10
4And reverse phase shift signal BVSR10
1-BVSR10
4With on-off circuit 1003
1-1003
4The drive signal S that is produced
1-S
4Between relation, draw input signal P2 and P3 among Figure 13, with can set up and the signal timing diagram of Figure 11 between association.
Figure 14 is the embodiment of another shift register of expression.Consult Figure 14, the on-off circuit 1003 that provides to Figure 10 is provided shift register 14
1-1003
4Shift signal VSR10
1-VSR10
4With reverse phase shift signal BVSR10
1-BVSR10
4Shift register 14 comprises shifting deposit unit 140
1-140
4, and each shifting deposit unit has identical framework.In order to clearly demonstrate, below will be with shifting deposit unit 140
1For example describes.Shifting deposit unit 140
1Comprise switch element 1400, capacitor 1401 and rp unit 1402-1404.The input end of switch element 1400 receives start signal, and its output terminal couples node N140.Switch element 1400 is controlled by clock signal CKV and clock signal XCKV, and wherein, clock signal CKV and clock signal XCKV are anti-phase each other.Capacitor 1401 is coupled between node N140 and the N141.The input end of rp unit 1402 couples node N141, and its output terminal couples node N142.Rp unit 1402 is gone up in node N142 and is produced corresponding reverse phase shift signal BVSR10
1The input end of rp unit 1403 couples node N142, and its output terminal couples node N141.The input end of rp unit 1404 couples node N142, and its output terminal couples output node N143.Rp unit 1404 produces corresponding shift signal VSR10 on output node N143
1Can learn according to Figure 14, except shifting deposit unit 140
4In addition, shifting deposit unit 140
1-140
3The shift signal VSR10 that is produced
1-VSR10
3Respectively as the start signal of next stage shift register, and shifting deposit unit 140
1Received signal STV is with as its start signal.
By shifting deposit unit 140
1The shift signal VSR10 that is produced
1Then be sent to on-off circuit 1003 among Figure 10
1On- off element 1005 and 1007 control end, and reverse phase shift signal BVSR10
1Then be sent to on-off circuit 1003
1The control end of on-off element 1006.Shifting deposit unit 140
2-140
4Carry out and shifting deposit unit 140
1Identical operations.
The signal timing diagram of the shift register 14 of Figure 14, as shown in figure 13.
Figure 15 is the electronic system of expression according to the embodiment of the invention.Electronic system 15 can be portable apparatus (for example personal digital assistant (personal digital assistant, PDA)), digital camera, notebook computer, desktop PC, mobile phone, display screen device, projector, e-book, digital frame, televisor, automobile-used display or portable DVD player or the like.In general, electronic system 15 comprises input block 150 and display device 160.In addition, input block 150 couples display device 160, and provides a plurality of input signals (for example picture signal) to display device 160.Display device 160 comprises the display panel 2 of controller 161 and Fig. 2.Display panel 2 has the scanning driving device 3 of Fig. 3 or the scanning driving device 1000 of Figure 10.The input signal that controller 161 receives from input block 150.Controller 161 is coupled to display panel 2, and provides a plurality of control signals (for example initial pulse) or view data or the like to display panel 2 according to the input signal that receives.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (10)
1. drive unit, in order to exporting a plurality of drive signals, and these drive signals are enabled in order, and this drive unit comprises:
One shift register comprises multi-stage shift registering units connected in series, and wherein, these shifting deposit units produce a plurality of shift signals respectively, and these shift signals are enabled in order;
One buffer cell in order to receive at least one input signal, wherein, is enabled to this at least one input signal cycle, and this this at least one input signal of buffer unit buffers output; And
A plurality of on-off circuits couple these shifting deposit units respectively to receive these shift signals;
Wherein, these on-off circuits couple this buffer cell jointly receiving this at least one input signal, and these on-off circuits are exported this at least one input signal in order according to the activation of these shift signals and are used as these drive signals.
2. drive unit according to claim 1, wherein, this buffer cell receives one first input signal and this first input signal of buffering output, these on-off circuits receive this first input signal, and these on-off circuits according to the activation of these shift signals and in order conducting be used as these drive signals to export this first input signal respectively.
3. drive unit according to claim 2, wherein, each this on-off circuit comprises:
One first on-off element has the control end that receives this corresponding shift signal, second end that receives first end of this first input signal and couple a first node;
One second switch element has the control end that receives this corresponding shift signal, second end that couples first end of this first node and couple an earth terminal; And
One the 3rd on-off element has the control end that receives a corresponding reverse phase shift signal, second end that receives first end of this first input signal and couple this first node, and wherein, this reverse phase shift signal is anti-phase each other with this corresponding shift signal;
Wherein, this first on-off element and the not conducting simultaneously of this second switch element, the conducting simultaneously of this first on-off element and the 3rd on-off element, and each this on-off circuit produces this corresponding drive signal in this first node.
4. drive unit according to claim 3, wherein, each this shifting deposit unit comprises:
One first switch element has input end that receives an initial signal and the output terminal that couples a Section Point, and is controlled by one first clock signal and a second clock signal, and wherein, this first clock signal and this second clock signal are anti-phase each other;
One first rp unit, the output terminal that has the input end that couples this Section Point and couple one the 3rd node;
One capacitor is coupled between this Section Point and this earth terminal;
One output unit is coupled between the 3rd node and the output node, in order to produce this corresponding shift signal on this output node; And
One second rp unit, the output terminal that has the input end that couples the 3rd node and produce an output signal, wherein, this second rp unit produces this output signal with this start signal of this shifting deposit unit as the back one-level.
5. drive unit according to claim 3, wherein, each this shifting deposit unit comprises:
One first switch element has input end that receives an initial signal and the output terminal that couples a Section Point, and is controlled by one first clock signal and a second clock signal, and wherein, this first clock signal and this second clock signal are anti-phase each other;
One capacitor is coupled between this Section Point and one the 3rd node;
One first rp unit, the output terminal that has the input end that couples the 3rd node and couple one the 4th node, wherein, this first rp unit produces a control signal on the 4th node;
One second rp unit, the output terminal that has the input end that couples the 4th node and couple the 3rd node;
One output unit is coupled between the 4th node and the output node, in order to produce this corresponding shift signal on this output node; And
One the 3rd rp unit, the output terminal that has the input end that couples the 4th node and couple one the 5th node, wherein, the 3rd rp unit produces an output signal with this start signal of this shifting deposit unit as the back one-level on the 5th node.
6. drive unit according to claim 1, wherein, this buffer cell comprises:
One first buffer element is in order to receive one first input signal and this first input signal of buffering output; And
One second buffer element, in order to receive one second input signal and this second input signal of buffering output, wherein, this first input signal and this second input signal are enabled alternately;
Wherein, these on-off circuits of these shifting deposit units of corresponding odd level receive this first input signal, and according to the activation of these shift signals of correspondence and in order conducting is used as these corresponding drive signals to export this first input signal respectively; And
Wherein, these on-off circuits of these shifting deposit units of corresponding even level receive this second input signal, and according to the activation of these shift signals of correspondence and in order conducting is used as these corresponding drive signals to export this second input signal respectively.
7. drive unit according to claim 6, wherein, each this on-off circuit comprises:
One first on-off element has control end, first end that receives this corresponding shift signal and second end that couples a first node;
One second switch element has the control end that receives this corresponding shift signal, second end that couples first end of this first node and couple an earth terminal; And
One the 3rd on-off element has control end, first end that receives a reverse phase shift signal and second end that couples this first node, and wherein, this reverse phase shift signal is anti-phase each other with this corresponding shift signal;
Wherein, in these on-off circuits of the shifting deposit unit of corresponding these odd levels, first termination of three on-off elements such as first end of these first on-off elements and this is received this first input signal;
Wherein, in these on-off circuits of the shifting deposit unit of corresponding these even levels, first termination of first end of these first on-off elements and this grade in an imperial examination three on-off elements is received this second input signal;
Wherein, for each this on-off circuit, this first on-off element and the not conducting simultaneously of this second switch element, the conducting simultaneously of this first on-off element and the 3rd on-off element, and in this corresponding drive signal of this first node generation.
8. drive unit according to claim 7, wherein, each this shifting deposit unit comprises:
One first switch element has input end that receives an initial signal and the output terminal that couples a Section Point, and is controlled by one first clock signal and a second clock signal, and wherein, this first clock signal and this second clock signal are anti-phase each other;
One capacitor is coupled between this Section Point and this earth terminal;
One first rp unit, the output terminal that has the input end that couples this Section Point and couple one the 3rd node, wherein, this first rp unit produces this corresponding reverse phase shift signal on the 3rd node; And
One second rp unit, the output terminal that has the input end that couples the 3rd node and couple an output node, in order on this output node, to produce this corresponding shift signal, wherein, this second rp unit produces this shift signal with this start signal of this shifting deposit unit as the back one-level.
9. drive unit according to claim 7, wherein, each this shifting deposit unit comprises:
One first switch element has input end that receives an initial signal and the output terminal that couples a Section Point, and is controlled by one first clock signal and a second clock signal, and wherein, this first clock signal and this second clock signal are anti-phase each other;
One capacitor is coupled between this Section Point and one the 3rd node;
One first rp unit, the output terminal that has the input end that couples the 3rd node and couple one the 4th node, wherein, this first rp unit produces this corresponding reverse phase shift signal on the 4th node;
One second rp unit, the output terminal that has the input end that couples the 4th node and couple the 3rd node; And
One the 3rd rp unit, the output terminal that has the input end that couples the 4th node and couple an output node, in order on this output node, to produce this corresponding shift signal, wherein, the 3rd rp unit produces this shift signal with this start signal of this shifting deposit unit as the back one-level.
10. display panel comprises:
One array of display;
The one scan drive unit comprises the described drive unit of a claim 1, in order to producing a plurality of drive signals, and by the multi-strip scanning line these drive signals is provided to this array of display, and wherein, these drive signals are enabled in order; And
One data driven unit is in order to provide a plurality of data-signals to this array of display by many data lines.
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| CN200910177541.0A CN102024401B (en) | 2009-09-15 | 2009-09-15 | Drive unit, display panel, display device and electronic system |
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| CN200910177541.0A CN102024401B (en) | 2009-09-15 | 2009-09-15 | Drive unit, display panel, display device and electronic system |
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| CN102024401A true CN102024401A (en) | 2011-04-20 |
| CN102024401B CN102024401B (en) | 2015-09-23 |
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| WO2017133100A1 (en) * | 2016-02-02 | 2017-08-10 | 京东方科技集团股份有限公司 | Emission electrode scanning driving unit, driving circuit, driving method, and array substrate |
| CN113362754A (en) * | 2020-12-07 | 2021-09-07 | 友达光电股份有限公司 | Shift register circuit |
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|---|---|
| CN102024401B (en) | 2015-09-23 |
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