CN102023699A - Processor and control method of high-speed caches - Google Patents

Abstract

The invention discloses a processor and a control method of high-speed caches. The processor comprises a plurality of high-speed caches and a control unit, wherein the high-speed caches are respectively controlled by a plurality of high-speed cache enabling signals to be started, the control unit generates the high-speed cache enabling signals according to a power mode of the processor to select and store subsets corresponding to the power mode of the high-speed caches, and the quantity of the subsets of the high-speed caches is determined by the power mode. Therefore, the processor requires the high-speed caches to be started according to the power mode so as to reduce the power consumption of the high-speed caches.

Description

The control method of processor and cache memory

Technical field

The present invention relates to the control method of a kind of processor and cache memory (cache), and be particularly related to a kind of control method that can dynamically control the processor and the cache memory of cache size.

Background technology

(microcontroller MCU) can be regarded as computing machine on single IC for both to microcontroller, and wherein single IC for both is by being made up of processor, timer and IO interface elements such as (I/O interface).Generally speaking, when the programmed instruction carried out from external program memory (for example flash memory), need microcontroller access program instruction and data, if program storage does not embed in the integrated circuit, (Serial Peripheral Interface is SPI) to reduce the number of pins of integrated circuit by serial peripheral interface.Will be from the data access of program storage to time of microcontroller usually greater than time of microprocessor execution of program instructions or handle by the time of access data, therefore when program storage during by access microcontroller can be in idle state.

The some parts of data in the program storage, Chang Yong program variable for example, often when executive routine by access, and these a little data have good time zone in program storage.Consider usefulness, a plurality of cache memories are implemented in the part usually to be used in the storage data in the microcontroller usually, and other partial data can still be stored in program storage.The storer of hierarchy type storer (memory hierarchy) for having a plurality of different levels, for example cache memory and program storage.Memory hierarchy is high more, and the access time is short more.Be shorter than time from the time of cache memory accesses data from the program storage access data.Yet, when microcontroller is carried out a certain program, be not that all cache memories all can be by access.Cache memory in microcontroller can cause a large amount of power consumptions, and this problem is even more serious when microcontroller is applied to the product of power sensitive.

Summary of the invention

Therefore, quantity and size that embodiments of the invention provide the control method of a kind of processor and cache memory can dynamically control the cache memory that is activated, the cache memory that wherein is activated are that the required access of microcontroller is to reduce the cache memory of power consumption.

The present invention proposes a kind of processor that comprises a plurality of cache memories and a control module.A plurality of cache memories are controlled by a plurality of cache memory enable signals respectively.Control module produces above-mentioned cache memory enable signal according to the electric source modes of processor, and to select the also subclass of the corresponding above-mentioned electric source modes of the above-mentioned cache memory of access, wherein the subclass quantity of cache memory is decided by electric source modes.

In one embodiment of this invention, processor also comprises a plurality of registers.Each register writes down the accessing state information of block in the corresponding cache memory respectively.Control module produces a subclass that controls signal to register, and the subclass of its corresponding selecteed cache memory is with the accessing state information of the subclass of reseting selecteed cache memory.

The present invention proposes a kind of control method of cache memory.At first, provide a plurality of cache memories.These a little cache memories are controlled by a plurality of cache memory enable signals respectively and are activated.Then, produce above-mentioned cache memory enable signal by a control module according to an electric source modes, to select the also subclass of the corresponding power pattern of access cache, wherein the subclass quantity of cache memory is decided by above-mentioned electric source modes.

In one embodiment of this invention, the control method of cache memory also is included in the accessing state information that writes down block in the corresponding cache memory respectively.Reset the accessing state information of block in the subclass of selecteed cache memory.

As the cache size that substitutes traditional static, when making microcontroller be in different mode, the above-mentioned processor and the control method of cache memory can dynamically control the quantity and the size of the cache memory that is activated.Therefore, the power consumption of microcontroller can be reduced effectively.

For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.

Description of drawings

Fig. 1 is the synoptic diagram of explanation according to the processor of one embodiment of the invention.

Fig. 2 is the quantity that under the different electrical power pattern of microcontroller cache memory be activated of explanation according to one embodiment of the invention.

Fig. 3 is the process flow diagram according to the cache memory control method of the present invention's one one exemplary embodiment.

[main element symbol description]

100: processor

110,110_1～110_n: cache memory

120: control module

140_1～140_n: register

B1～Bm, B1～Bj: block

S301～S305: the step of control cache memory

Embodiment

Fig. 1 is the synoptic diagram of explanation according to the processor of one embodiment of the invention.Please refer to Fig. 1, processor 100 comprises a plurality of cache memory 110_1～110_n, a control module 120, a microcontroller 130 and a plurality of register 140_1～140_n, wherein, cache memory 110_1～110_n can for example be cache memory or the outside cache memory that is connected to microcontroller 130 that is embedded in the integrated circuit of microcontroller 130.Each register 140_1～140_n comprises a plurality of blocks of storing many data respectively, for microcontroller 130 accesses, wherein data for example be programmed instruction or when programs executed by microcontroller instructs required data.For example, cache memory 110_1 comprises block B1～Bm, and cache memory 110_2 comprises block B1～Bj, and wherein m, j can be identical or different positive integer.Cache memory 110_1～110_n is controlled by a plurality of cache memory enable signals respectively.

Each register 140_1～140_n temporarily stores the data that may be used again, and these data are the duplicate of data in the support storage device (backing storage device), and wherein support storage device for example is main cache memory (main cache).Each block among cache memory 110_1～110_n also writes down except the storage data and is used for the label of Identification Data in the address of support storage device.When microcontroller 130 executive routines, cache memory 110_1～110_n checks according to label whether required data are stored earlier.If required data have been stored among cache memory 110_1～110_n one of them, it will be called as " hitting (hit) ".On the contrary, if any one that required data can't be in cache memory 110_1～110_n is found, it will be called as " missing (miss) ", and some data among cache memory 110_1～110_n will be evicted from, to transcribe the required data of storing between clearancen from the support storage device access.Generally speaking, replacement policy is with reference to the accessing state information of block among cache memory 110_1～110_n, replaces least-recently-used data with required data.Therefore, in an embodiment of the present invention, each register 140_1～140_n writes down the accessing state information of the block in the corresponding cache memory respectively.

Generally speaking, microcontroller 130 can be set as different electric source modes according to its working load.For example, along with the minimizing of calculated amount, microcontroller 130 can be set as battery saving mode to reduce power consumption.Microcontroller 130 often is used to the product or the device of robotization control, and carries out the routine corresponding to electric source modes.The needed data of corresponding these a little programs can be stored in some cache memory.That is to say, be not that all cache memory 110_1～110_n all must be activated.In an embodiment of the present invention, control module 120 is electrically connected to microcontroller 130 and cache memory 110_1～110_n, and produces the cache memory enable signal to cache memory 110_1～110_n according to the electric source modes of microcontroller 130.By this, control module 120 is responded electric source modes and is selected the also subclass of access cache 110_1～110_n.Just, the number of subsets of cache memory is decided by that cache memory quantity that dynamically control starts and cache size are to reduce the electric source modes of power consumption.

Fig. 2 is the quantity that under the different electrical power pattern of microcontroller 130 cache memory be activated of explanation according to one embodiment of the invention.Please refer to Fig. 2, the cache memory that the corresponding cache memory enable signal that on behalf of Be Controlled unit 120, the cache memory that utilizes the solid line block to be illustrated among cache memory 110_1～110_n exported starts, and the cache memory that the cache memory representative that utilizes the dotted line block to be illustrated among cache memory 110_1～110_n is not activated.Microcontroller 130 accesses are from the data of the cache memory that is activated that is used for executive routine.For example, when microcontroller 130 was in the electric source modes 1 of best system effectiveness, all cache memory 110_1～110_n were activated.In addition, has only a cache memory among cache memory 110_1～110_n, for example cache memory 110_1 be activated when microcontroller 130 is in the electric source modes N that saves maximum power supplys, and other cache memory is not activated.When microcontroller 130 was carried out the program of corresponding power patterns, the quantity that is activated corresponding to the cache memory of different electric source modes can suitably be designed according to the data volume of desired data, so the present invention is not exceeded with this embodiment.In an embodiment of the present invention, a state machine (state machine) can be embedded in control module 120 to select suitable cache memory when electric source modes switches.

With electric source modes N-2 and electric source modes N is example.Please refer to Fig. 1 and Fig. 2, when microcontroller 130 was in electric source modes N-2 and carry out the corresponding program of electric source modes N-2, cache memory 110_1～110_3 was started by the corresponding cache memory enable signal from control module 120.Simultaneously, register 140_1～140_n writes down the accessing state information of the block of corresponding cache memory 110_1～110_3 respectively, for example " hits " or the quantity of " missing ", and it can be consulted to increase the usefulness of replacement policy.Under electric source modes N-2, total size of cache memory is the cache memory summation of cache memory 110_1～110_3 of being activated.When microcontroller 130 switched to electric source modes N, cache memory 110_1 was still started by corresponding cache memory enable signal, but cache memory 110_2～110_3 is not activated.Because required data when carrying out the required data of program of electric source modes N correspondence and may be different from the program of carrying out electric source modes N-2 correspondence partially or completely, control module 120 produces the subclass (that is register 140_1) that controls signal to register 140_1～140_n, its selected subclass corresponding to cache memory 110_1～110_n (that is cache memory 110_1) is with the status information of the selected subclass of reseting cache memory 110_1～110_n and guarantee that microcontroller 130 can normally operate.

In the present embodiment, selecteed cache memory is exemplary in the different electrical power pattern, for example in electric source modes N-2 selecteed cache memory 110_1～110_3 and in electric source modes N selecteed cache memory 110_1, but do not exceed with the disclosed scope of embodiments of the invention.In other embodiments, the blocked operation between the different electrical power pattern is similar to the blocked operation between electric source modes N-2 and electric source modes N in the foregoing description.Quantity and size response that processor 100 is dynamically controlled the cache memory that starts are the electric source modes that reduces the microcontroller of power consumption

Fig. 3 is the process flow diagram according to the cache memory control method of the present invention's one one exemplary embodiment.Please refer to Fig. 1～Fig. 3, the control method of cache memory comprises the following steps.At first, provide a plurality of cache memories 110 (step S301).Then, the electric source modes according to present microcontroller 130 produces corresponding cache memory enable signal (step S302) by control module 120.Then, respond electric source modes, select the also subclass (step S303) of access cache 110.Afterwards, the accessing state information (step S304) of block in the cache memory that record is corresponding respectively.Before present electric source modes switches to next electric source modes, the accessing state information of the block of selected subclass (step S305) in the replacement cache memory 110.For said method, can obtain enough teachings, suggestion and implementation by the above embodiments, do not repeat them here.

In sum, one exemplary embodiment utilization of the present invention provides the control method of a kind of microprocessor and cache memory can dynamically control the quantity and the size of the cache memory that is activated when microcontroller is in different mode.Control module produces the cache size of cache memory enable signal with management corresponding power pattern, and the cache memory of therefore corresponding other different electrical power pattern optionally is designed to meet the demand of power supply.Therefore, the size of the cache memory in the processor dynamically is controlled to reduce power consumption.

Though the present invention with embodiment openly as above; right its is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.

Claims (4)

1. processor comprises:

A plurality of cache memories are controlled by a plurality of cache memory enable signals respectively and are activated; And

One control module, electric source modes according to this processor produces these cache memory enable signals, with select and these cache memories of access to subclass that should electric source modes, wherein the subclass quantity of these cache memories is decided by this electric source modes.

2. processor as claimed in claim 1 also comprises:

A plurality of registers, respectively this register writes down the accessing state information of block in the corresponding cache memory respectively, and wherein this control module more produces one and controls signal to the subclass of these registers of subclass of corresponding selecteed these cache memories with the accessing state information of the subclass of reseting selecteed these cache memories.

3. the control method of a cache memory comprises:

The a plurality of cache memories that are controlled by a plurality of cache memory enable signals and are activated are provided; And

Produce these cache memory enable signals by a control module according to an electric source modes, with select and these cache memories of access to subclass that should electric source modes, wherein the subclass quantity of these cache memories is decided by this electric source modes.

4. control method as claimed in claim 1 also comprises:

In the cache memory of correspondence, write down the accessing state information of block respectively; And

Reset the accessing state information of block in the subclass of selecteed these cache memories.

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