CN102006055A - Negative level high voltage shift circuit - Google Patents
Negative level high voltage shift circuit Download PDFInfo
- Publication number
- CN102006055A CN102006055A CN 201010546237 CN201010546237A CN102006055A CN 102006055 A CN102006055 A CN 102006055A CN 201010546237 CN201010546237 CN 201010546237 CN 201010546237 A CN201010546237 A CN 201010546237A CN 102006055 A CN102006055 A CN 102006055A
- Authority
- CN
- China
- Prior art keywords
- source generator
- circuit
- transistor
- constant pressure
- pressure source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
A negative level high voltage shift circuit relates to the electronic technology. The shift circuit comprises a first constant voltage source generator, a second constant voltage source generator, an inverter, a biased P-type transistor, a bias circuit and a clamping circuit, wherein a bias voltage input end is connected with the first constant voltage source generator and is also connected with the second constant voltage source generator by the inverter; the biased P-type transistor is connected with the first constant voltage source generator and the second constant voltage source generator and is also connected with an output end; the bias circuit and the clamping circuit are connected between the output end and a low level input end in parallel; a low level output end is connected with the first constant voltage source generator and the second constant voltage source generator; a high level input end is connected with the first constant voltage source generator and the second constant voltage source generator; and a negative level high voltage input end is connected with the first constant voltage source generator. The shift circuit simplifies the structural design of the schematic circuit, solves the problem of complexity of high voltage devices, reduces the difficulty of process implementation, improves the stability of the whole circuit and expands the range of application of the circuit.
Description
Technical field
The invention belongs to electronic technology field, relate to and be applied to negative level high pressure shift circuit.
Background technology
In a lot of semiconductor integrated circuit chip for driving or the power electronic chip system, all have different supply voltages on the present market, the supply voltage that has has only several volts, and the supply voltage that has is then up to tens volts.For they being applied in various external connected electronic equipment or the device, must between these equipment or device and the chip for driving of using different electrical power voltage or power electronic chip system, provide interface, change the level displacement circuit that low pressure or low pressure are changed high pressure thereby must in semiconductor integrated circuit, use from high pressure.
In addition, in order to provide best supply voltage to each circuit block in semiconductor integrated circuit, therefore needing provides interface between the circuit block of different electrical power voltage, also must use level displacement circuit.Therefore the importance that can predict following level displacement circuit increases just day by day.
The green science and technology of recently efficiently, saving, environmental protection is in vogue, follow the appearance of energy-conservation low-power consumption requirement, and the continuous expansion of semiconductor integrated circuit chip for driving and power electronic chip application scope, semiconductor integrated circuit chip more and more is applied in the high pressure field.
In the high pressure negative level shift circuit that discrete component constitutes, usually adopt photoelectrical coupler or pulse transformer to realize, yet optocoupler transmission line scope is little, operating current is little, can only be used for little current range, pulse converter is easy to generate distortion to index request than higher, and it is integrated that maximum problem is that these two kinds of devices all are not easy to, thereby this dual mode seldom adopts in power integrated circuit.
A kind of in the market high voltage level shift circuit as shown in Figure 1.Wherein VH is high-end floating power supply, and VB is high-end floating ground, and M1 and M2 must be the high voltage PMOS pipe, and this circuit has less power consumption.But this circuit is when high-voltage applications, need to bear very high voltage between the grid of M1 and M2 pipe and the source electrode, require designed high voltage PMOS pipe to have higher grid source withstand voltage, and this withstand voltage has exceeded the withstand voltage requirement in common PMOS grid source, this has brought difficulty also for simultaneously the design of high voltage PMOS pipe threshold, so the level shift of low voltage circuit in generally being applicable to.
In sum, therefore currently used high pressure negative level shift circuit exists the circuit complexity owing to relate to the realization of high pressure resistant device and the compatibility of high-low pressure technology, the requirement on devices height, and technology realizes difficulty, is not suitable for application problems such as high pressure.
Summary of the invention
Technical problem to be solved by this invention is, overcome that above-mentioned prior art exists not enough and the problem that exists provide a kind of level displacement circuit, when realizing level shift, do not need to use high tension apparatus and voltage device and low-voltage device in all using.
The technical scheme that the present invention solve the technical problem employing is that negative level high pressure shift circuit is characterized in that, comprises the first constant pressure source generator, the second constant pressure source generator, inverter, biasing P transistor npn npn, biasing circuit and reed position circuit;
The bias voltage input termination second constant pressure source generator also connects the second constant pressure source generator by inverter;
Biasing P transistor npn npn connects the first constant pressure source generator and the second constant pressure source generator, also is connected with output;
Biasing circuit and reed position circuit are parallel between output and the low level input, and the low level output also connects the first constant pressure source generator and the second constant pressure source generator;
The high level input termination first constant pressure source generator and the second constant pressure source generator;
The high pressure negative level input termination first constant pressure source generator.
Further, all transistors are all common P transistor npn npn, but not the high-voltage P-type transistor.
The described first constant pressure source generator comprises:
The first transistor and transistor seconds are parallel between high level input and the 3rd transistor;
The 3rd transistor and the 4th transistor of series connection, the 4th transistor connects high pressure negative level input by resistance;
The 5th transistor, grid is connected with drain electrode, and grid also is connected with the grid of transistor seconds, and drain electrode connects electronegative potential by resistance.
The described second constant pressure source generator comprises:
The 8th transistor and the 9th transistor are parallel between high level input and the tenth transistor;
The tenth transistor and the 11 transistor of series connection, the 11 transistor connects high pressure negative level input by resistance;
The 7th transistor, grid is connected with drain electrode, and grid also is connected with the 8th transistorized grid, and drain electrode connects electronegative potential by resistance.
The present invention does not use the high-voltage P-type transistor in whole high pressure negative level shift circuit project organization, be to use common P transistor npn npn, thereby simplified the structural design of schematic circuit greatly, solved the complexity of high tension apparatus, reduced the difficulty that technology realizes, increase the stability of integrated circuit, enlarged the scope of application of this circuit.In sum, this circuit has that circuit is simple, lower to requirement on devices relatively, technology realizes easily, stable working state, be easy to integrated and characteristics such as suitable high-voltage applications.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is existing a kind of level displacement circuit figure.
Fig. 2 is a high pressure negative level shift circuit block diagram of the present invention.
Fig. 3 is a high pressure negative level shift circuit embodiment circuit diagram of the present invention.
Fig. 4 is the first constant pressure source generator circuit diagram of high pressure negative level shift circuit of the present invention.
Fig. 5 is the second constant pressure source generator circuit diagram of high pressure negative level shift circuit of the present invention.
Fig. 6 is high pressure negative level shift circuit simulation result figure of the present invention
Embodiment
Embodiment: shown in Fig. 2,3, a kind of high pressure negative level shift circuit of present embodiment has seven circuit branch: three circuit branch of Far Left constitute the first constant pressure source generator, be labeled as article one circuit branch respectively, second circuit branch, the 3rd circuit branch; The middle branch road constitutes biasing circuit unit and reed position circuit unit, is labeled as the 4th circuit branch; Three circuit branch of rightmost constitute the second constant pressure source generator unit, are labeled as the 5th circuit branch respectively, the 6th circuit branch, the 7th circuit branch.
The whole annexations of the integrated circuit of present embodiment are as follows:
The first constant pressure source generator is managed M1 by resistance R 1, R2, R3, R4, R5 and PMOS, M2, and M3, M4, M5 constitutes three branch roads, wherein:
Article one, circuit branch comprises interconnective resistance R 1, resistance R 2 and resistance R 3;
The second circuit branch comprises interconnective PMOS pipe M1, and PMOS manages M2, and PMOS manages M3, PMOS pipe M4 and resistance R 4; Wherein said PMOS pipe M1 leaks level and PMOS pipe M2 leakage level links together, and the grid of PMOS pipe M1 is used to connect the homophase input control signal S1 of external input voltage signal IN1.
Article three, circuit branch comprises interconnective PMOS pipe M5 and resistance R 5, and grid and the drain electrode of wherein said PMOS pipe M5 link together.
In the above-mentioned first constant pressure source generator, article one in the circuit branch between resistance R 1 and the resistance R 2 signal S6 be connected to the grid of the pipe of PMOS in second circuit branch M3, signal S7 is connected to the grid that PMOS in the second circuit branch manages M4 between resistance R 2 and the resistance R 3.
Biasing P transistor npn npn circuit unit, biasing circuit and clamped circuit unit are the 4th circuit branch, comprise resistance R 6, PMOS pipe M6 and Zener diode Zener.Wherein:
Article four, circuit branch comprises interconnective PMOS pipe M6, resistance R 6 and Zener diode Zener, and wherein resistance R 6 is with Zener diode Zener parallel connection; The drain electrode of PMOS pipe M6 and parallel circuits network are that resistance R 6 is exactly level displacement circuit final output signal V with the output voltage signal S5 between the Zener diode Zener
OUT
The second constant pressure source generator constitutes three branch roads by resistance R 7, R8, R9, R10, R11 and PMOS pipe M7, M8, M9, M10, M11, wherein:
Article five, circuit branch comprises interconnective resistance R 9, resistance R 10 and resistance R 11;
Article six, circuit branch comprises interconnective PMOS pipe M8, PMOS pipe M9, PMOS pipe M10, PMOS pipe M11 and resistance R 8; Wherein said PMOS pipe M8 leaks level and PMOS pipe M9 leakage level links together, and the grid of PMOS pipe M9 is used to connect the anti-phase input control signal S2 that external input voltage signal IN1 produces through inverter.
Article seven, circuit branch comprises interconnective PMOS pipe M7 and resistance R 7, and grid and the drain electrode of wherein said PMOS pipe M7 link together.
In the above-mentioned second constant pressure source generator, article five, signal S8 is connected to the grid that the 6th circuit branch PMOS manages M10 between resistance R 9 in the circuit branch and the resistance R 10, and signal S9 is connected to the grid of PMOS pipe M11 in the 6th circuit branch between resistance R 10 and the resistance R 11.
In above-mentioned level displacement circuit, the output voltage signal S3 in the second circuit branch of the described first constant pressure source generator between M4 drain electrode of PMOS pipe and the resistance R 4 is connected to the grid of the PMOS pipe M6 of the 4th circuit branch; Output voltage signal S4 in the 6th circuit branch of the described second constant pressure source generator between M11 drain electrode of PMOS pipe and the resistance R 8 is connected to the source electrode of PMOS pipe M6 in the 4th circuit branch.
With the present embodiment is the operation principle of example explanation integrated circuit of the present invention:
In the present embodiment, article one, second and the 3rd circuit branch and the 5th, the 6th and the 7th circuit branch PMOS pipe parameter and resistance sizes are symmetrical, so electric current I
D1=I
D9And I
D2=I
D8, I
D5=I
D7Input voltage signal V
CCPerseverance is 5V, V
SS1The ground connection perseverance is 0V, V
SS2For external input high pressure negative level, can suppose V
SS2=-80V, the clamped voltage V of Zener diode
Zener=7V.
Article one, resistance R 2 in the circuit branch, PMOS pipe M3 in R3 and the second circuit branch, M4 constitutes a similar cascade (Cascode) structure just, by configuration resistance R 1, R2, the size of R3 makes M3 pipe and M4 pipe be operated in the saturation region.Small-signal equivalent circuit as shown in Figure 4, M3 and M4 two ends equivalent resistance R
Equ1Approximate (g
M3+ g
Mb3) r
O3r
O4, only relevant with M4 pipe itself with the M3 pipe.This branch road from power in the stable process M3 and M4 small-signal equivalent resistance bigger, it is more to share voltage, thereby has reduced M1 and M2 drain-source both end voltage.The design that pressure pipe is come framework high negative pressure level displacement circuit in having realized using.
Article three, PMOS pipe M5 and resistance R 5 conductings in the circuit branch make it produce a microampere order (10 by configuration PMOS pipe M2 parameter and resistance R 5 sizes
-6) constant-current source I
D5, PMOS pipe M2 and M5 constitute a current mirror, constant-current source I
D5Be mirrored to the M2 current I
D2=I
D5
Article five, PMOS pipe M7 and resistance R 7 conductings in the circuit branch make it produce a microampere order (10 by configuration PMOS pipe M7 parameter and resistance R 7 sizes
-6) constant-current source I
D7, PMOS pipe M7 and M8 constitute a current mirror, constant-current source I
D7Be mirrored to the M8 current I
D8=I
D7
Article seven, resistance R 10 in the circuit branch, PMOS pipe M10 in R9 and the second circuit branch, M11 constitutes a similar cascade (Cascode) structure just, by configuration resistance R 9, R10, the size of R11 makes M10 pipe and M11 pipe be operated in the saturation region.Small-signal equivalent circuit as shown in Figure 5, M10 and M11 two ends equivalent resistance R
Equ2Approximate (g
M10+ g
Mb10) r
O10r
O11, only relevant with M11 pipe itself with the M10 pipe.This branch road from power in the stable process M10 pipe to manage the small-signal equivalent resistance with M11 bigger, it is more to share voltage, thereby has reduced M8 and M9 drain-source both end voltage.The design that pressure pipe is come framework high negative pressure level displacement circuit in having realized using.
When the external biasing voltage signal IN1 of the logic level signal of CMOS compatible/TTL is high level, import the grid of PMOS pipe M1 and M9 respectively, M1 pipe conducting this moment, the M9 pipe ends, and configuration M1 pipe parameter makes it produce a milliampere level (10
-3) electric current I
D1, I here
D1＞＞I
D2=I
D5, because I
D1+ I
D2＞＞I
D9, voltage signal S3 is much larger than voltage signal S4, and PMOS manages M6 gate source voltage V
GS＜0 conducting.Work as R
6I
D6＞V
Zener, Zener diode Zener plays the clamped effect of voltage, final output voltage signal V
OUT=V
SS2+ V
Zener=-80V+7V=-73V＞V
SS2=-80V; Work as R
6I
D6＜V
Zener, Zener diode Zener does not work, final output voltage signal V
OUT=V
SS2+ R
6I
D6＜-80V+7V=-73V.
When the external biasing voltage signal IN1 of the logic level signal of CMOS compatible/TTL is low level, import the grid of PMOS pipe M1 and M9 respectively, M9 pipe conducting this moment, the M1 pipe ends, and configuration M9 pipe parameter makes it produce a milliampere level (10
-3) electric current I
D9, I here
D9＞＞I
D8=I
D7, because I
D9+ I
D8＞＞I
D8, voltage signal S4 is much larger than voltage signal S3, and PMOS manages M6 gate source voltage V
GS＞0 ends, final output voltage signal V
OUT=V
SS2=-80V.
Fig. 6 has provided the simulation result figure of this execution mode, and simulated conditions wherein is: IN1: square-wave signal 0V-5.8V, Vcc:5V, Vss1:0V, Vss2:-80V.Simulation result is as shown in the figure: output V
OUTSignal: square-wave signal-80V-73V, promptly the relative low side with input of the high-end relatively earth potential logical relation of output ground logical relation is identical, has reached the purpose of level shift.
In sum, high pressure negative level shift circuit of the present invention can be used as the basic circuit in semiconductor integrated circuit power electronic chip or the chip for driving, can realize that driving to driving tube is to reach the driving to load.
Claims (5)
1. negative level high pressure shift circuit is characterized in that, comprises the first constant pressure source generator, the second constant pressure source generator, inverter, biasing P transistor npn npn, biasing circuit and reed position circuit;
Bias voltage input (INV1) connects the second constant pressure source generator, also connects the second constant pressure source generator by inverter;
Biasing P transistor npn npn connects the first constant pressure source generator and the second constant pressure source generator, also is connected with output (VOUT);
Biasing circuit and reed position circuit are parallel between output (VOUT) and the low level input (Vss1), and low level output (Vss1) also connects the first constant pressure source generator and the second constant pressure source generator;
High level input (Vcc) connects the first constant pressure source generator and the second constant pressure source generator;
High pressure negative level input (Vss2) connects the first constant pressure source generator.
2. negative level high pressure shift circuit as claimed in claim 1 is characterized in that all transistors are all common P transistor npn npn.
3. negative level high pressure shift circuit as claimed in claim 1 is characterized in that, the described first constant pressure source generator comprises:
The first transistor (M1) and transistor seconds (M2) are parallel between high level input (Vcc) and the 3rd transistor (M3);
The 3rd transistor (M3) and the 4th transistor (M4) of series connection, the 4th transistor (M4) connects high pressure negative level input (Vss2) by resistance (R4);
The 5th transistor (M5), grid is connected with drain electrode, and grid also is connected with the grid of transistor seconds (M2), and drain electrode connects electronegative potential (Vss1) by resistance (R5).
4. negative level high pressure shift circuit as claimed in claim 1 is characterized in that, the described second constant pressure source generator comprises:
The 8th transistor (M8) and the 9th transistor (M9) are parallel between high level input (Vcc) and the tenth transistor (M10);
The tenth transistor (M10) and the 11 transistor (M11) of series connection, the 11 transistor (M11) connects high pressure negative level input (Vss2) by resistance (R8);
The 7th transistor (M7), grid is connected with drain electrode, and grid also is connected with the grid of the 8th transistor (M8), and drain electrode connects electronegative potential (Vss1) by resistance (R7).
5. negative level high pressure shift circuit as claimed in claim 1 is characterized in that described biasing circuit is a resistance R 6, and described reed position circuit is a Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105462371A CN102006055B (en) | 2010-11-16 | 2010-11-16 | Negative level high voltage shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105462371A CN102006055B (en) | 2010-11-16 | 2010-11-16 | Negative level high voltage shift circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102006055A true CN102006055A (en) | 2011-04-06 |
| CN102006055B CN102006055B (en) | 2012-06-20 |
Family
ID=43813172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105462371A Expired - Fee Related CN102006055B (en) | 2010-11-16 | 2010-11-16 | Negative level high voltage shift circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102006055B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883178A (en) * | 2015-05-27 | 2015-09-02 | 中国航天科技集团公司第九研究院第七七一研究所 | Negative voltage level converting circuit inhibiting DC path |
| CN107437434A (en) * | 2016-05-26 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | High voltage level shift circuit and nonvolatile memory |
| CN108616269A (en) * | 2018-07-27 | 2018-10-02 | 无锡安趋电子有限公司 | A kind of downlink level shift circuit of low-work voltage |
| CN112202440A (en) * | 2020-09-15 | 2021-01-08 | 广州慧智微电子有限公司 | Negative voltage level conversion control circuit and method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028468A (en) * | 1994-04-15 | 2000-02-22 | Stmicroelectronics S.R. L. | Voltage-level shifter |
| US6320414B1 (en) * | 1999-05-14 | 2001-11-20 | U.S. Philips Corporation | High-voltage level tolerant transistor circuit |
| US20060091929A1 (en) * | 2004-11-03 | 2006-05-04 | Pauletti Timothy P | Self-biased high voltage level shifter |
| US20080054979A1 (en) * | 2006-08-31 | 2008-03-06 | Oki Data Corporation | Level shifting circuit, driving device, led print head, and image forming apparatus |
| CN101159430A (en) * | 2007-11-15 | 2008-04-09 | 电子科技大学 | Narrow pulse pull-down current type level displacement circuit |
| US7710152B1 (en) * | 2006-07-07 | 2010-05-04 | Analog Devices, Inc. | Multistage dual logic level voltage translator |
| CN101782790A (en) * | 2010-01-26 | 2010-07-21 | 灿芯半导体(上海)有限公司 | Circuit for generating reference voltage and bias current of power chip |
| CN201590808U (en) * | 2009-12-31 | 2010-09-22 | 成都成电硅海科技股份有限公司 | Level conversion circuit of push-pull amplifier |
-
2010
- 2010-11-16 CN CN2010105462371A patent/CN102006055B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028468A (en) * | 1994-04-15 | 2000-02-22 | Stmicroelectronics S.R. L. | Voltage-level shifter |
| US6320414B1 (en) * | 1999-05-14 | 2001-11-20 | U.S. Philips Corporation | High-voltage level tolerant transistor circuit |
| US20060091929A1 (en) * | 2004-11-03 | 2006-05-04 | Pauletti Timothy P | Self-biased high voltage level shifter |
| US7710152B1 (en) * | 2006-07-07 | 2010-05-04 | Analog Devices, Inc. | Multistage dual logic level voltage translator |
| US20080054979A1 (en) * | 2006-08-31 | 2008-03-06 | Oki Data Corporation | Level shifting circuit, driving device, led print head, and image forming apparatus |
| CN101159430A (en) * | 2007-11-15 | 2008-04-09 | 电子科技大学 | Narrow pulse pull-down current type level displacement circuit |
| CN201590808U (en) * | 2009-12-31 | 2010-09-22 | 成都成电硅海科技股份有限公司 | Level conversion circuit of push-pull amplifier |
| CN101782790A (en) * | 2010-01-26 | 2010-07-21 | 灿芯半导体(上海)有限公司 | Circuit for generating reference voltage and bias current of power chip |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883178A (en) * | 2015-05-27 | 2015-09-02 | 中国航天科技集团公司第九研究院第七七一研究所 | Negative voltage level converting circuit inhibiting DC path |
| CN107437434A (en) * | 2016-05-26 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | High voltage level shift circuit and nonvolatile memory |
| CN107437434B (en) * | 2016-05-26 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | High voltage level shift circuit and non-volatile memory |
| CN108616269A (en) * | 2018-07-27 | 2018-10-02 | 无锡安趋电子有限公司 | A kind of downlink level shift circuit of low-work voltage |
| CN108616269B (en) * | 2018-07-27 | 2023-12-29 | 无锡安趋电子有限公司 | Low-working-voltage downlink level shift circuit |
| CN112202440A (en) * | 2020-09-15 | 2021-01-08 | 广州慧智微电子有限公司 | Negative voltage level conversion control circuit and method |
| CN112202440B (en) * | 2020-09-15 | 2022-08-09 | 广州慧智微电子股份有限公司 | Negative voltage level conversion control circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102006055B (en) | 2012-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103856205B (en) | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method | |
| CN102622954B (en) | Bidirectional shift register and driving method thereof | |
| CN106601190A (en) | Shift register unit and driving method thereof, gate drive circuit and display device | |
| CN104700776A (en) | Pixel circuit and driving method thereof, display device | |
| CN206790353U (en) | A kind of isolating transformer drive circuit | |
| KR20120136675A (en) | Level shifter | |
| CN102006055B (en) | Negative level high voltage shift circuit | |
| CN109039059A (en) | A kind of efficient multi-mode charge pump | |
| CN103944554B (en) | A kind of level shifting circuit and digital to analog converter | |
| CN100530965C (en) | High performance level shift circuit with low input voltage | |
| CN102006022B (en) | Low voltage operational amplifier based on CMOS (complementary metal oxide semiconductor) process | |
| CN109412395A (en) | Power initiation adjusts circuit and power supply circuit | |
| CN104124951B (en) | Circuit for driving high-side transistor | |
| CN105897252A (en) | Level shifter circuit applied to display device | |
| CN105577165A (en) | IO interface level conversion circuit and IO interface level conversion method | |
| CN218162431U (en) | Bidirectional level conversion circuit | |
| CN103208988A (en) | Level shifting circuit and method for conducting positive voltage level shifting and negative voltage level shifting | |
| CN203193605U (en) | A driving circuit used for driving a high-voltage device | |
| WO2023024805A1 (en) | Level shift circuit and electronic device | |
| CN207490898U (en) | The logic level transition device and amplifying circuit of dual power supply amplifier | |
| CN106341118B (en) | Level shifter circuit | |
| CN115037292A (en) | High-dropout level transfer circuit with enabling detection and power-down protection | |
| CN109391258A (en) | Level displacement circuit based on low-voltage tube | |
| CN213152036U (en) | Level shift circuit and integrated circuit | |
| CN107422773A (en) | Digital low-dropout regulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120620 Termination date: 20151116 |
|
| EXPY | Termination of patent right or utility model |