CN102005731B - Controller, power converter and method for providing over-temperature protection - Google Patents

Controller, power converter and method for providing over-temperature protection Download PDF

Info

Publication number
CN102005731B
CN102005731B CN201010543816.0A CN201010543816A CN102005731B CN 102005731 B CN102005731 B CN 102005731B CN 201010543816 A CN201010543816 A CN 201010543816A CN 102005731 B CN102005731 B CN 102005731B
Authority
CN
China
Prior art keywords
signal
circuit
controller
thermistor
power converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201010543816.0A
Other languages
Chinese (zh)
Other versions
CN102005731A (en
Inventor
黄伟轩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Taiwan Corp
Original Assignee
System General Corp Taiwan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by System General Corp Taiwan filed Critical System General Corp Taiwan
Priority to CN201010543816.0A priority Critical patent/CN102005731B/en
Publication of CN102005731A publication Critical patent/CN102005731A/en
Application granted granted Critical
Publication of CN102005731B publication Critical patent/CN102005731B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Dc-Dc Converters (AREA)

Abstract

The invention provides a controller, a power converter and a method for providing over-temperature protection. The power converter comprises a transformer, a power switch and a controller, wherein the transformer is provided with a primary winding, a secondary winding and an auxiliary winding; the power switch is coupled with the primary winding of the transformer to adjust the power converter; the controller is provided with an output end so as to generate a driving signal according to a switching signal for switching the power switch; a thermosensitive resistor is coupled with the output end of the controller; and when the switching signal is switched off, the driving signal which spans the thermosensitive resistor is adjusted.

Description

Controller, power converter and the method thereof of over-temperature protection are provided
Technical field
The present invention relates to a kind of pulse width modulation (pulse width modulation, PWM) controller, particularly relate to a kind of PWM controller, it is provided for the over-temperature protection of power converter.
Background technology
Fig. 1 shows the existing power converter that utilizes the controller 60 with over-temperature protection.Power converter comprises transformer 10, power transistor 20, resistor 25, controller 60, thermistor 36, rectifier 11 and 21, capacitor 12 and 22 and secondary feedback circuit 16.Controller 60 has feeder ear VCC, output GATE, sense terminals CS, feedback end FB, temperature detection end RT and earth terminal GND.Transformer 10 comprises armature winding N p, auxiliary winding N aand secondary winding N s.Auxiliary winding N aby rectifier 21, resistor 22 is charged, to generate supply power voltage V cCcontroller 60 is powered.Secondary winding N sgenerate across the output voltage V of the power converter of capacitor 12 by rectifier 11 o.Secondary feedback circuit 16 comprises resistor 13, silicon reference diode 14 and optical coupler 15.Resistor 13 is coupled between the output of power converter and the cathode terminal of silicon reference diode 14.The input of optical coupler 15 couples the anode tap of silicon reference diode 14.Output voltage V on the output of secondary feedback circuit 16 received power transducers oto generate feedback signal V fB.Resistor 25 is coupled to the source electrode of power transistor 20 and with reference between ground connection.In the time that power transistor 20 is connected by the output GATE of controller 60, resistor 25 is by flowing through the switch current I of power transistor 20 pbe converted to sensing voltage V cS.
Controller 60 comprises thermal-shutdown circuit, circuit overcurrent protection, regulating circuit and pulse width modulation (pulse width modulation, PWM) circuit 30.Thermal-shutdown circuit comprises current source 34, comparator 33 and delay circuit 35.Current source 34 is coupled to the temperature detection end RT of controller 60 and the negative terminal of comparator 33.Thermistor 36 is coupled to the temperature detection end RT of controller 60 and with reference between ground connection.The anode receive threshold voltage V of comparator 33 t.The output of comparator 33 generates excess temperature signal S by delay circuit 35 oT.Circuit overcurrent protection comprises comparator 31.Comparator 31 has the deboost of reception V lMTanode and receive sensing voltage V cSnegative terminal.The output of comparator 31 generates overcurrent signal S oC.Regulating circuit comprises comparator 32 and resistor 37.The anode receiving feedback signals V of comparator 32 fB, and by resistor 37 by draw.The negative terminal of comparator 32 receives sensing voltage V cS.The output of comparator 32 generates conditioning signal S rG.Pwm circuit 30 receives overcurrent signal S oC, conditioning signal S rGand excess temperature signal S oT, drive signal V to generate on the output GATE at controller 60 g.
Fig. 2 shows the embodiment of the pwm circuit of controller 60.Pwm circuit 30 comprise oscillator 301, inverter 302, trigger 303, with door 304, NAND gate 305 and 306, blanking circuit (blanking circuit) 307 and buffer 308.The oscillator signal PLS that the input reception oscillator 301 of inverter 302 generates.The output of inverter 302 couples the frequency input ck of trigger 303, to enable trigger 303.The output of inverter 302 also couples the first input end with door 304.The input D of trigger 303 receives excess temperature signal S oT.The output Q of trigger 303 couples the second input with door 304.Generate switching signal S with the output of door 304 pWM.Overcurrent signal S oCwith conditioning signal S rGtwo inputs to NAND gate 305 are provided.The output of NAND gate 305 couples the first input end of NAND gate 306.Blanking circuit 307 is coupled to and the output of door 304 and the second input of NAND gate 306.The output of NAND gate 306 couples the replacement input R of trigger 303, with the trigger 303 of resetting.Buffer 308 receives switching signal S pWMgenerate and drive signal V g.
In existing controller, in order to realize over-temperature protection function, conventionally need a special encapsulation pin.Therefore, need a scheme not destroy its original function in order to the pin count that reduces controller, reach cost-effective object simultaneously.
Summary of the invention
The invention provides a kind of controller that over-temperature protection is provided, be applicable to power converter.This controller comprises commutation circuit, drive circuit, thermal-shutdown circuit and signal generator.Commutation circuit generates switching signal.Drive circuit is made up of high-pressure side transistor and low-pressure side transistor, to generate driving signal.Drive signal to be used for regulating power transducer.Thermal-shutdown circuit couples drive circuit.Thermistor couples drive circuit, and in the down periods of switching signal, adjusts the driving signal across thermistor.Signal generator control thermal-shutdown circuit.Signal generator also couples drive circuit, to drive high-pressure side transistor and low-pressure side transistor.
Thermal-shutdown circuit comprises current source circuit and comparator.Current source circuit is enabled to provide current to thermistor, adjusts the driving signal across thermistor with the down periods in switching signal according to the first signal that signal generator was generated.Comparator is at the down periods of switching signal comparative threshold voltage and driving signal, to generate excess temperature signal.Excess temperature signal drives signal to close power converter in order to forbidden energy.
Signal generator comprises serrated signal, the first comparison circuit, enable circuits and the second comparison circuit.Sawtooth circuit generates the first driving signal and serrated signal according to switching signal.First drives signal to be used for driving high-pressure side transistor.The first comparison circuit is serrated signal and the first reference voltage relatively, with forbidden energy two driving signal.Two driving signal is enabled according to the falling edge of the first driving signal, to drive low-pressure side transistor.Enable circuits generates first signal according to the falling edge of two driving signal.First signal is used for enabling thermal-shutdown circuit.The second comparison circuit is serrated signal and the second reference voltage relatively, to enable secondary signal.Secondary signal is used for forbidden energy thermal-shutdown circuit.Thermistor is thermistor.When in the time that the ambient temperature of the down periods of switching signal power converter raises, the level of switching signal reduces.
Controller also comprises clamped circuit.This clamped circuit is enabled to be coupled to thermistor, drives the boundary level of signal with the down periods strangulation in switching signal.
The present invention also provides a kind of power converter that over-temperature protection is provided, and comprises transformer, power switch and controller.Transformer has armature winding, secondary winding and auxiliary winding.Power switch couples the armature winding of transformer with regulating power transducer.Controller has output, to generate and to drive signal to carry out power switched switch according to switching signal.Thermistor is coupled to the output of controller.In the down periods of switching signal, adjust the driving signal across thermistor.
Controller comprises commutation circuit, thermal-shutdown circuit and clamped circuit.Commutation circuit generates switching signal.Thermal-shutdown circuit is coupled to thermistor, with the down periods in switching signal, adjusts the driving signal across thermistor.Clamped circuit is enabled to be coupled to thermistor, drives the boundary level of signal with the down periods strangulation in switching signal.Thermistor is thermistor.
The present invention also provides a kind of method that over-temperature protection is provided, and is applicable to power converter.The method comprises: switching signal is provided; Generate and drive signal with power switched switch according to switching signal, use regulating power transducer; In the down periods of switching signal, generate serrated signal; In the time that serrated signal exceedes the first reference voltage, enable thermal-shutdown circuit; Adjust driving signal according to the ambient temperature of power converter; Relatively drive signal and threshold voltage to enable inhibit signal, use and after time of delay, generate excess temperature signal; And in the time that serrated signal exceedes the second reference voltage, forbidden energy thermal-shutdown circuit.In the down periods of switching signal, drive signal to be adjusted to lower than a boundary level.This boundary level is used for avoiding power switch to be switched within the down periods of switching signal.Excess temperature signal is used for disconnecting power switch.The second reference voltage level is greater than the first reference voltage level.
An object of the present invention is to provide over-temperature protection to power converter.
Another object of the present invention is to the pin count of the controller that reduces power converter, not original defencive function of breakdown power transducer of while.
Accompanying drawing explanation
Fig. 1 shows existing power converter;
Fig. 2 shows the pwm circuit of existing power converter internal controller in Fig. 1;
Fig. 3 shows the power converter according to the embodiment of the present invention;
Fig. 4 shows according to the pwm circuit of the controller of the embodiment of the present invention;
Fig. 5 shows according to the signal generator of the controller of the embodiment of the present invention;
Fig. 6 shows the various waveforms according to the controller of the embodiment of the present invention;
Fig. 7 shows according to the delay circuit of the pwm circuit of the embodiment of the present invention; And
Fig. 8 shows the method that offers power converter over-temperature protection according to the embodiment of the present invention.
Reference numeral explanation
Fig. 1:
10～transformer; 11～rectifier;
12～capacitor; 13～resistor;
14～silicon reference diode; 15～optical coupler;
16～secondary feedback circuit; 20～power transistor;
21～rectifier; 22～capacitor;
25～resistor;
30～pulse width modulation (PWM) circuit;
31,32,33～comparator; 34～current source;
35～delay circuit; 36～thermistor;
37～resistor; 60～controller;
CS～sense terminals; FB～feedback end;
GATE～output; GND～earth terminal;
I p～switch current; N a～auxiliary winding;
N p～armature winding; N s～secondary winding;
RT～temperature detection end; S oC～overcurrent signal;
S oT～excess temperature signal; S rG～conditioning signal;
V cC～supply power voltage; V cS～sensing voltage;
V fB～feedback signal; V g～driving signal;
V lMT～deboost; V o～output voltage;
V t～threshold voltage; VCC～feeder ear.
Fig. 2:
30～pulse width modulation (PWM) circuit;
301～oscillator; 302～inverter;
303～trigger; 304～with door;
305,306～NAND gate; 307～blanking circuit;
308～buffer; The frequency input of ck～trigger;
The input of D～trigger 303; PLS～oscillator signal;
The output of Q～trigger 303;
The replacement input of R～trigger 303;
S oC～overcurrent signal; S oT～excess temperature signal;
S pWM～switching signal; S rG～conditioning signal;
V g～driving signal.
Fig. 3
10～transformer; 11～rectifier;
12～capacitor; 13～resistor;
14～silicon reference diode; 15～optical coupler;
16～secondary feedback circuit; 20～power transistor;
21～rectifier; 22～capacitor;
25～resistor; 31,32～comparator
36～thermistor; 37～resistor;
50～pulse width modulation (PWM) circuit;
100～controller; CS～sense terminals;
FB～feedback end; GATE～output;
GND～earth terminal; I p～switch current;
N a～auxiliary winding; N p～armature winding;
N s～secondary winding; S oC～overcurrent signal;
S rG～conditioning signal; V cC～supply power voltage;
V cS～sensing voltage; V fB～feedback signal;
V g～driving signal; V lMT～deboost;
V o～output voltage; VCC～feeder ear.
Fig. 4
50～pulse width modulation (PWM) circuit;
70～signal generator; 301～oscillator;
302～inverter; 303～trigger;
304～with door; 305,306～NAND gate;
307～blanking circuit; 309～NAND gate;
310～comparator; 311～current source;
312,313～switch; 314～diode;
315～buffer; 316～transistor;
317～buffer; 318～transistor;
319～delay circuit; The input end of clock of ck～trigger 303;
The input of D～trigger 303; GATE～output;
PLS～oscillator signal; The output of Q～trigger 303;
The replacement input of R～trigger 303;
S 1～first signal; S 2～secondary signal;
S d～inhibit signal; S h～the first drives signal;
S lthe～the two driving signal; S oC～overcurrent signal;
S pWM～switching signal; S rG～conditioning signal;
S oT～excess temperature signal; V cC～supply power voltage;
V g～driving signal; V t～threshold voltage.
Fig. 5
70～signal generator; 711,712～inverter;
713～current source; 714,715～switch;
716～capacitor; 717,718～comparator;
720,721,722～NOR gate;
S 1～first signal; S 2～secondary signal;
S h～the first drives signal; S lthe～the two driving signal;
S pWM～switching signal; V cC～supply power voltage;
V r1the～the first reference signal; V r2the～the second reference signal;
V rMP～ramp signal.
Fig. 6:
A～time point; S 1～first signal;
S 2～secondary signal; S h～the first drives signal;
S lthe～the two driving signal; S pWM～switching signal;
V fthe forward voltage of～diode 314; V g～driving signal;
V r1the～the first reference signal; V r2the～the second reference signal;
V rMP～ramp signal; V t～threshold voltage.
Fig. 7:
319～delay circuit; 321,322,326～trigger;
The input end of clock of ck～trigger;
The input of D～trigger; GATE～output;
PLS～oscillator signal; The output of Q～trigger;
the reversed-phase output of～trigger;
The replacement input of R～trigger;
S oT～excess temperature signal; S d～inhibit signal;
V cC～supply power voltage.
Fig. 8:
1001...1007～method step.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Fig. 3 shows the power converter according to the embodiment of the present invention.This power converter comprises transformer 10, power switch 20, resistor 25, controller 100, thermistor 36, rectifier 11 and 21, capacitor 12 and 22 and secondary feedback circuit 16.In this embodiment, power switch 20 is a power transistor.Controller 100 has feeder ear VCC, output GATE, sense terminals CS, feedback end FB and earth terminal GND.Transformer 10 comprises armature winding N p, auxiliary winding N aand secondary winding N s.Auxiliary winding N aby rectifier 21, capacitor 22 is charged, to generate supply power voltage V cCcontroller 60 is powered.Secondary winding N sgenerate across the output voltage V of the power converter of capacitor 12 by rectifier 11 o.Secondary feedback circuit 16 comprises resistor 13, silicon reference diode 14 and optical coupler 15.Resistor 13 is coupled between the output of power converter and the cathode terminal of silicon reference diode 14.The input of optical coupler 15 couples the anode tap of silicon reference diode 14.Output voltage V on the output of secondary feedback circuit 16 received power transducers oto generate a feedback signal V fB.Resistor 25 is coupled to the source electrode of power transistor 20 and with reference between ground connection.When power transistor 20 is controlled by the output GATE of controller 60 and while connecting, resistor 25 will be converted to sensing voltage V the switch current IP of the power transistor 20 of flowing through cS.
Controller 100 comprises circuit overcurrent protection, regulating circuit and pulse width modulation (pulse width modulation, PWM) circuit 50.According to one embodiment of the invention, the thermistor 36 with negative temperature coefficient feature is coupled to the output GATE of controller 100.In the time that ambient temperature raises, the resistance value of thermistor 36 will reduce, and vice versa.Circuit overcurrent protection comprises comparator 31.The anode of comparator 31 receives deboost V lMT, its negative terminal receives sensing voltage V cS.The output of comparator 31 generates overcurrent signal S oC.Regulating circuit comprises comparator 32 and resistor 37.The anode of comparator 32 receives feedback voltage V fB, and by drawing on resistor 37.The negative terminal of comparator 32 receives sensing voltage V cS.The output of comparator 32 generates conditioning signal S rG.Overcurrent signal S oCwith conditioning signal S rGbe provided to pwm circuit 50 and drive signal V to generate g.
Fig. 4 shows according to the pwm circuit 50 of the controller 100 of the embodiment of the present invention.Pwm circuit 50 comprises commutation circuit, thermal-shutdown circuit, clamped circuit, signal generator 70 and drive circuit.Commutation circuit comprise oscillator 301, inverter 302, trigger 303, with door 304, NAND gate 305 and 306 and blanking circuit (blanking circuit) 307.Thermal-shutdown circuit comprises current source 311, switch 312, comparator 310, NAND gate 309 and delay circuit 319, and wherein, current source 311 forms current source circuit with switch 312.Drive circuit comprises buffer 315 and 317 and transistor 316 and 318.In this embodiment, clamped circuit is realized by switch 313 and diode 314.
Oscillator 301 generates oscillator signal PLS.Oscillator signal PLS is provided to the input end of clock ck of trigger 303 and the first input end with door 304 by inverter 302.The output Q of trigger 303 couples the second input with door 304.Generate switching signal S with the output of door 304 pWM.Overcurrent signal S oCwith conditioning signal S rGbe provided to two inputs of NAND gate 305.The output of NAND gate 305 couples the first input end of NAND gate 306.The second input of NAND gate 306 receives switching signal S by blanking circuit 307 pWM.The output of NAND gate 306 couples the replacement input R of trigger 303, with the trigger 303 of resetting.
Switching signal S pWMbe provided to signal generator 70 to generate the first driving signal S h, two driving signal S l, first signal S 1and secondary signal S 2.The first end of current source 311 couples supply power voltage V cC.Switch 312 and switch 313 coupled in series are between the second end of current source 311 and the anode of diode 314.The negative electrode of diode 314 couples with reference to ground connection.Switch 312 and 313 is all by first signal S 1institute controls.Transistor 316 and transistor 318 coupled in series are in supply power voltage V cCand between ground connection, wherein, couple supply power voltage V cCtransistor 316 be called high-pressure side transistor, be called low-pressure side transistor and couple with reference to the transistor 318 of ground connection.First drives signal S hcontrol transistor 316 by buffer 315.Two driving signal S lcontrol transistor 318 by buffer 317.The common tie point of transistor 316 and 318 couples the output GATE of controller 100, drives signal V to generate g.The common tie point of switch 312 and switch 313 also couples the output GATE of controller 100.The output GATE of controller 100 couples the positive input terminal of comparator 310.The negative input end receive threshold voltage V of comparator 310 t.The output of comparator 310 couples the first input end of NAND gate 309.The second input of NAND gate 309 receives secondary signal S 2.The output of NAND gate 309 provides inhibit signal S dto the input of delay circuit 319.The output of delay circuit 319 generates excess temperature signal S oTto the input D of trigger 303.
Fig. 5 shows according to the signal generator 70 of the controller 100 of the embodiment of the present invention.Signal generator 70 comprises sawtooth circuit, the first comparison circuit, the second comparison circuit and enable circuits.Sawtooth circuit comprises inverter 711 and 712, current source 713, switch 714 and 715 and capacitor 716.The first comparison circuit comprises comparator 717 and NOR gate 720.The second comparison circuit comprises comparator 718 and NOR gate 722.In this embodiment, enable circuits is realized by NOR gate 721.The first end of current source 713 couples supply power voltage V cC. Switch 714 and 715 coupled in series in the second end of current source 713 and with reference to ground connection between.Switch 715 is controlled by switching signal S pWM.The input of inverter 712 receives switching signal S pWM.The output of inverter 712 couples the input of inverter 711.
The output of inverter 711 generates first and drives signal S h.Switching signal S pWMby inverter 712 control switchs 714.Capacitor 716 is in parallel with switch 715.By obtain ramp voltage V on capacitor 716 rMP.Ramp voltage V rMPbe provided to the anode of comparator 717 and the negative terminal of comparator 718.The anode of the negative terminal of comparator 717 and comparator 718 receives respectively the first reference signal V r1with the second reference signal V r2.The second reference signal level is greater than the first reference signal level.The first input end of NOR gate 720,721 and 722 all receives the first driving signal S h.The second input of NOR gate 720 couples the output of comparator 717.The second input of NOR gate 722 couples the output of comparator 718.The output of NOR gate 720 generates two driving signal S l.Two driving signal S lbe provided to the second input of NOR gate 721.The output of the output of NOR gate 721 and NOR gate 722 generates respectively first signal S 1and secondary signal S 2.
Fig. 6 shows according to the various waveforms of the controller 100 of the embodiment of the present invention.Consult Fig. 5, as switching signal S simultaneously pWMwhile being disabled (disabled), switch 714 will be connected, and switch 715 will disconnect.Current source 713 will charge to capacitor 716 by switch 714, to generate the ramp voltage V across capacitor 716 rMP.Consult Fig. 6, ramp voltage V rMPbe considered as serrated signal.Once switching signal S pWMbe disabled, first drives signal S hto be disabled.Two driving signal S lwill be according to the first driving signal S hfalling edge and be enabled (enabled).Consult Fig. 4, transistor 318 is by buffer 317 and by two driving signal S again lconnect.Drive signal V gtherefore and for example, by the level (0V) being pulled down to reference to ground connection.Once ramp voltage V rMPcontinue to increase and exceed the first reference voltage V r1level time, two driving signal S lto be disabled.First signal S 1will be according to two driving signal S lfalling edge and be enabled.This will disconnect transistor 318, and turn on- switch 312 and 313.
Consult Fig. 3, thermistor 36 is coupled to the output GATE of controller 100 and with reference between ground connection.When switch 312 and 313 is by first signal S 1when connection, a series connection parasitic resistor (not shown) of diode 314 is by the output GATE by controller 100 and in parallel with thermistor 36.Because the resistance value of the parasitic resistor of diode 314 is relatively less than the resistance value of thermistor 36, the most of electric current therefore being provided by current source 311 will flow to diode 314.At this moment, drive signal V glevel then will be pulled to the forward voltage V of diode 314 flevel.The forward voltage V of diode 314 fguarantee now to drive signal V gboundary level, to avoid power transistor 20 at switching signal S pWMdown periods in be switched on.Be provided to the threshold voltage V of the negative terminal of comparator 310 tdefinition excess temperature condition, and threshold voltage V tlower than the forward voltage V of diode 314 f.Because thermistor 36 has negative temperature coefficient feature, therefore (it also equals to drive signal V to the voltage level of thermistor 36 glevel) will raise and reduce along with ambient temperature.When driving signal V glevel become the forward voltage V lower than diode 314 ftime, most of electric current that current source 311 provides will flow to thermistor 36.When driving signal V glevel constantly along with ambient temperature raise and reduce and become lower than threshold voltage V ttime (for example in Fig. 6 by " A " time point of indication), comparator 310 will enable inhibit signal S by NAND gate 306 d.Once inhibit signal S dthe time being enabled is longer than the time of delay that delay circuit 319 provides, and delay circuit 319 will generate low logic excess temperature signal S oTgive the input D of trigger 303, with forbidden energy switching signal S pWM, this will drive signal V by forbidden energy gshift to cut off energy, and protection power converter avoids being subject to the damage of excess temperature state.
Once ramp signal V rMPincrease constantly and exceed the second reference voltage V r2level time, secondary signal S 2to be enabled.The secondary signal S being enabled 2to carry out forbidden energy inhibit signal S by NAND gate 309 d.As long as the second input of NAND gate 309 receives the secondary signal S being disabled 2, thermal-shutdown circuit will be disabled.Therefore, thermal-shutdown circuit is by first signal S 1institute enables, and by secondary signal S 2institute's forbidden energy.
Fig. 7 shows according to the delay circuit 319 of the pwm circuit 50 of the embodiment of the present invention.Delay circuit 319 is essentially a counter, and it comprises the trigger 321,322 and 326 of series connection.The input end of clock ck of the trigger of these series connection receives oscillator signal PLS.The replacement input R receive delay signal S of the trigger of these series connection d.As inhibit signal S dwhile being enabled, oscillator signal PLS will drive these trigger devices to generate time of delay.In one embodiment of this invention, between transfer period, be 10 μ s, and it is 10ms time of delay.After time of delay, the reversed-phase output of trigger 326
Figure BSA00000345404200111
to generate low logic excess temperature signal S oT.As inhibit signal S dwhile being disabled, these triggers will be reset, and excess temperature signal S oTto again become high logic.
Fig. 8 shows the method that offers power converter over-temperature protection according to the embodiment of the present invention.First, generate switching signal (step 1001).Then, generate and drive signal with power switched switch according to described switching signal, use regulating power transducer (step 1002).Then, generate serrated signal (step 1003) in the down periods of described switching signal.Then,, in the time that described serrated signal exceedes the first reference voltage, enable thermal-shutdown circuit (step 1004).Then, adjust and drive signal (step 1005) according to the ambient temperature of described power converter.Then,, by more described driving signal and threshold voltage, after time of delay, generate excess temperature signal (step 1006) to enable inhibit signal.Finally, in the time that described serrated signal exceedes the second reference voltage, forbidden energy thermal-shutdown circuit (step 1007).In the switching signal down periods, drive signal to be adjusted to lower than a boundary level.Excess temperature signal is used for closing power converter.Described boundary level is used for avoiding power switch to be switched within the down periods of switching signal.The second reference signal level is greater than the first reference signal level.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, therefore protection scope of the present invention is to be as the criterion with claim of the present invention.

Claims (13)

1. the controller that over-temperature protection is provided, is applicable to power converter, comprising:
Commutation circuit, generates switching signal;
Drive circuit, is made up of high-pressure side transistor and low-pressure side transistor, and to generate driving signal, wherein, described driving signal is used for regulating described power converter;
Thermal-shutdown circuit, couples described drive circuit, and wherein, thermistor couples described drive circuit, and in the down periods of described switching signal, adjusts the described driving signal across described thermistor; And
Signal generator, controls described thermal-shutdown circuit; Wherein, described signal generator also couples described drive circuit, to drive described high-pressure side transistor and described low-pressure side transistor.
2. controller as claimed in claim 1, wherein, described thermal-shutdown circuit comprises:
Current source circuit, is enabled to provide current to described thermistor, adjusts the described driving signal across described thermistor with the described down periods in described switching signal according to the first signal that described signal generator was generated; And
Comparator, at described down periods comparative threshold voltage and the described driving signal of described switching signal, to generate excess temperature signal, wherein, described excess temperature signal is in order to drive signal to close described power converter described in forbidden energy.
3. controller as claimed in claim 2, wherein, described signal generator comprises:
Sawtooth circuit, generates the first driving signal and serrated signal according to described switching signal, and wherein, described first drives signal to be used for driving described high-pressure side transistor;
The first comparison circuit, more described serrated signal and the first reference voltage, with forbidden energy two driving signal, wherein, described two driving signal drives the falling edge of signal to be enabled according to described first, to drive described low-pressure side transistor;
Enable circuits, generates described first signal according to the falling edge of described two driving signal, and wherein, described first signal is used for enabling described thermal-shutdown circuit; And
The second comparison circuit, more described serrated signal and the second reference voltage, to enable secondary signal, wherein, described secondary signal is used for thermal-shutdown circuit described in forbidden energy.
4. controller as claimed in claim 1, wherein, described thermistor is thermistor, and when in the time that the ambient temperature of power converter described in the described down periods of described switching signal raises, the level of described switching signal reduces.
5. controller as claimed in claim 1, also comprises:
One clamped circuit, is enabled to be coupled to described thermistor, with the boundary level driving signal described in the described down periods strangulation of described switching signal.
6. the power converter that over-temperature protection is provided, comprising:
Transformer, has armature winding, secondary winding and auxiliary winding;
Power switch, couples the described armature winding of described transformer to regulate described power converter; And
Controller, has output, and to generate and to drive signal to switch described power switch according to switching signal, wherein, thermistor is coupled to the described output of described controller;
Wherein, in the down periods of described switching signal, described controller adjustment is across the described driving signal of described thermistor; And
Wherein, described controller comprises drive circuit, is made up of, to generate described driving signal high-pressure side transistor and low-pressure side transistor.
7. power converter as claimed in claim 6, wherein, described controller comprises:
Commutation circuit, generates described switching signal;
Thermal-shutdown circuit, is coupled to described thermistor, with the described down periods in described switching signal, adjusts the described driving signal across described thermistor; And
Clamped circuit, is enabled to be coupled to described thermistor, with the boundary level driving signal described in the described down periods strangulation of described switching signal.
8. power converter as claimed in claim 6, wherein, described thermistor is thermistor.
9. the method that over-temperature protection is provided, is applicable to power converter, comprising:
Generate switching signal;
Generate and drive signal with power switched switch according to described switching signal, use and regulate described power converter;
In the down periods of described switching signal, generate serrated signal;
In the time that described serrated signal exceedes the first reference voltage, enable thermal-shutdown circuit;
Adjust described driving signal according to the ambient temperature of described power converter;
More described driving signal and threshold voltage, to enable inhibit signal, are used and after time of delay, are generated excess temperature signal; And
In the time that described serrated signal exceedes the second reference voltage, thermal-shutdown circuit described in forbidden energy.
10. method as claimed in claim 9, wherein, in the described down periods of described switching signal, described driving signal is adjusted to lower than boundary level.
11. methods as claimed in claim 10, wherein, described boundary level is used for avoiding described power switch to be switched within the described down periods of described switching signal.
12. methods as claimed in claim 9, wherein, described excess temperature signal is used for disconnecting described power switch.
13. methods as claimed in claim 9, wherein, the level of described the second reference voltage is greater than the level of described the first reference voltage.
CN201010543816.0A 2010-11-15 2010-11-15 Controller, power converter and method for providing over-temperature protection Expired - Fee Related CN102005731B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010543816.0A CN102005731B (en) 2010-11-15 2010-11-15 Controller, power converter and method for providing over-temperature protection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010543816.0A CN102005731B (en) 2010-11-15 2010-11-15 Controller, power converter and method for providing over-temperature protection

Publications (2)

Publication Number Publication Date
CN102005731A CN102005731A (en) 2011-04-06
CN102005731B true CN102005731B (en) 2014-05-14

Family

ID=43812882

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010543816.0A Expired - Fee Related CN102005731B (en) 2010-11-15 2010-11-15 Controller, power converter and method for providing over-temperature protection

Country Status (1)

Country Link
CN (1) CN102005731B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI456382B (en) 2011-10-03 2014-10-11 Leadtrend Tech Corp Power supply, power management device applied to a power supply, and method for brown-out protection and over-heated protection of a power management device
CN103036454A (en) * 2011-10-08 2013-04-10 通嘉科技股份有限公司 Power supply, power management device and low-voltage and excess-temperature protective method
CN103580460B (en) * 2012-07-24 2016-06-15 杰力科技股份有限公司 Power supply change-over device
JP2014064392A (en) * 2012-09-21 2014-04-10 Sanken Electric Co Ltd Switching power supply device
TWI525973B (en) * 2012-11-02 2016-03-11 崇貿科技股份有限公司 Circuit of power converter with temperature control and method therefore
CN109905041A (en) * 2017-12-08 2019-06-18 神讯电脑(昆山)有限公司 Power supply device and its method for supplying power supply
CN111799761A (en) * 2020-06-24 2020-10-20 华源智信半导体(深圳)有限公司 Temperature protection method and circuit based on pin multiplexing
CN114024457B (en) * 2022-01-11 2022-05-13 深圳市创芯微微电子有限公司 Switching power supply circuit and power adapter
CN116382385B (en) * 2023-04-03 2024-03-05 无锡市稳先微电子有限公司 Temperature control method, temperature control circuit, intelligent electronic switch and automobile

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812677B2 (en) * 2001-08-21 2004-11-02 Intersil Americas Inc. Thermally compensated current sensing of intrinsic power converter elements
US6765372B2 (en) * 2001-12-14 2004-07-20 Intersil Americas Inc. Programmable current-sensing circuit providing continuous temperature compensation for DC-DC Converter
US6970339B2 (en) * 2004-04-27 2005-11-29 Texas Instruments Incorporated Current limit protection scheme for PWM buck converter with synchronous rectifier
CN100426617C (en) * 2005-10-14 2008-10-15 崇贸科技股份有限公司 Over-power protector capable of regulating over-current level
US8174243B2 (en) * 2007-03-19 2012-05-08 Semiconductor Components Industries, Llc Power supply controller and method therefor
US20110063877A1 (en) * 2009-09-16 2011-03-17 Ta-Yung Yang Synchronous rectifying circuit with primary-side swithching current detection for offline power converters
US8351227B2 (en) * 2010-01-22 2013-01-08 System General Corp. Switching controller for power converters

Also Published As

Publication number Publication date
CN102005731A (en) 2011-04-06

Similar Documents

Publication Publication Date Title
CN102005731B (en) Controller, power converter and method for providing over-temperature protection
CN104660022B (en) The system and method that overcurrent protection is provided for supply convertor
US7898114B2 (en) Protective circuit device for a solar module
TWI470911B (en) Switch converting circuit and converting method
US8649129B2 (en) Method and apparatus of providing over-temperature protection for power converters
US10491104B2 (en) Active clamp power converter and method of reducing shoot-through current during soft start
CN101552560B (en) Switch voltage stabilizing circuit and control method thereof
CN101867295B (en) Circuit and control method
US20160126718A1 (en) Semiconductor device
CN110719015A (en) Semiconductor switch in a protected switch mode power converter
CN110572020B (en) Control circuit and flyback switching power supply system
US9030848B2 (en) DC to DC converter
TWI429172B (en) Switching controller for power converters
CN109039027A (en) Multistage gate driving for cascode current sensing
JP2012157191A (en) Switching power supply device
US11716081B2 (en) Controller for controlling a GaN-based device and method for implementing the same
CN110165912B (en) Drive circuit of synchronous rectifier
KR102650677B1 (en) Power converter with active clamp
TWI422132B (en) Controllers, power converters and method for providing over-temperature protection
TW201843915A (en) Control Module with Active Snubber and Related Flyback Power Converting Device
US10536088B2 (en) Switched mode power supply controller
CN108736748B (en) Power conversion device and synchronous rectification controller thereof
US20190089264A1 (en) Synchronous rectifier circuit and switching power supply apparatus
JP2009050080A (en) Snubber circuit
CN212752133U (en) Synchronous rectification control circuit and switching power supply

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140514

Termination date: 20211115