CN102005361B - Forming method of aligned layer graphs on silicon wafer - Google Patents
Forming method of aligned layer graphs on silicon wafer Download PDFInfo
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- CN102005361B CN102005361B CN2009100578665A CN200910057866A CN102005361B CN 102005361 B CN102005361 B CN 102005361B CN 2009100578665 A CN2009100578665 A CN 2009100578665A CN 200910057866 A CN200910057866 A CN 200910057866A CN 102005361 B CN102005361 B CN 102005361B
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Abstract
The invention discloses a forming method of aligned layer graphs on a silicon wafer, which comprises: (1) a first dielectric layer is deposited on a silicon substrate, and an etching window is formed through photoetching; (2) a groove is etched in the etching window; (3) a layer of silicon oxide which is firstly deposited on the side wall and at the bottom of the groove is taken as a substrate oxidation layer, a layer of interlamination medium is deposited on the surface of the silicon wafer, and the groove is full of the interlamination medium at least; (4) the interlamination medium is grinded by adopting a chemical and mechanical grinding process; (5) the first dielectric layer is eliminated by adopting a wet method etching process, and a groove is formed on the surface of the silicon wafer again at the position of the original groove; and (6) a layer of polycrystalline silicon is deposited on the surface of the silicon wafer, a second dielectric layer is deposited, and the upper surface of the deposited polycrystalline silicon is provided with a downwards concave step, i.e. the aligned layer graphs. The forming method can be used for saving the manufacturing process and the manufacturing time of the aligned layer graphs, and a photoetching machine can clearly identify the aligned layer graphs on the silicon wafer.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing process, particularly relate in a kind of photoetching process by the formation method of alignment figure.
Background technology
Photoetching is the technical process that the circuit structure of the last graphic form of mask (mask) is transferred to the silicon chip surface that scribbles photoresist through steps such as aligning, exposure, developments.Photoetching process can form one deck photoresist masking figure (litho pattern) at silicon chip surface, and its subsequent technique is that etching or ion inject.
The manufacturing of any semiconductor device all comprises the photoetching process of multistep; Except that first step photoetching; The litho pattern of current layer all will be measured with the alignment precision of being undertaken by the alignment figure of anterior layer during later per step photoetching, guarantees between the multistep photoetching aligning of figure on the silicon chip.
At present, comprised the steps: by the formation method of alignment figure on the silicon chip
The 1st step saw also Fig. 1 a, and deposit one deck silicon nitride 11 on silicon substrate 10 adopts photoetching process to form etching window 13 more earlier.
The 2nd step saw also Fig. 1 b, in etching window 13, etched groove 14, and the bottom of groove 14 is dropped in the silicon substrate 10, removed photoresist 12 after etching is accomplished.Groove 14 is exactly the overlay mark of this layer pattern on the silicon chip, and this overlay mark possibly be a kind of lines or shape (like square annular, cross etc.) from the silicon chip vertical view, but is exactly groove from the silicon chip cutaway view.By the alignment figure is the silicon slice pattern that on the overlay mark basis, forms.
The 3rd step saw also Fig. 1 c, adopted depositing technics growth one deck silica as cushion oxide layer 15 in the sidewall and the bottom of groove 14 earlier, and is again at silicon chip surface deposit one deck silica 16, full to 14 fillings of major general's groove.
The 4th step saw also Fig. 1 d, adopted cmp (CMP) technology to grind silica 16, until silica 16 and silicon nitride 11 flush.
The 5th step saw also Fig. 1 e, adopted wet corrosion technique to remove silicon nitride 11, and this moment, the cushion oxide layer 15 of part also was removed with silica 16, and silicon chip surface has formed more shallow groove again in the position of the groove 14 in the 2nd step.
The 6th step saw also Fig. 1 f, adopted photoetching process to form once more and identical etching window 13 of the 1st step, and in etching window 13 etching once more, etch than darker groove of the 5th step in the position of the groove 14 in the 2nd step, etching is accomplished back removal photoresist 12.Why will carry out etching to overlay mark (being groove 14 positions) once more, be to be identified more easily and to measure in order to make by the edge of alignment figure.
In the 7th step, see also Fig. 1 g, at silicon chip surface deposit one deck polysilicon 17.This one deck polysilicon 17 is used to carry out the photoetching of a new layer pattern as the material of a layer pattern new on the silicon chip.Polysilicon 17 is exactly by the alignment figure, and this moment, polysilicon 17 upper surfaces recessed step occurred at groove 14 corresponding positions, and this is a benchmark of measuring alignment precision.
The 8th step saw also Fig. 1 h, at silicon chip surface spin coating photoresist 18, adopted photoetching process to form new one deck litho pattern.
At this moment, the current layer figure just need and be carried out the measurement of alignment precision between the alignment figure.Usually the method for measuring alignment precision is: measure current layer figure (promptly forming the photoresist 18 of new one deck litho pattern) edge and by the distance between alignment figure (being the recessed ledge frame of the polysilicon 17 upper surfaces) edge, calculate alignment precision again.
By the formation method of alignment figure, need carry out Twi-lithography technology on the above-mentioned silicon chip, this has increased the cost of technology, and makes manufacturing time longer.
Summary of the invention
Technical problem to be solved by this invention provides on a kind of silicon chip by the formation method of alignment figure; This method only needs a photoetching process can form by the alignment figure, and formedly can more easily be identified and measure the edge by the alignment figure.
For solving the problems of the technologies described above, comprised the steps: by the formation method of alignment figure on the silicon chip of the present invention
The 1st step, first deposit one deck first dielectric layer on silicon substrate, photoetching forms etching window again;
The 2nd step etched groove in etching window, the bottom of groove is dropped in the silicon substrate, removed photoresist after etching is accomplished;
The 3rd step, earlier at the sidewall of groove and deposit one deck silica as cushion oxide layer, again at silicon chip surface deposit one deck inter-level dielectric, said inter-level dielectric to major general's trench fill is completely;
In the 4th step, adopt chemical mechanical milling tech to grind inter-level dielectric, until the inter-level dielectric and the first dielectric layer flush;
The 5th step, adopt wet corrosion technique to remove first dielectric layer, this moment, the cushion oxide layer and the inter-level dielectric of part also were removed, and silicon chip surface forms groove once more in the primitive groove groove location;
The 6th step is at silicon chip surface elder generation deposit one deck polysilicon, deposit one deck second dielectric layer again.The upper surface of institute's deposit polysilicon has recessed ledge frame, is by the alignment figure.This recessed ledge frame is corresponding up and down on the position with the groove of the 5th step formation.Said polysilicon is used to carry out the photoetching of a new layer pattern as the material of a layer pattern new on the silicon chip.
Compared with existing method by the formation method of alignment figure on the silicon chip of the present invention; Cancelled deepening etching the second time of overlay mark (groove position); But after new one deck graphic material (polysilicon) deposit, increased deposit one deck second dielectric layer; Second dielectric layer plays the effect of magnifying glass, can make mask aligner more easily, more clearly pick out the overlay mark on the silicon chip.
Description of drawings
Fig. 1 a to Fig. 1 h is by each step sketch map of the formation method of alignment figure on the existing silicon chip;
Fig. 2 a to Fig. 2 g is by each step sketch map of the formation method of alignment figure on the silicon chip of the present invention.
Description of reference numerals among the figure:
10 is silicon substrate; 11 is silicon nitride; 12 is photoresist; 13 is etching window; 14 is groove; 15 is cushion oxide layer; 16 is silica; 17 is polysilicon; 18 is photoresist; 20 is silicon substrate; 21 is first dielectric layer; 22 is photoresist; 23 is etching window; 24 is groove; 25 is cushion oxide layer; 26 is inter-level dielectric; 27 is polysilicon; 28 is second dielectric layer; 29 is photoresist.
Embodiment
Comprised the steps: by the formation method of alignment figure on the silicon chip of the present invention
The 1st step saw also Fig. 2 a, and first deposit one deck first dielectric layer 21, the first dielectric layers 21 can be silica (SiO on silicon substrate or polysilicon 20
2), silicon nitride (Si
3N
4), silicon oxynitride (SiO
xN
y, x and y are natural number) etc.Spin coating photoresist 22 on first dielectric layer 21 forms litho pattern fenetre mouth 23 at once with photoetching process exposure, the back of developing again.If this is the photoetching first on the silicon chip, then be silicon substrate 20; If this is the second time or photoetching later on the silicon chip, then is polysilicon 20.
The 2nd step saw also Fig. 2 b, in etching window 23, etched groove 24, and groove 24 runs through first dielectric layer 21, and the bottom of groove 24 is dropped in silicon substrate or the polysilicon 20, removed photoresist 22 after etching is accomplished.
The 3rd step; See also Fig. 2 c, earlier at the sidewall of groove 24 and deposit one deck silica as cushion oxide layer 25, again at silicon chip surface deposit one deck inter-level dielectric 26; Inter-level dielectric 26 can be silica, silicon nitride, silicon oxynitride etc., and inter-level dielectric 26 to major general's groove 24 is filled full.The deposit of cushion oxide layer 25 can form etching window 23 by photoetching process earlier, silicon oxide deposition again, and the step of removing photoresist again forms.
The 4th step saw also Fig. 2 d, adopted chemical mechanical milling tech to grind inter-level dielectric 26, until inter-level dielectric 26 and first dielectric layer, 21 flush.
The 5th step saw also Fig. 2 e, adopted wet corrosion technique to remove first dielectric layer 21.At this moment, the cushion oxide layer 25 of part also is removed with inter-level dielectric 26, sees from the silicon chip section to have formed the shallow groove of the former groove of depth ratio 24 again in the position of groove 24.
The 6th step saw also Fig. 2 f, at silicon chip surface elder generation deposit one deck polysilicon 27, deposit one deck second dielectric layer 28 again.Polysilicon 27 is used to carry out the photoetching of a new layer pattern as the material of a layer pattern new on the silicon chip.Polysilicon layer 27 is exactly by alignment.Because former groove 24 positions, the 5th step back have formed shallow trench again, so the recessed ledge frame that occurred in the position of corresponding up and down (finishing watching full weight with depression angle closes) of the upper surface of polysilicon layer 27, Here it is by the alignment figure.Second dielectric layer 28 can be silica, silicon nitride, silicon oxynitride etc.The deposition thickness of second dielectric layer 28 can be 30～1000 μ m, is preferably 30～500 μ m.
The 7th step saw also Fig. 2 g, at silicon chip surface spin coating photoresist 29, adopted photoetching process to form new one deck litho pattern.At this moment; The current layer litho pattern just need and be carried out the measurement of alignment precision between the alignment figure; Promptly measure current layer figure (promptly forming the photoresist 29 of new one deck litho pattern) edge earlier and, calculate alignment precision again by the distance between alignment figure (being the recessed ledge frame of the polysilicon 27 upper surfaces) edge.
Want accurate measurement pattern edge, current layer figure and all need be had certain strength of figure by the alignment figure.Strength of figure is mainly by following physical quantity decision: n*d/ λ.Wherein n is the refractive index of graphics environment, and d is the shoulder height of figure, and λ is for measuring light wavelength.Usually the wavelength X of measuring light is certain.
As far as the current layer figure, owing to be that direct photoetching forms, shoulder height d is exactly a photoresist thickness, usually big (between 0.2 μ m to 10 μ m); Refractive index n is exactly the refractive index of air; Therefore n*d/ λ is bigger, and the current layer figure has good strength of figure, can accurately measure its edge.
As far as by the alignment figure, owing to be to be deposited on the overlay mark of groove shape, be the recessed ledge frame degree of depth of illuvium upper surface by the shoulder height d of alignment, less usually (between 0.01 μ m to 0.5 μ m).The present invention is through deposit one second dielectric layer 28 again on by alignment (polysilicon 27), thereby improved refractive index n.Though lower by the shoulder height d of alignment figure like this, refractive index n is bigger, therefore the size balance of n*d/ λ is also had good strength of figure by the alignment figure, can accurately measure its edge.Second dielectric layer 28 has been equivalent to play the effect of magnifying glass owing to have the refractive index n higher than air when measuring alignment precision.
In sum, by the formation method of alignment figure, only adopt a photoetching process can form by the alignment figure on the silicon chip of the present invention, technology is simple, practices thrift cost.Formedly can also be made things convenient for, be identified preparatively, thereby can accurately be used for the measurement of alignment precision by the alignment figure.
Claims (5)
- On the silicon chip by the formation method of alignment, it is characterized in that, comprise the steps:The 1st step, first deposit one deck first dielectric layer on silicon substrate, photoetching forms etching window again;The 2nd step etched groove in etching window, the bottom of groove is dropped in the silicon substrate, removed photoresist after etching is accomplished;The 3rd step, earlier at the sidewall of groove and deposit one deck silica as cushion oxide layer, again at silicon chip surface deposit one deck inter-level dielectric, said inter-level dielectric to major general's trench fill is completely;In the 4th step, adopt the direct chemical mechanical milling tech to grind inter-level dielectric, until the inter-level dielectric and the first dielectric layer flush;The 5th step, adopt wet corrosion technique to remove first dielectric layer, this moment, the cushion oxide layer and the inter-level dielectric of part also were removed, and silicon chip surface forms groove once more in the primitive groove groove location;The 6th step is at silicon chip surface elder generation deposit one deck polysilicon, deposit one deck second dielectric layer again; The upper surface of institute's deposit polysilicon has recessed ledge frame, is by the alignment figure; This recessed ledge frame is corresponding up and down on the position with the groove of the 5th step formation; Said polysilicon is used to carry out the photoetching of a new layer pattern as the material of a layer pattern new on the silicon chip.
- 2. by the formation method of alignment figure, it is characterized in that on the silicon chip according to claim 1 that said method is in the 6th step, the thickness of the said second dielectric layer deposit is 30 μ m to 1000 μ m.
- 3. by the formation method of alignment figure, it is characterized in that on the silicon chip according to claim 1 that said method is in the 6th step, the thickness of the said second dielectric layer deposit is 30 μ m to 500 μ m.
- 4. by the formation method of alignment figure, it is characterized in that on the silicon chip according to claim 1 that in the said method, first dielectric layer, inter-level dielectric, second dielectric layer are silica, silicon nitride or silicon oxynitride.
- 5. by the formation method of alignment figure, it is characterized in that the gash depth that the gash depth that said the 5th step of method forms formed less than said the 2nd step of method on the silicon chip according to claim 1.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103107115B (en) * | 2011-11-09 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | A kind of etching control method |
| CN103311092B (en) * | 2012-03-12 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | The lithographic method of groove |
| CN103377980B (en) * | 2012-04-17 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Fleet plough groove isolation structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| CN1458667A (en) * | 2002-05-17 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for producing alignment mark |
| US6979651B1 (en) * | 2002-07-29 | 2005-12-27 | Advanced Micro Devices, Inc. | Method for forming alignment features and back-side contacts with fewer lithography and etch steps |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| CN1458667A (en) * | 2002-05-17 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for producing alignment mark |
| US6979651B1 (en) * | 2002-07-29 | 2005-12-27 | Advanced Micro Devices, Inc. | Method for forming alignment features and back-side contacts with fewer lithography and etch steps |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140107 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140107 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |