CN101996113A - Method and device for identifying cause of system reset - Google Patents
Method and device for identifying cause of system reset Download PDFInfo
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- CN101996113A CN101996113A CN2009101675234A CN200910167523A CN101996113A CN 101996113 A CN101996113 A CN 101996113A CN 2009101675234 A CN2009101675234 A CN 2009101675234A CN 200910167523 A CN200910167523 A CN 200910167523A CN 101996113 A CN101996113 A CN 101996113A
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Abstract
The invention provides a method for identifying a cause of system reset, which comprises the following steps of: monitoring the change of system power supply voltage, and generating a RESET signal and a web data object (WDO) signal; delaying the RESET signal; and identifying the cause of the system reset according to the WDO signal and the delayed RESET signal. The invention also provides a device for identifying the cause of system reset, which comprises a power supply voltage monitoring module used for monitoring the change of the system power supply voltage and generating a RESET signal and a WDO signal, and an identifying module used for delaying the RESET signal and identifying the causes of the system reset according to a relative potential relationship of the WOD signal and the delayed RESET signal. The method and the system can easily and reliably identify the cause of system reset, namely power on reset or charged reset, so as to improve the reliability of communication electronic equipment.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of reason recognition methods and device of system reset.
Background technology
In communication electronic equipment manufacturing field, no matter be equipment R﹠D process or equipment use, all need the reason that a kind of method knows that system reset is restarted: be because re-powering institute after the power down causes (this kind situation is called electrification reset), or CPU or appliance circuit detect the device reset (this kind situation is called charged resetting) that triggers after the unit exception under the situation of not power down.The reset circuit of correct recognition system not only helps to design research staff's defective or the mistake of discovering device aspect system design and relative program early; shorten product design R﹠D process and constant product quality cycle; also help the location fast of safeguarding in the use at equipment of support staff after sale, it is unusual or equipment operation is unusual in time to get rid of the functions of the equipments that caused by working environment supply voltage shakiness.
At present, whether the method that mainly adopts internal memory to combine identification with CPLD (CPLD) discerns electrification reset.A special read-only register is set in CPLD; System reset, CPU reads the value of this register, and is saved in the internal memory; CPLD this register of resetting; CPU comes whether electrification reset of compartment system according to the value in the internal memory.This method requires above-mentioned register under electrification reset and charged reset case different values to be arranged, this register value zero clearing during electrification reset, and the value of this register is constant during charged resetting, the setting before the hold reset.
The inventor finds that there is following problem at least in prior art: because charged the resetting of system also needs to reset simultaneously CPLD sometimes, its internal register all returned to initial default value when CPLD resetted, and this charged situation about resetting will be mistaken as system power-on reset.This recognition methods causes erroneous judgement disconnected easily, and reliability is lower, and there is limitation in range of application.
Summary of the invention
The present invention aims to provide a kind of reason recognition methods and device of system reset, causes erroneous judgement disconnected easily to solve prior art, and reliability is lower, and there is circumscribed problem in range of application.
According to an aspect of the present invention, provide a kind of reason recognition methods of system reset, having comprised: the variation of supervision system power voltage, and produce RESET signal and WDO signal; The RESET signal is delayed time; According to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the reason that recognition system resets.
Preferably, according to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the reason that recognition system resets specifically comprises: according to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the value of register is set; According to the value of register, the reason that recognition system resets.
Preferably, according to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the value that register is set specifically comprises: at the rising edge of WDO signal, the RESET signal after the time-delay is sampled; Whether the current potential of judging the RESET signal that sampling obtains is electronegative potential; If the value that register then is set is the electrification reset discre value, the electrification reset discre value represents that the reason of system reset is an electrification reset; If not, the value that then keeps register.
Preferably, according to the value of register, the reason that recognition system resets specifically comprises: the value that reads register; Whether judgment value is the electrification reset discre value; If determine that then the reason of system reset is an electrification reset; If not, then the reason of definite system reset is charged resetting.
Preferably, register is a read-only register.
Preferably, the value of register reverts to initial default value after system reset, and the electrification reset discre value is different with initial default value.
According to another aspect of the present invention, also provide a kind of reason recognition device of system reset, having comprised: the supply voltage monitoring module is used for the variation of supervision system power voltage, and produces RESET signal and WDO signal; Identification module is used for the RESET signal is delayed time, and according to the current potential relativeness of RESET signal after WDO signal and the time-delay, the reason that recognition system resets.
Preferably, the supply voltage monitoring module is a μ P supply voltage monitoring chip.
Preferably, identification module comprises: CPLD is used for the RESET signal is delayed time, and according to the current potential relativeness of RESET signal after WDO signal and the time-delay, the value of register is set; Processing unit is used for the value according to register, the reason that recognition system resets.
Preferably, CPLD is delayed time to the RESET signal, and according to the current potential relativeness of RESET signal after WDO signal and the time-delay, the value that register is set specifically comprises: the RESET signal is delayed time; At the rising edge of WDO signal, the RESET signal after the time-delay is sampled; Whether the current potential of judging the RESET signal that sampling obtains is electronegative potential; If the value that register then is set is the electrification reset discre value, the electrification reset discre value represents that the reason of system reset is an electrification reset; If not, the value that then keeps register.
Preferably, register is a read-only register, and the value of register reverts to initial default value after system reset, and the electrification reset discre value is different with initial default value.
Preferably, processing unit is according to the value of register, and the reason that recognition system resets specifically comprises: the value that reads register; Whether judgment value is the electrification reset discre value; If determine that then the reason of system reset is an electrification reset; If not, then the reason of definite system reset is charged resetting.
Preferably, processing unit is CPU.
In the present invention, because the output signal by detection supply voltage monitoring module (μ P supply voltage monitoring chip) is restarted the reason that wave form varies in the reseting procedure is known this device reset at equipment, having solved prior art causes erroneous judgement disconnected easily, reliability is lower, there is circumscribed problem in range of application, thereby has improved the reliability of communication electronic equipment.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 shows the process flow diagram according to the reason recognition methods of the system reset of the embodiment of the invention;
Fig. 2 shows the synoptic diagram according to the reason recognition device of the system reset of the embodiment of the invention;
Fig. 3 shows the synoptic diagram according to the reason recognition device of the system reset of the preferred embodiment of the present invention one;
Fig. 4 shows according to the output signal of the μ P supply voltage monitoring chip of the preferred embodiment of the present invention one oscillogram in the electrification reset situation;
Fig. 5 shows according to the μ P supply voltage monitoring chip output signal of the preferred embodiment of the present invention one oscillogram in the watchdog reset situation;
Fig. 6 shows the process flow diagram according to the reason recognition methods of the system reset of the preferred embodiment of the present invention one.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Fig. 1 shows the process flow diagram according to the reason recognition methods of the system reset of the embodiment of the invention, comprising:
Step S10, the variation of supervision system power voltage, and produce RESET signal and WDO signal;
Step S20 delays time to the RESET signal;
Step S30 is according to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the reason that recognition system resets.
The preferred embodiment is owing to restart the reason that wave form varies in the reseting procedure is known this device reset by the output signal of detection supply voltage monitoring module (μ P supply voltage monitoring chip) at equipment, having solved prior art causes erroneous judgement disconnected easily, reliability is lower, there is circumscribed problem in range of application, thereby has improved the reliability of communication electronic equipment.μ P supply voltage monitoring chip has been widely used in electronic device field at present very much, realizes supply voltage monitoring function and watchdog function.
Preferably, step S30 specifically comprises: according to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the value of register is set; According to the value of register, the reason that recognition system resets.
Wherein, according to the current potential relativeness of the RESET signal after WDO signal and the time-delay, the value that register is set specifically comprises: at the rising edge of WDO signal, the RESET signal after the time-delay is sampled; Whether the current potential of judging the RESET signal that sampling obtains is electronegative potential; If the value that register then is set is the electrification reset discre value, the electrification reset discre value represents that the reason of system reset is an electrification reset; If not, the value that then keeps register.
According to the value of register, the reason that recognition system resets specifically comprises: the value that reads register; Whether judgment value is the electrification reset discre value; If determine that then the reason of system reset is an electrification reset; If not, then the reason of definite system reset is charged resetting.
The preferred embodiment provides the current potential relativeness according to the RESET signal after WDO signal and the time-delay, the specific embodiments of the reason that recognition system resets.By a specified register is set in CPLD, system reset, CPLD is saved in distinguishing mark (electrification reset discre value) in this specified register, and CPU reads the value of this register, can be worth whether electrification reset of compartment system according to this.
Preferably, register is a read-only register.The read operation of a register response external can not write.Like this, distinguishing mark is kept in the register, no matter whether running software catastrophic failure occurs, and distinguishing mark can be by maloperation, and the value of register is positioning system electrification reset whether exactly.
Preferably, the value of register reverts to initial default value after system reset, and the electrification reset discre value is different with initial default value.Like this, can the compartment system reset circuit be electrification reset or charged resetting.
Fig. 2 shows the synoptic diagram according to the reason recognition device of the system reset of the embodiment of the invention, and this device comprises: supply voltage monitoring module 10 is used for the variation of supervision system power voltage, and produces RESET signal and WDO signal; Identification module 20 is used for the RESET signal is delayed time, and according to the current potential relativeness of RESET signal after WDO signal and the time-delay, the reason that recognition system resets.
Preferably, the supply voltage monitoring module is a μ P supply voltage monitoring chip.
The preferred embodiment is owing to restart the reason that wave form varies in the reseting procedure is known this device reset by the output signal of detection supply voltage monitoring module (μ P supply voltage monitoring chip) at equipment, having solved prior art causes erroneous judgement disconnected easily, reliability is lower, there is circumscribed problem in range of application, thereby has improved the reliability of communication electronic equipment.μ P supply voltage monitoring chip has been widely used in electronic device field at present very much, realizes supply voltage monitoring function and watchdog function.
Preferably, identification module 20 comprises: CPLD 201 is used for the RESET signal is delayed time, and according to the current potential relativeness of RESET signal after WDO signal and the time-delay, the value of register is set; Processing unit 202 is used for the value according to register, the reason that recognition system resets.
Wherein, 201 pairs of RESET signals of CPLD are delayed time, and according to the current potential relativeness of RESET signal after WDO signal and the time-delay, the value that register is set specifically comprises: the RESET signal is delayed time; At the rising edge of WDO signal, the RESET signal after the time-delay is sampled; Whether the current potential of judging the RESET signal that sampling obtains is electronegative potential; If the value that register then is set is the electrification reset discre value, the electrification reset discre value represents that the reason of system reset is an electrification reset; If not, the value that then keeps register.
CPLD possesses the function of automatic recognition system electrification reset, and the system for the existing supply voltage monitoring chip in periphery need not to increase the additional hardware cost, can simple and reliable ground distinguishing system be electrification reset or charged resetting just.
Preferably, register is a read-only register, and the value of register reverts to initial default value after system reset, and the electrification reset discre value is different with initial default value.Like this, distinguishing mark is kept in the register, no matter whether running software catastrophic failure occurs, and distinguishing mark can be by maloperation, and the value of register is positioning system electrification reset whether exactly.
Processing unit 202 is according to the value of register, and the reason that recognition system resets specifically comprises: the value that reads register; Whether judgment value is the electrification reset discre value; If determine that then the reason of system reset is an electrification reset; If not, then the reason of definite system reset is charged resetting.Preferably, processing unit 202 is CPU.
Above preferred embodiment provides the current potential relativeness of identification module according to the RESET signal after WDO signal and the time-delay, the specific embodiments of the reason that recognition system resets.By a specified register is set in CPLD, system reset, CPLD is saved in distinguishing mark (electrification reset discre value) in this specified register, and CPU reads the value of this register, can be worth whether electrification reset of compartment system according to this.
Fig. 3 shows the synoptic diagram according to the reason recognition device of the system reset of the preferred embodiment of the present invention one.This device comprises μ P supply voltage monitoring chip, CPLD and CPU.When carrying out Hardware Design, in advance the RESET and the WDO signal of μ P supply voltage monitoring chip are all introduced among the CPLD, as the input signal of CPLD.An eight bit register is set in CPLD, and this register initial default value is 0, and the read operation of this register response external, can not write.CPLD possesses the function of automatic recognition system electrification reset, specifically describes as follows:
1) time-delay: the RESET signal is delayed time slightly, guarantee that the RESET signal is in a stable potential state when the rising edge of WDO arrives, do not have the situation of sudden change, thereby guarantee the RESET sampled signal accurately and reliably, also guarantee the reliability of follow-up automatic identification indirectly.
2) sampling identification: the rising edge at the WDO signal is sampled to the RESET signal after delaying time.In conjunction with Fig. 4 and Fig. 5, can make as judging: so this time to reset must be electrification reset if the RESET signal that obtains of sampling is an electronegative potential.
3) be provided with: in the system reset start-up course, if CPLD recognize system power-on reset just the value of register be set to 0x55.0x55 is the electrification reset discre value, in the application of reality, the discre value of electrification reset can also be 0xAA etc. other be different from the value of 0x00 (initial default value of register).
It should be noted that in the application of reality the register of use can also be register of 4 or 12 etc.
Fig. 6 shows the process flow diagram according to the reason recognition methods of the system reset of the preferred embodiment of the present invention one, may further comprise the steps:
Step S102, μ P supply voltage monitoring chip monitoring power voltage produces RESET signal and WDO signal, system reset, system reset comprise electrification reset and charged resetting, during system reset, CPLD also is reset, the wherein value of eight bit register meeting zero clearing, and promptly value is 0x00;
Step S104, CPLD delays time to the RESET signal, and at the rising edge of WDO signal the RESET signal after postponing is sampled;
Step S106 judges whether the RESET signal that sampling obtains is electronegative potential;
Step S108 is if then the value of register is set to 0x55;
Step S110 if not, does not then change the value of register;
Step S112, CPU read the value of register;
Step S114, CPU judge that the value of register is 0x55 or 0x00;
Step S116, if 0x55, then the recognition system reset circuit is an electrification reset;
Step S118, if 0x00, then the recognition system reset circuit is charged resetting.
Above-mentioned steps S104 is a cyclic process to step S118, and each system reset all once circulates.
From above description, as can be seen, the present invention has realized following technique effect: owing to restart the reason that wave form varies in the reseting procedure is known this device reset by the output signal of detection supply voltage monitoring module (μ P supply voltage monitoring chip) at equipment, having solved prior art causes erroneous judgement disconnected easily, reliability is lower, there is circumscribed problem in range of application, the reason that can simple and reliable ground recognition system resets is electrification reset or charged resetting, thereby has improved the reliability of communication electronic equipment.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the memory storage and carry out by calculation element, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. the reason recognition methods of a system reset is characterized in that, comprising:
The variation of supervision system power voltage, and produce RESET signal and WDO signal;
Described RESET signal is delayed time;
According to the current potential relativeness of the described RESET signal after described WDO signal and the time-delay, the reason that recognition system resets.
2. method according to claim 1 is characterized in that, according to the current potential relativeness of the described RESET signal after described WDO signal and the time-delay, the reason that recognition system resets specifically comprises:
According to the current potential relativeness of the described RESET signal after described WDO signal and the time-delay, the value of register is set;
According to the value of described register, the reason that recognition system resets.
3. method according to claim 2 is characterized in that, according to the current potential relativeness of the described RESET signal after described WDO signal and the time-delay, the value that register is set specifically comprises:
At the rising edge of described WDO signal, the described RESET signal after the time-delay is sampled;
Whether the current potential of judging the described RESET signal that sampling obtains is electronegative potential;
If the value that register then is set is the electrification reset discre value, described electrification reset discre value represents that the reason of system reset is an electrification reset;
If not, the value that then keeps described register.
4. method according to claim 3 is characterized in that, according to the value of described register, the reason that recognition system resets specifically comprises:
Read the value of described register;
Judge whether described value is described electrification reset discre value;
If determine that then the reason of system reset is an electrification reset;
If not, then the reason of definite system reset is charged resetting.
5. method according to claim 3 is characterized in that, described register is a read-only register.
6. method according to claim 3 is characterized in that the value of described register reverts to initial default value after system reset, and described electrification reset discre value is different with described initial default value.
7. the reason recognition device of a system reset is characterized in that, comprising:
The supply voltage monitoring module is used for the variation of supervision system power voltage, and produces RESET signal and WDO signal;
Identification module is used for described RESET signal is delayed time, and according to the current potential relativeness of described RESET signal after described WDO signal and the time-delay, the reason that recognition system resets.
8. device according to claim 7 is characterized in that, described supply voltage monitoring module is a μ P supply voltage monitoring chip.
9. device according to claim 7 is characterized in that, described identification module comprises:
CPLD is used for described RESET signal is delayed time, and according to the current potential relativeness of described RESET signal after described WDO signal and the time-delay, the value of register is set;
Processing unit is used for the value according to described register, the reason that recognition system resets.
10. device according to claim 9, it is characterized in that, described CPLD is delayed time to described RESET signal, and according to the current potential relativeness of described RESET signal after described WDO signal and the time-delay, the value that register is set specifically comprises:
Described RESET signal is delayed time;
At the rising edge of described WDO signal, the described RESET signal after the time-delay is sampled;
Whether the current potential of judging the described RESET signal that sampling obtains is electronegative potential;
If the value that register then is set is the electrification reset discre value, described electrification reset discre value represents that the reason of system reset is an electrification reset;
If not, the value that then keeps described register.
11. device according to claim 10 is characterized in that, described register is a read-only register, and the value of described register reverts to initial default value after system reset, and described electrification reset discre value is different with described initial default value.
12. device according to claim 10 is characterized in that, described processing unit is according to the value of described register, and the reason that recognition system resets specifically comprises;
Read the value of described register;
Judge whether described value is described electrification reset discre value;
If determine that then the reason of system reset is an electrification reset;
If not, then the reason of definite system reset is charged resetting.
13. device according to claim 12 is characterized in that, described processing unit is CPU.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910167523.4A CN101996113B (en) | 2009-08-21 | 2009-08-21 | Method and device for identifying cause of system reset |
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| CN200910167523.4A CN101996113B (en) | 2009-08-21 | 2009-08-21 | Method and device for identifying cause of system reset |
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| CN101996113A true CN101996113A (en) | 2011-03-30 |
| CN101996113B CN101996113B (en) | 2015-05-20 |
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| CN200910167523.4A Expired - Fee Related CN101996113B (en) | 2009-08-21 | 2009-08-21 | Method and device for identifying cause of system reset |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102591734A (en) * | 2011-12-31 | 2012-07-18 | 中兴通讯股份有限公司 | Method and device for detecting reset type of system |
| CN104092589A (en) * | 2014-07-24 | 2014-10-08 | 南车株洲电力机车研究所有限公司 | Network module and monitoring method for resetting of network module |
| CN104142726A (en) * | 2013-05-09 | 2014-11-12 | 中国科学院微电子研究所 | Chip and chip reset protection method |
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| CN1776566A (en) * | 2005-11-25 | 2006-05-24 | 港湾网络有限公司 | Method for distinguishing system power-on reset and live-line reset |
| CN2824125Y (en) * | 2005-08-11 | 2006-10-04 | 中兴通讯股份有限公司 | Watchdog reset circuit |
| CN201021986Y (en) * | 2007-03-08 | 2008-02-13 | 杭州华三通信技术有限公司 | Door guard reset circuit |
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Patent Citations (3)
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| CN2824125Y (en) * | 2005-08-11 | 2006-10-04 | 中兴通讯股份有限公司 | Watchdog reset circuit |
| CN1776566A (en) * | 2005-11-25 | 2006-05-24 | 港湾网络有限公司 | Method for distinguishing system power-on reset and live-line reset |
| CN201021986Y (en) * | 2007-03-08 | 2008-02-13 | 杭州华三通信技术有限公司 | Door guard reset circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102591734A (en) * | 2011-12-31 | 2012-07-18 | 中兴通讯股份有限公司 | Method and device for detecting reset type of system |
| CN104142726A (en) * | 2013-05-09 | 2014-11-12 | 中国科学院微电子研究所 | Chip and chip reset protection method |
| CN104142726B (en) * | 2013-05-09 | 2020-04-14 | 中国科学院微电子研究所 | Chip reset protection method and chip |
| CN104092589A (en) * | 2014-07-24 | 2014-10-08 | 南车株洲电力机车研究所有限公司 | Network module and monitoring method for resetting of network module |
| CN104092589B (en) * | 2014-07-24 | 2017-06-30 | 南车株洲电力机车研究所有限公司 | The monitoring method that a kind of mixed-media network modules mixed-media and mixed-media network modules mixed-media reset |
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| CN101996113B (en) | 2015-05-20 |
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