CN104991832A - Method for processing shutdown of embedded processor - Google Patents
Method for processing shutdown of embedded processor Download PDFInfo
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- CN104991832A CN104991832A CN201510344469.1A CN201510344469A CN104991832A CN 104991832 A CN104991832 A CN 104991832A CN 201510344469 A CN201510344469 A CN 201510344469A CN 104991832 A CN104991832 A CN 104991832A
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Abstract
The present invention relates to the field of embedded systems, and provides a method that is based on joint detection of hardware and software and that processes shutdown of an embedded processor. Provided by the invention is a novel post processing means for processor shutdown, and the adjustability of the embedded system is strengthened so as to facilitate accurate and high-efficient locating of complex problems like the embedded processor shutdown.
Description
Technical field
The present invention relates to embedded system field, particularly relate to and a kind ofly jointly detect based on hardware and software and process machine of the delaying exception method of flush bonding processor.
Background technology
If the software in flush bonding processor is in operation, and fatal exception occurs, processor can be made to delay machine, and cause control end software to access, the Debugging message on processor cannot obtain.Especially, under the formal product running environment departing from hardware emulator, flush bonding processor, when delaying machine, lacks the running software record that means obtain processor, is not easy to analyze machine of the delaying reason of processor.
Commonly delay machine treatment scheme as shown in Figure 1, in this flow process, the reset of processor destroys first when delaying machine and runs on-the-spot, cannot analyze abnormal cause; And this flow process often needs a large amount of beta versions to attempt, could orientation problem.
Summary of the invention
For solving the above-mentioned problems in the prior art, the embodiment of the present invention provides on the one hand a kind of flush bonding processor and to delay the disposal route of machine, and method comprises:
Use software survival to be detected as the judgement whether subsequent processor survive and the first foundation is provided;
Use hardware survival to be detected as the judgement whether subsequent processor survive and the second foundation is provided;
Processor survival judges to determine whether processor survives according to the testing result of software restraint;
Processor warm reset carries out force revert to the machine of delaying, but does not destroy the running environment of processor;
Processor is according to hardware characteristics, and decision runs machine post processor of delaying, or rerun normal procedure.
Machine post processor of delaying is for re-establishing the communication link with control end;
Machine post processor of the delaying internal memory after machine of being delayed by processor sends control end to;
When linking normal procedure, retaining one section of internal memory, after the executable file mirror image generating normal procedure, the machine post processor of delaying being appended in reserved internal memory.
The embodiment of the present invention, adopt and a kind ofly jointly detect based on hardware and software and process machine of the delaying exception method of flush bonding processor, provide new processor to delay machine aftertreatment means, enhance the commissioning of embedded system, be conducive to positioning embedded processor accurately and efficiently and delay the challenge of machine class.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of machine of the delaying conventional process flow of flush bonding processor;
Fig. 2 is the schematic flow sheet of the first embodiment of machine of the delaying process of flush bonding processor of the present invention;
Fig. 3 is that flush bonding processor of the present invention is delayed the storage schematic diagram of machine post processor of delaying in the disposal route of machine and the first embodiment of device.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 2, be that flush bonding processor of the present invention is delayed the schematic flow sheet of the first embodiment of disposal route of machine, the method comprises:
Step S11: software survival detects.
In this step, software module, based on the pattern of request à response, sends software asks by control end to detected processor, requires that processor responds.
In this step, after control end sends request, start time of reception window simultaneously, if do not receive the response of detected end in time window, be then designated as one-time detection time-out, again send request simultaneously.After continuous print repeated detection time-out, can think that processor is not survived.
Exemplary, PING order can be sent from control end to detected processor, or send the data field of specific format.
Step S12: hardware survival detects.
In this step, hardware survival detects based on listen mode, and namely by other processor connected with detected processor or chip, the active state of passive measurement processor, as the level change on measurement processor external terminal.
Hardware survival detects has stricter requirement compared with software survival detection, if in the time window of setting, the active state change of processor do not detected always, can think that processor is not survived.
Step S13: whether decision processor survives.
In this step, whether the testing result decision processor according to S11 and S12 survives.
Step S14: processor warm reset.
In this step, after being judged to be that processor is not survived, the warm reset of Trigger processor, makes program re-execute from start-up code.The triggering mode of warm reset, can be triggered by other processor be connected with detected processor, or directly uses other feasible pattern connected with processor warm reset pin.
Step S15: read hardware characteristics.
In this step, according to the follow-up processing flow expected, need to set hardware characteristics, thus make start-up code select corresponding executable program.Start-up code, in the minimum running environment started most, needs to read hardware characteristics.Hardware characteristics as the level of processor external terminal, processor certain register inner etc.
Step S16: determine whether to carry out machine aftertreatment of delaying.
In this step, when start-up code will judge to need operation to delay machine post processor according to hardware characteristics.
Step S17: run machine post processor of delaying.
In this step, start-up code will jump to machine post processor of delaying and perform.Machine post processor of delaying for re-establishing the communication link with control end, and sends the internal memory of processor after the machine of delaying to control end, and the reason of memory information to the machine of delaying that developer recycles collection is analyzed.
The embodiment of the present invention, to delay the analysis means after machine for user provides embedded system, is convenient to user and reads and obtain process accurately and to delay the reason of machine, improve the efficiency of positioning problems.
Detailed introduction is done to the embodiment of the adjustment method of embedded system in the present invention above.Below the debugging apparatus corresponding to said method is further elaborated.
Fig. 3, be the storage organization schematic diagram of machine post processor of delaying in the first embodiment of the debugging apparatus of embedded system of the present invention, this device 100 comprises normal procedure 110, machine post processor 120 of delaying.
Wherein, module 110 is normal function codes of user; Module 120 is the reserved internal memories storing machine post processor of delaying.Compile with link delay machine post processor time, need all the elements such as operation storehouse, data segment, code segment of designated program, all can only reserve internal memory in exist.
The foregoing is only preferred embodiment of the present invention, be not intended to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. flush bonding processor is delayed a disposal route for machine, and it is characterized in that, described method comprises:
Software survival is detected as the judgement whether subsequent processor survive and provides the first foundation;
Hardware survival is detected as the judgement whether subsequent processor survive and provides the second foundation;
Processor survival judges to determine whether processor survives according to the testing result of software restraint;
Processor warm reset carries out force revert to the machine of delaying, but does not destroy the running environment of processor;
Processor reruns start-up code;
Processor is according to hardware characteristics, and decision runs machine post processor of delaying, or rerun normal procedure.
2. the method for claim 1, is characterized in that, described software survival detects the pattern based on request à response, namely sends software asks by control end to detected processor, requires that processor responds.
3. the method for claim 1, is characterized in that, described software survival detects after control end sends request, starts time of reception window simultaneously, if do not receive the response of detected end in time window, is then designated as and detects time-out, again send request simultaneously;
Described software survival detects after continuous print repeated detection time-out, can think that processor is not survived.
4. the method for claim 1, is characterized in that, described hardware survival detects based on listen mode, by other processor be connected with detected processor or chip, and the active state of passive measurement processor;
Described hardware survival detects in the time window of setting, the active state change of processor do not detected always, can think that processor is not survived.
5. the method for claim 1, is characterized in that, after decision processor is not survived, triggers the warm reset of described processor, program is re-executed from start-up code.
6. the method for claim 1, is characterized in that, the described follow-up processing flow according to expecting, needs to set hardware characteristics, thus makes start-up code select corresponding executable program;
Described start-up code, in the minimum running environment started most, needs to read hardware characteristics.
7. the method for claim 1, is characterized in that, described in delay machine post processor when start-up code according to hardware characteristics judge need run time, machine post processor of delaying described in program will jump to execution.
8. the method for claim 1, is characterized in that, described in the delay method of machine post processor comprise:
For re-establishing the communication link with control end;
The internal memory after machine of being delayed by processor sends control end to;
The reason of memory information to the machine of delaying that developer recycles collection is analyzed.
9. the method for claim 1, is characterized in that, described in machine post processor of delaying be the code prestored in territory, save memory;
Territory, described save memory needs, when linking normal procedure, to retain one section of internal memory, after the executable file mirror image generating normal procedure, the machine post processor of delaying is appended in reserved internal memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510344469.1A CN104991832A (en) | 2015-06-20 | 2015-06-20 | Method for processing shutdown of embedded processor |
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| CN201510344469.1A CN104991832A (en) | 2015-06-20 | 2015-06-20 | Method for processing shutdown of embedded processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105912416A (en) * | 2016-04-07 | 2016-08-31 | 珠海市魅族科技有限公司 | Method for monitoring processor in terminal, and terminal |
| CN107145402A (en) * | 2017-05-27 | 2017-09-08 | 合肥联宝信息技术有限公司 | A kind of inspection software is delayed the method and electronic equipment of machine |
| CN107273291A (en) * | 2017-06-14 | 2017-10-20 | 湖南国科微电子股份有限公司 | A kind of processor debugging method and system |
| CN116701042A (en) * | 2023-07-27 | 2023-09-05 | 飞腾信息技术有限公司 | Memory data retention method, retention device and related equipment |
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| US20040177242A1 (en) * | 2003-03-05 | 2004-09-09 | Erickson Michael John | Dynamic computer system reset architecture |
| CN1940884A (en) * | 2005-09-30 | 2007-04-04 | 联想(北京)有限公司 | Computer system, computer network and method |
| CN1979381A (en) * | 2005-12-09 | 2007-06-13 | 中兴通讯股份有限公司 | Resetting method for preventing system from dead to stop operation by associating software and hardware |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105912416A (en) * | 2016-04-07 | 2016-08-31 | 珠海市魅族科技有限公司 | Method for monitoring processor in terminal, and terminal |
| CN105912416B (en) * | 2016-04-07 | 2019-06-28 | 珠海市魅族科技有限公司 | A kind of method and terminal monitoring processor in the terminal |
| CN107145402A (en) * | 2017-05-27 | 2017-09-08 | 合肥联宝信息技术有限公司 | A kind of inspection software is delayed the method and electronic equipment of machine |
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| CN107273291A (en) * | 2017-06-14 | 2017-10-20 | 湖南国科微电子股份有限公司 | A kind of processor debugging method and system |
| CN107273291B (en) * | 2017-06-14 | 2021-01-01 | 湖南国科微电子股份有限公司 | Processor debugging method and system |
| CN116701042A (en) * | 2023-07-27 | 2023-09-05 | 飞腾信息技术有限公司 | Memory data retention method, retention device and related equipment |
| CN116701042B (en) * | 2023-07-27 | 2023-10-13 | 飞腾信息技术有限公司 | Memory data retention method, retention device and related equipment |
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