CN101995523A - Structure and method for testing interconnection active device - Google Patents
Structure and method for testing interconnection active device Download PDFInfo
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- CN101995523A CN101995523A CN2009100577662A CN200910057766A CN101995523A CN 101995523 A CN101995523 A CN 101995523A CN 2009100577662 A CN2009100577662 A CN 2009100577662A CN 200910057766 A CN200910057766 A CN 200910057766A CN 101995523 A CN101995523 A CN 101995523A
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Abstract
The invention provides a structure and method for testing an interconnection active device, which is used for reducing the number of test terminals and test cost. The test structure comprises an interconnection structure and an active device structure, wherein the interconnection in the interconnection structure and the active device at least share one test terminal the interconnection of which is not in a return circuit.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to interconnection line active device test structure and method.
Background technology
Integrated circuit (IC) chip mainly is made of active device structures such as transistor integrated in it and the interconnecting construction that connects each active device structures, for obtaining the integrated circuit (IC) chip of good quality and performance, need usually interconnecting construction and active device structures are tested.
At present the test process to interconnecting construction and active device structures is: manufacturing test chip at first, and described test chip comprises interconnecting construction and active device structures usually, and described test structure all is connected with test lead (Pad) separately; After producing test chip, use corresponding Pad that interconnecting construction and/or active device structures are tested.
Figure 1A is the structural representation of interconnection line test structure in the existing test chip, and with reference to this figure, interconnecting construction 10 is connected with interconnection line Pad 100, based on interconnection line Pad 100 can test interconnection line structure 10 character such as resistance capacitance.
Figure 1B is the structural representation of active device test structure in the existing test chip, and with reference to this figure, active device structures 11 is connected with active device Pad110, can test the character of active device structures 11 based on active device Pad 110.
Though above-mentioned testing scheme is used widely, because the Pad number that needs is more, so the Pad area occupied is bigger, causes the test chip area bigger, and testing cost is also higher.
Summary of the invention
The invention provides interconnection line active device test structure and method,, reduce testing cost to reduce test lead quantity.
The present invention proposes interconnection line active device test structure, comprise interconnecting construction and active device structures, the shared at least test lead of interconnection line in the described interconnecting construction and active device structures; And the interconnection line of shared test lead is not in the loop.
The invention allows for interconnection line active device method of testing, comprise step: make the test chip that comprises interconnection line active device test structure, wherein said test structure comprises interconnecting construction and active device structures, the shared at least test lead of interconnection line in the described interconnecting construction and active device structures; And the interconnection line of shared test lead is not in the loop; And, interconnecting construction and/or active device structures are tested based on corresponding test lead.
Because the interconnection line and the shared at least test lead of active device structures of interconnecting construction in the interconnection line active device test structure that the present invention proposes, therefore adopt test lead separately to compare with existing test interconnection line structure separately with the test active device structures, when test interconnection line structure and active device structures, just reduced the quantity of required test lead, and because test lead shared area in test structure is bigger, the increase of test lead number can cause the very big increase of testing cost, therefore the scheme that proposes of the present invention has been owing to realized the minimizing of test lead number, so testing cost reduces greatly.The method of testing of embodiment of the invention proposition is based on the test structure realization of described shared test lead in addition, so this method also greatly reduces testing cost.
Description of drawings
Figure 1A is the structural representation of interconnection line test structure in the existing test chip;
Figure 1B is the structural representation of active device test structure in the existing test chip;
Fig. 2 is the structural representation of interconnection line active device test structure in the embodiment of the invention;
Fig. 3 is the structural representation of test structure in the first embodiment of the invention;
Fig. 4 is the structural representation of test structure in the second embodiment of the invention;
The interconnection line active device method of testing process flow diagram that Fig. 5 proposes for the embodiment of the invention.
Embodiment
In existing scheme, because when test interconnection line structure and active device structures, adopt pad separately to test respectively, therefore needed pad number is various, makes that the area of test structure is bigger, testing cost is higher, at this problem,, then can reduce pad quantity if propose can be shared with the pad of the pad of interconnecting construction and active device structures for the embodiment of the invention, thereby reduce the area of test structure, reduce testing cost.
Based on above-mentioned mentality of designing, the embodiment of the invention proposes following interconnection line active device test structure and method, can all test interconnecting construction and active device structures, and can reduce testing cost.
Referring to Fig. 2, for the structural representation of interconnection line active device test structure in the embodiment of the invention, in conjunction with this figure, this test structure 20 that the embodiment of the invention provides comprises:
Interconnecting construction 21 and active device structures 22, the shared at least pad 23 of the interconnection line of wherein said interconnecting construction 21 and active device structures 22.
Described interconnecting construction 21 can be multiple structure, for avoiding active device structures 22 test result to interconnecting construction 21 when the test interconnection line structure 21 to exert an influence, interconnection line 210 should not be in the loop in the interconnecting construction, if interconnection line 210 is in the loop, all may exert an influence to test result.
Preferable, for further avoiding influence to test result, interconnection line only with a shared pad of active device, but this is optional, for example under the situation that the shared pad of two or more active devices is arranged, an interconnection line can be connected to this pad, as with the shared pad of described two or more active devices, at this moment, the influence of test result also almost can be ignored, promptly interconnection line just can with the shared pad of a plurality of active devices, so the embodiment of the invention propose interconnection line preferable only with a shared pad of active device, but also can with the shared pad of a plurality of active devices.
Form by a sinuous curve and two pectinate lines with interconnecting construction below, active device is metal oxide semiconductor field effect tube (MOS, Metal Oxide Semiconductor) be example, come such scheme is described in detail, but at interconnecting construction is that the interconnecting construction of other structure and/or active device structures also are other kinds for example during diode etc., and such scheme also can be implemented.
With reference to Fig. 3, be the structural representation of test structure in the first embodiment of the invention, in conjunction with this figure, this test structure 30 comprises:
Interconnecting construction 31, this interconnecting construction 31 is made of first pectinate line 310, the second dressing line 311 and the curve 312 that wriggles, wherein sinuous curve 312 two ends are connected with two pad separately, be respectively a pad 1, the 2nd pad 2, the 3rd pad 4 and the 4th pad 5, the one pad 1 and the 2nd pad 2 are connected the same end of the curve 312 that wriggles, and the 3rd pad 4 and the 4th pad 5 are connected an other end of the curve 312 that wriggles; And first pectinate line 310 adopt through holes to be connected with second pectinate line 311, and be connected with the 3rd pad 3.
Metal-oxide-semiconductor 32, the source S of this metal-oxide-semiconductor 32 are connected with the 6th pad 6, and substrate is connected with the 7th pad7, and drain terminal D is connected with the 8th pad 8, grid G and interconnecting construction 31 shared the 5th pad 5.
Be that the 5th pad 5 of interconnecting construction 31 is shared with metal-oxide-semiconductor 32 in the test structure 30 of this embodiment, and the sinuous curve 312 of shared the 5th pad 5 does not connect other active device structures, and sinuous curve 312 is not in the loop, to prevent other active device that connects when testing test result is exerted an influence.
A pad among other three pad that the curve 312 of can selecting in addition to wriggle connects is as shared pad, other three pad that the curve 312 that wriggles connects comprise a pad 1, the 2nd pad2 and the 4th pad 4, but because a pad 1, the 2nd pad 2, the 4th pad 4 and the 5th pad 5 all are connected with sinuous curve 312, therefore can only select one of them pad as shared pad, other three pad just need unsettled.
The sinuous curve 312 of interconnecting construction 31 and metal-oxide-semiconductor 32 shared pad in the foregoing description in addition, reality also can be that the 3rd pad 3 that connects of pectinate line is as shared pad, the 3rd pad 3 both can be shared with metal-oxide-semiconductor 32, also can be shared with other active device.
In the foregoing description, the pad that metal-oxide-semiconductor 32 grid G connect is as shared pad, reality also can be other three end for example any end among source end S, drain terminal D and the substrate B as shared pad, but because grid G has high input impedance, the influence of interconnecting construction 31 in the time of almost can avoiding testing, the therefore preferable shared pad of grid G that selects for use usually.
In the foregoing description metal-oxide-semiconductor 32 just with the sinuous curve 312 shared pad of interconnecting construction 31, in fact metal-oxide-semiconductor 32 can also be simultaneously with other interconnecting construction in the shared pad of interconnection line, other that just needs to select metal-oxide-semiconductor 32 also do not have the connection of public pad bring in described other interconnection structure in the shared pad of interconnection line.
Test a plurality of active device structures and a plurality of interconnecting construction in addition if desired, then can independently determine shared mode according to the foregoing description, be that example is set forth the test structure that is used to test a plurality of active device structures and a plurality of interconnecting constructions with two metal-oxide-semiconductors and two shared pad of interconnecting construction below, but except the sharing structure that following embodiment provides, therefore multiple structure can also be arranged, and the sharing structure that should not provide with following embodiment is as restriction of the present invention.
Referring to Fig. 4, for the test structure synoptic diagram in the second embodiment of the invention, in conjunction with this figure, this test structure 40 comprises first metal-oxide-semiconductor 41, second metal-oxide-semiconductor 42, first interconnecting construction 43 and second interconnecting construction 44.Wherein first metal-oxide-semiconductor 41 comprises the first source end S1, the first drain terminal D1, first grid G1 and the first substrate B1; Second metal-oxide-semiconductor 42 comprises the second source end S2, the second drain terminal D2, second grid G2 and the second substrate B2; The first source end S1 and second source end S2 common source pad 46, the first drain terminal D1 and the shared leakage of second drain terminal D2 pad 48, the first substrate B1 and the second substrate B2 sharing body pad 47 in the present embodiment;
First metal-oxide-semiconductor 41 and first interconnecting construction, 43 shared pad, second metal-oxide-semiconductor and second interconnecting construction, 44 shared pad, which pad is its shared mode for example select come shared grade that multiple choices can be arranged, and can know with reference to the foregoing description, repeats no more herein.
Present embodiment is with shared pad between the metal-oxide-semiconductor, interconnecting construction and metal-oxide-semiconductor more respectively the mode of shared pad realize that the pad between a plurality of metal-oxide-semiconductors and a plurality of interconnecting construction is shared, in fact also can be the shared pad of metal-oxide-semiconductor and interconnecting construction, interconnecting construction again with the shared pad of other metal-oxide-semiconductor, other metal-oxide-semiconductor again and the mode of the shared pad of other interconnecting construction realize that the pad between a plurality of metal-oxide-semiconductors and a plurality of interconnecting construction is shared.
Owing to interconnecting construction and the shared pad of active device structures, therefore can reduce pad quantity in the test structure that the embodiment of the invention proposes, thereby reduce the test structure area, reduce testing cost.
The embodiment of the invention gives a plurality of embodiment to set forth a plurality of schemes of interconnecting construction and the shared pad of active device, described a plurality of scheme is owing to can increase the quantity of shared pad, therefore can further reduce required pad total quantity, further reduce the test structure area, reduced testing cost.
In the test structure that the embodiment of the invention provides interconnection line can only with a shared pad of active device, and this interconnection line can not be in the loop, therefore avoided largely when test interconnection line, active device is to the influence of interconnection line test result, also avoided when the test active device, interconnection line has improved test accuracy to the influence of active device test result.
The embodiment of the invention gives interconnection line active device method of testing, to reduce testing cost.
The interconnection line active device method of testing process flow diagram that Fig. 5 proposes for the embodiment of the invention, in conjunction with this figure, the method comprising the steps of:
Step a makes the test chip that comprises interconnection line active device test structure, and wherein said test structure comprises interconnecting construction and active device structures, the shared at least pad of described interconnecting construction and active device structures; And the interconnection line of shared pad is not in the loop; Preferable, in the described interconnecting construction interconnection line can only with a shared pad of active device.
Step b based on corresponding pad, tests interconnecting construction and/or active device structures.
Because therefore the pad of the embodiment of the invention shared interconnecting construction and active device structures when testing has reduced the pad number of test interconnection line structure and active device structures, thereby has reduced testing cost.
The mode of interconnecting construction and the shared pad of active device has multiplely among the step a, can not be described in detail with reference to the scheme of the shared pad of said structure embodiment herein.
For step b, character that can a test interconnection line structure, the character that also can only test active device can also all be tested both character.
Be example with interconnection line active device structures in the test pattern 3 below, a kind of specific implementation process that provides step b is beneficial to understand step b, but should not limit step b: at first can adopt a pad 1, the 2nd pad 2, the 4th pad 4 and the 5th pad 5 to come the resistance of sinuous curve 312 in the test interconnection line structure 31; Select for use any one pad among the 3rd pad 3 and above-mentioned four pad to come electric capacity in the test interconnection line structure 31; Can adopt the 5th pad 5, the 6th pad 6, the 7th pad 7 and the 8th pad 8 to test the characteristic of MOs pipe 32 then.
The situation that the scheme that the embodiment of the invention proposes can also be used to test a plurality of interconnecting constructions and a plurality of active devices is released in conjunction with Fig. 4 easily with reference to above-mentioned testing scheme.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. an interconnection line active device test structure comprises interconnecting construction and active device structures, it is characterized in that the shared at least test lead of the interconnection line of described interconnecting construction and active device structures; And
The interconnection line of shared test lead is not in the loop.
2. test structure as claimed in claim 1 is characterized in that, in the described interconnecting construction interconnection line can only with a shared test lead of active device structures.
3. test structure as claimed in claim 1 is characterized in that, an active device structures and the shared test lead of interconnection line.
4. test structure as claimed in claim 1 is characterized in that, an active device structures and at least two shared test leads of interconnection line.
5. test structure as claimed in claim 1 is characterized in that, described active device is metal oxide semiconductor transistor or diode.
6. test structure as claimed in claim 5 is characterized in that, in four links of described transistorized source electrode, drain electrode, grid and substrate, each link all with the shared test lead of interconnection line.
7. test structure as claimed in claim 5 is characterized in that, in described transistorized source electrode, drain electrode, grid and four links of substrate, the shared test lead of part link and interconnection line is arranged.
8. interconnection line active device method of testing comprises:
Making comprises the test chip of interconnection line active device test structure, and wherein said test structure comprises interconnecting construction and active device structures, the shared at least test lead of described interconnecting construction and active device structures; And the interconnection line of shared test lead is not in the loop; And
Based on corresponding test lead, interconnecting construction and/or active device structures are tested.
9. method as claimed in claim 8 is characterized in that, in the described interconnecting construction interconnection line can only with a shared test lead of active device.
10. method as claimed in claim 8 is characterized in that, an active device and the shared test lead of interconnection line.
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| CN2009100577662A CN101995523A (en) | 2009-08-19 | 2009-08-19 | Structure and method for testing interconnection active device |
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| CN2009100577662A CN101995523A (en) | 2009-08-19 | 2009-08-19 | Structure and method for testing interconnection active device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187399A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via (TSV) testing structure and TSV testing method |
| CN105097780A (en) * | 2014-04-28 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection reliability detection structure and detection method |
| CN106505054A (en) * | 2016-11-30 | 2017-03-15 | 上海华力微电子有限公司 | A kind of test structure of semiconductor crystal wafer |
-
2009
- 2009-08-19 CN CN2009100577662A patent/CN101995523A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187399A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via (TSV) testing structure and TSV testing method |
| CN103187399B (en) * | 2011-12-31 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via (TSV) testing structure and TSV testing method |
| CN105097780A (en) * | 2014-04-28 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection reliability detection structure and detection method |
| CN105097780B (en) * | 2014-04-28 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of detection structure and detection method of metal interlinking reliability |
| CN106505054A (en) * | 2016-11-30 | 2017-03-15 | 上海华力微电子有限公司 | A kind of test structure of semiconductor crystal wafer |
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Application publication date: 20110330 |