CN101992422B - Process control method and system of copper chemical mechanical polishing - Google Patents
Process control method and system of copper chemical mechanical polishing Download PDFInfo
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- CN101992422B CN101992422B CN 200910194573 CN200910194573A CN101992422B CN 101992422 B CN101992422 B CN 101992422B CN 200910194573 CN200910194573 CN 200910194573 CN 200910194573 A CN200910194573 A CN 200910194573A CN 101992422 B CN101992422 B CN 101992422B
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Abstract
The invention discloses a process control method of copper chemical mechanical polishing (CMP). A detection region consisting of a plurality of parallel copper metal wires is arranged in a sample wafer; the thickness of the copper metal wire in a monitor region of sample wafer in the current batch of wafers is measured before and after the CMP; the average material removal rate of the sample wafer is calculated according to the difference value of the two thickness values; the material removal rate obtained by calculation is compared with a target material removal rate so as to determine a time compensation value; and the time length of the CMP is adjusted according to the time compensation value and the CMP processing is performed on the next batch of wafers by using the adjusted time length. The invention also discloses a process control system of the copper chemical mechanical polishing. Through the scheme of the invention, the accuracy of thickness measurement is greatly improved, so that the time length is more accurately adjusted.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly the course control method for use of copper CMP and system.
Background technology
Along with the critical size of semiconductor devices further reduces, copper metallization technology becomes more and more important as the manufacturing process of interconnect devices.Copper metal layer is constructed in normal at present employing technological process as shown in Figure 1 on wafer, comprise the steps:
Step 101: (Inner Level Dielectric, ILD), inter-level dielectric is an insulating material at crystal column surface deposition inter-level dielectric.
Step 102: inter-level dielectric is carried out photoetching generate figure, this graphical definition goes out groove structure.
Step 103: in wafer upper surface and trench wall deposited barrier layer successively, copper seed layer.
Step 104: on copper seed layer, continue deposited copper with electrochemical deposition (ECD) method, copper is filled in the said groove, forms copper metal layer.
Step 105: to wafer carry out copper chemically mechanical polishing (Chemical Mechanical Polish, CMP) so that remove unnecessary copper.
In the prior art, large batch of wafer is being carried out formal first being processed, is at first trying processing with sample wafer, in about 50 microns * 50 microns zone of sample wafer set inside as CMP guarded region (Monitor Pad).Fig. 2 overlooks the sketch map of direction for sample wafer in the prior art.Sample wafer 201 only is shown among the figure is provided with the guarded region 202 that is made up of copper, other irrelevant structures are also not shown.Wherein guarded region 202 is merely signal, and its size is not represented the size on actual wafer.
After sample wafer is carried out the CMP process of copper, the copper thickness of the CMP guarded region of sample wafer is measured, if the distribution of one-tenth-value thickness 1/10 that measures and one-tenth-value thickness 1/10 meets predefined technological requirement, again wafer in enormous quantities is processed; If one-tenth-value thickness 1/10 does not meet technological requirement,, adjust like pressure of process time, wafer and grinding pad etc. then to the relevant parameter of CMP technology.Can avoid as much as possible doing over again like this and waste of raw materials etc.
Shown in Figure 3 is near the generalized section the crystal column surface after the copper CMP in the prior art.Wherein, last figure is an ideal situation, and the upper surface of the copper layer 302a after the CMP is that the upper surface with inter-level dielectric 301a constitutes an absolute plane.But actual conditions are shown in figure below, and uneven depression appears in the upper surface place of copper layer 302b, that is to say, variation heterogeneous appears in the thickness of copper layer 302b.
Can infer; The copper layer thickness of the sample wafer guarded region after the CMP is measured; Because the non-uniform change of copper layer thickness; The thickness of measuring at different parts is different, obviously can cause the measurement result of the guarded region copper layer thickness of sample wafer inaccurately, and then has influence on the processing technology of semiconductor integrated circuit.In addition, according to the layer resistance (Sheet Resistance, Rs) computing formula:
Rs＝ρ/H (1)
ρ is the resistivity of copper, is the constant constant of value, and H is the thickness of copper layer.Obviously, the inhomogeneities of copper thickness also can influence the uniformity of copper Rs significantly, and Rs is the important parameter of crossbeam IC products.Therefore the inhomogeneities of copper thickness can cause the homogeneity variation of properties of product.
Summary of the invention
In view of this, the objective of the invention is to, propose a kind of course control method for use and system of copper CMP, can improve accuracy the sample wafer thickness measure.
The course control method for use of a kind of copper CMP that the embodiment of the invention proposes is provided with guarded region in sample wafer, said guarded region is made up of many parallel copper metal lines, and this method comprises the steps:
The thickness H1 of copper metal line in the guarded region of sample wafer in A, the current lot of measurement;
B, with fixed time span current lot is carried out copper CMP and handle;
C, after copper CMP is handled, measure current batch in the thickness H2 of copper metal line in the guarded region of sample wafer;
D, calculate the difference of said H1 and H2, remove rate according to the average material of said difference calculation sample wafer;
E, the material that calculates is removed rate remove rate with target material and compare, confirm the offset of time;
F, according to the time span of said time bias value adjustment copper CMP, the next batch wafer as current batch, and is gone to said steps A.
The width range of every copper metal line is 0.07 micron to 0.12 micron in the said guarded region.
Spacing in the said guarded region between the adjacent copper metal line is 0.07 micron to 0.12 micron.
The embodiment of the invention proposes a kind of Process Control System of copper CMP, comprises measuring unit (701), computing module (702), formation module (703) and chemically mechanical polishing CMP board (704),
Measuring unit (701) is used for the guarded region copper metal line thickness of sample wafer before the CMP is measured, and the guarded region copper metal line thickness of the sample wafer after the CMP is measured, and the one-tenth-value thickness 1/10 that measures exports computing module (702) to;
Said computing module (702) be used for calculating before the same sample wafer CMP with CMP after the thickness difference of the guarded region copper metal line measured, remove rate MRR according to the average material of said difference calculation sample wafer; And the MRR that calculates compared with target MRR; Confirm the offset of time; Compensate according to the time span of this offset current batch, the time span value after being compensated, and export the time span value after the said compensation to CMP board (704);
Said formation module (703) is used to receive non-sample wafer and from the sample wafer of measuring unit (701), said non-sample wafer is divided into a plurality of batches, and sample wafer is sneaked in each batch; The non-sample wafer and the sample wafer order of each batch are sent to CMP board (704);
CMP board (704) is used for that one batch wafer from formation module (703) is carried out CMP to be handled; The time span that said CMP handles confirms that according to the time span value from computing module (702) sample wafer after CMP is handled is sent to measuring unit (701).
Said formation module (703) comprises three load terminal port: load terminal port 1, load terminal port 2 and load terminal port 3; Each load terminal port is used to place one batch wafer, and wherein load terminal port 1 is used to receive non-sample wafer and from the sample wafer of measuring unit (701); Load terminal port 2 is used to receive non-sample wafer and the sample wafer from load terminal port 1; Load terminal port 3 is used to receive non-sample wafer and the sample wafer from load terminal port 2, and said non-sample wafer and sample wafer are sent to CMP board (704).
Can find out that from above technical scheme the excursion of copper metal line thickness is very little in the sample wafer guarded region, therefore can greatly improve the accuracy of thickness measure, make the adjustment of time span more accurate.In addition, in the processing technology of prior art, need independent first processed sample wafer, and sample wafer is measured, and meanwhile considerable wafer just is in wait state, this causes decrease in efficiency for being very big waste process time.And among the present invention program sample wafer is inserted in the wafer of each batch; Last batch sample wafer is measured and is obtained the offset of time span; Can be applied in the CMP process of next batch wafer, save process time greatly, improve operating efficiency.
Description of drawings
Fig. 1 is the process chart of structure copper metal layer on wafer;
Fig. 2 overlooks the sketch map of direction for sample wafer in the prior art;
Fig. 3 is near the generalized section the crystal column surface after the copper CMP in the prior art;
Fig. 4 overlooks the sketch map of direction for the sample wafer of the embodiment of the invention;
Fig. 5 is in the embodiment of the invention scheme, the generalized section of the sample wafer near surface after carrying out the copper CMP processing;
Fig. 6 carries out the flow chart of copper CMP for the embodiment of the invention to wafer in enormous quantities;
Fig. 7 is the CMP Process Control System block diagram of the embodiment of the invention;
Fig. 8 carries the sequential chart of each lot for bearing end mouthpiece in the formation module of the CMP system of the embodiment of the invention.
The specific embodiment
The present invention program one of the purpose that will reach be to make after the copper CMP technology, the copper layer thickness excursion of guarded region is as far as possible little, that is to say the homogeneity that improves copper layer thickness as far as possible.To the deficiency of guarded region in the prior art, the present invention proposes the design of new guarded region.
For making the object of the invention, technical scheme and advantage clearer, the present invention is done further to set forth in detail below in conjunction with accompanying drawing.
Fig. 4 shows the sample wafer of the embodiment of the invention and overlooks the sketch map of direction.Sample wafer 401 only is shown among the figure is provided with by guarded region 402, other irrelevant structures are also not shown.Different with monoblock copper layer in the prior art as guarded region; Guarded region 402 is the array of metal lines that comprises that a plurality of parallel copper metal lines constitute; The span of the width of each copper metal line is 0.07 micron to 0.12 micron, and the span of the spacing between the adjacent copper metal line is 0.07 micron to 0.12 micron.And the area that whole guarded region 402 distributes can be suitable, perhaps bigger with the area of the guarded region 202 of sample wafer of the prior art.
Fig. 5 shows in the embodiment of the invention scheme, the generalized section of the sample wafer near surface after carrying out the copper CMP processing.Profile direction is vertical with the metal wire of guarded region 402.As can be seen from Figure 5, because the width of each metal wire has only 0.07 micron to 0.12 micron, the excursion of copper thickness is limited in the very little scope.If like this thickness of the metal wire in the guarded region 402 is measured, can obtain copper layer thickness comparatively accurately.
What Fig. 6 showed the embodiment of the invention carries out the flow process of copper CMP to wafer in enormous quantities, comprises the steps:
Step 601: the thickness of copper metal line in the guarded region of sample wafer in measuring current batch.In the embodiment of the invention, in the wafer of each batch, comprise at least one sample wafer.Sample wafer is to be provided with in the sample wafer guarded region that a plurality of parallel copper metal lines are formed with the difference of other wafers.
Step 602: keep under the identical situation of other process conditions, with fixed time span current batch wafer is carried out CMP and handle.When carrying out first, this time span can be confirmed through the mode that is provided with.
Step 603: after CMP handles, measure current batch in the thickness of copper metal line in the guarded region of sample wafer.
Step 604: calculate before the same sample wafer CMP with CMP after the thickness difference of copper metal line in the guarded region measured, according to the average material of said difference calculation sample wafer remove rate (Material Removal Rate, MRR).
Step 605: the MRR that calculates is compared with target MRR, confirm the offset of time.
This step can realize in the following manner: in advance through the time span of measuring CMP process and the corresponding relation between the MRR, obtain the corresponding relation curve of time and MRR.In this corresponding relation curve, find corresponding time value according to the MRR that calculates, and in this corresponding relation curve, find the time corresponding value according to target MRR, above-mentioned two time values are subtracted each other, the gained difference is as the offset of time.
Step 606:, the next batch wafer as current batch, and is gone to step 601 according to the time span of said time bias value adjustment CMP.
In order further to improve the efficient of entire process flow process, the embodiment of the invention adopts three load terminal port, and (Load Port LP) adds a measurement port and realizes large batch of wafer CMP process.Fig. 7 shows the CMP Process Control System block diagram of the embodiment of the invention, comprising measuring unit 701, computing module 702, formation module 703 and CMP board 704.
Said formation module 703 comprises three load terminal port: load terminal port 1, load terminal port 2 and load terminal port 3; Each load terminal port is used to place one batch wafer, and wherein load terminal port 1 is used to receive non-sample wafer and from the sample wafer of measuring unit 701; Load terminal port 2 is used to receive non-sample wafer and the sample wafer from load terminal port 1; Load terminal port 3 is used to receive non-sample wafer and the sample wafer from load terminal port 2, and said non-sample wafer and sample wafer are sent to CMP board 704.
Fig. 8 shows that the bearing end mouthpiece carries the sequential chart of each lot in the formation module of CMP system of the embodiment of the invention.For ease of explanation, suppose that each batch comprises 4 wafers.First batch wafer numbering is respectively #1, #2, #3 and #4, and wherein #1 is a sample wafer.At first the metal wire thickness to the guarded region of #1 is measured in measuring unit 701, and it is temporary that measurement result exports computing module 702 to; Then first batch wafer at first is placed on load terminal port 1; Then be sent to load terminal port 2 (meanwhile; Sample wafer # 5 in 701 pairs of second batch of wafers (#5 to #8) of measuring unit measures, and second batch of wafer is placed on load terminal port 1), and then (second batch of wafer is sent to load terminal port 2 simultaneously to be sent to load terminal port 3; Sample wafer # 9 in the 3rd batch of wafer (#9 to #12) is measured, and the 3rd piece of wafer is placed to load terminal port 1).Next, first wafer is sent to and carries out the CMP processing on the CMP board 704, is measured by 701 couples of #1 of measuring unit after the processing again, and measured value is sent to computing module 702.The adjusted time span of computing module 702 outputs, second batch of wafer is sent to and carries out the CMP processing on the CMP board 704, and time span equals the adjusted time span of said computing module 702 outputs.For follow-up batch wafer also like this mode handle.
Among the present invention program, the excursion of copper metal line thickness is very little in the sample wafer guarded region, therefore can greatly improve the accuracy of thickness measure.In addition, in the processing technology of prior art, need independent first processed sample wafer, and sample wafer is measured, and meanwhile considerable wafer just is in wait state, this causes decrease in efficiency for being very big waste process time.And among the present invention program sample wafer is inserted in the wafer of each batch; Last batch sample wafer is measured and is obtained the offset of time span; Can be applied in the CMP process of next batch wafer, save process time greatly, improve operating efficiency.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the course control method for use of a copper CMP is characterized in that, in sample wafer, is provided with guarded region, and said guarded region is made up of many parallel copper metal lines, and this method comprises the steps:
The thickness H1 of copper metal line in the guarded region of sample wafer in A, the current lot of measurement;
B, with fixed time span current lot is carried out copper CMP and handle;
C, after copper CMP is handled, measure current batch in the thickness H2 of copper metal line in the guarded region of sample wafer;
D, calculate the difference of said H1 and H2, remove rate according to the average material of said difference calculation sample wafer;
E, the material that calculates is removed rate remove rate with target material and compare, confirm the offset of time;
F, according to the time span of said time bias value adjustment copper CMP, the next batch wafer as current batch, and is gone to said steps A.
2. method according to claim 1 is characterized in that, the width range of every copper metal line is 0.07 micron to 0.12 micron in the said guarded region.
3. method according to claim 1 is characterized in that, the spacing in the said guarded region between the adjacent copper metal line is 0.07 micron to 0.12 micron.
4. the Process Control System of a copper CMP is characterized in that, comprises measuring unit (701), computing module (702), formation module (703) and CMP board (704),
Measuring unit (701) is used for the guarded region copper metal line thickness of sample wafer before the CMP is measured, and the guarded region copper metal line thickness of the sample wafer after the CMP is measured, and the one-tenth-value thickness 1/10 that measures exports computing module (702) to;
Said computing module (702) be used for calculating before the same sample wafer CMP with CMP after the thickness difference of the guarded region copper metal line measured, remove rate MRR according to the average material of said difference calculation sample wafer; And the MRR that calculates compared with target MRR; Confirm the offset of time; Compensate according to the time span of this offset current batch, the time span value after being compensated, and export the time span value after the said compensation to CMP board (704);
Said formation module (703) is used to receive non-sample wafer and from the sample wafer of measuring unit (701), said non-sample wafer is divided into a plurality of batches, and sample wafer is sneaked in each batch; The non-sample wafer and the sample wafer order of each batch are sent to CMP board (704);
CMP board (704) is used for that one batch wafer from formation module (703) is carried out CMP to be handled; The time span that said CMP handles confirms that according to the time span value from computing module (702) sample wafer after CMP is handled is sent to measuring unit (701).
5. system according to claim 4; It is characterized in that; Said formation module (703) comprises three load terminal port: load terminal port 1, load terminal port 2 and load terminal port 3; Each load terminal port is used to place one batch wafer, and wherein load terminal port 1 is used to receive non-sample wafer and from the sample wafer of measuring unit (701); Load terminal port 2 is used to receive non-sample wafer and the sample wafer from load terminal port 1; Load terminal port 3 is used to receive non-sample wafer and the sample wafer from load terminal port 2, and said non-sample wafer and sample wafer are sent to CMP board (704).
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| CN102810492B (en) * | 2011-06-03 | 2015-08-05 | 中国科学院微电子研究所 | Process monitoring method after metal gate CMP |
| CN102820237B (en) * | 2011-06-11 | 2015-08-05 | 中国科学院微电子研究所 | method for measuring metal thickness in semiconductor device |
| CN105563299B (en) * | 2014-11-05 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The chemical and mechanical grinding method of metal |
| CN105563291B (en) * | 2015-12-16 | 2017-12-12 | 广东光泰激光科技有限公司 | A kind of processing method for improving ceramic anilox roller qualification rate |
| CN206105604U (en) * | 2016-09-14 | 2017-04-19 | 天津华海清科机电科技有限公司 | Chemical mechanical polishing system |
| CN107186481B (en) * | 2017-05-26 | 2021-11-16 | 上海航天设备制造总厂 | Method for processing waveguide mounting hole of antenna frame for satellite |
| JP7081544B2 (en) * | 2019-03-22 | 2022-06-07 | 株式会社Sumco | Work double-sided polishing method and work double-sided polishing device |
| CN110394727B (en) * | 2019-07-29 | 2021-11-23 | 武汉新芯集成电路制造有限公司 | Wafer grinding control method and device and grinding equipment |
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