CN101989222A - Loongson simulator terminal - Google Patents
Loongson simulator terminal Download PDFInfo
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- CN101989222A CN101989222A CN 201010553498 CN201010553498A CN101989222A CN 101989222 A CN101989222 A CN 101989222A CN 201010553498 CN201010553498 CN 201010553498 CN 201010553498 A CN201010553498 A CN 201010553498A CN 101989222 A CN101989222 A CN 101989222A
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Abstract
The invention relates to a loongson simulator terminal, which is characterized by comprising a main control module, an Ethernet interface, a serial interface, a JTAG (Joint Test Action Group) interface and an LED indicating lamp, wherein the main control module comprises an AU1550 processor, an SDRAM (Synchronous Dynamic random access memory) memory, an NORFlash, a CPLD (Complex Programmable Logic Device) programmable device and a level conversion chip. Aiming at the defects that a debugging tool of a loongson processor is restrained by using conditions and cannot be applied to a wide range, the invention provides the efficient loongson simulator terminal which supports more integrated development environments and mainframe platforms. The a loongson simulator supports the open source integrated development environment, is irrelevant to an operating system utilized by a subscriber, simplifies an online process with the loongson processor, reduces the using burden of the subscriber and provides the technical guarantee for wide range application of the loongson processor.
Description
Technical field
The present invention relates to the debugging apparatus in a kind of embedded system, particularly a kind of Godson emulator terminal at the Godson processor debugging.
Background technology
Flush bonding processor has obtained using widely in every field, and correspondingly, people also become very urgent to the demand of embedded development instrument.The exploitation of flush bonding processor needs special development environment, generally comprises cross-compiler, intersection debugger, Integrated Development Environment (IDE) etc.The debugger that intersects has two kinds of implementations: a kind of is to debug on the sheet, and another kind is that the operation monitoring program is finished debugging on the target machine processor.The former needs the hardware debug module support of processor, EJTAG as the MIPS processor, the OnCE of state's die processor etc., can be under the bare machine state by above-mentioned module, hardware system and software systems are debugged, and the latter can only be after the processor operate as normal operable a kind of debugging method.
Godson is for No. one the homemade processor that Divine Land, Beijing Godson company has independent intellectual property right, be the characteristics of using at embedded system, to each side such as power consumption, area and performance improve and the high flexible that obtains be applicable to the more processor of wide spectrum, be the high ground term order of country's nuclear.Also realized class EJTAG debugging module in processor of Godson, have only the emulator of the USB interface that the applicant researches and develops under given conditions processor of Godson to be debugged support at present, this emulator only meets the following conditions could operate as normal: need and operate under the Windows xp operating system, do not support operating systems such as Linux, Mac; Need and operate in JARII-IDE(Integrated Development Environment on the debug host) support of software, do not support third party's Integrated Development Environment such as Eclipse, Insight; Only can support the debugging of the program of particular version compiler compiling, otherwise uncertain abnormal conditions can appear in debugging; The on line operation of USB emulator and Godson processor needs specific operational means, has increased debugging person's use burden.Therefore, the widespread adoption of a processor of Godson is subjected to the restriction of developing instrument.
Summary of the invention
Technical matters to be solved by this invention be the debugging acid at the Godson processor be subjected to the service condition restriction, can't carry out widespread adoption deficiency, provide a kind of efficiently, support the Godson emulator terminal of more Integrated Development Environment and host platform.
Technical matters to be solved by this invention is to realize by following technical scheme.The present invention is a kind of Godson emulator terminal, and be characterized in: it comprises main control module, Ethernet interface, serial line interface, jtag interface and LED light;
Described main control module comprises AU1550 processor, SDRAM storer, NOR Flash, CPLD programming device and level transferring chip;
The SDRAM storer is connected on the sdram controller of AU1550 processor;
NOR Flash is connected on the static bus controller of AU1550 processor;
The CPLD programming device is connected on the static bus controller of AU1550 processor by bus mode;
The bus of described static bus controller comprises address bus A[28:23] and A[11:0], data bus D[31:0] and control bus;
Described control bus comprises RBE[3:0] signal, RWE signal, ROE signal, RCS signal and EWAIT signal; Wherein, RBE signal indication byte enable is selected, and low level is effective, and RBE0 is for data bus D[7:0], RBE1 is for data bus D[15:8], RBE2 is for data bus D[23:16], RBE3 is for data bus D[31:24]; RWE signal indication write-enable, low level is effective; ROE signal indication output enable, low level is effective; RCS represents that chip selection signal enables, and low level is effective; EWAIT signal indication external unit needs processor to increase the stand-by period, and low level is effective;
Level transferring chip is connected with the CPLD programming device by the JTAG signal, produces the level signal of 1.2V to 5V; Described JTAG signal comprises TRST signal, TDI signal, TDO signal, tck signal and tms signal;
Jtag interface is connected with level transferring chip by described JTAG signal, and jtag interface also comprises RST signal, power supply input and ground connection input; Described RST signal generates Open Drain output signal by the CPLD programming device, and power supply input and ground connection input are from Target Board; Level transferring chip is input as level reference with power supply, produces and target machine level level signal same;
Ethernet interface is connected with AU1550 processor MAC0 controller by the PHY physical chip;
Serial line interface is connected by the UART0 controller of MAX232 chip and AU1550 processor;
LED light is connected with the CPLD programming device, and it comprises STA pilot lamp and TAR pilot lamp, the Chang Liang by two pilot lamp, extinguishes and the duty of the state representation emulator that glimmers.
If no special instructions, the letter abbreviations of each components and parts described in the present invention, chip, signal etc. is general (abbreviation) of the prior art title, perhaps is the commercially available prod.
When the present invention powered on, STA pilot lamp Chang Liang, TAR pilot lamp extinguished the expression system and enter init state, represented system initialization success, running normally when the STA pilot lamp extinguishes, the TAR pilot lamp is often bright or glimmer; STA pilot lamp flicker when the present invention and Eclipse, Insight or third party's Integrated Development Environment are carried out data communication, when not having data communication, the STA pilot lamp extinguishes; When the Godson processor of Target Board enters debugging mode, TAR pilot lamp Chang Liang; When the Godson processor of Target Board withdraws from debugging mode and enters running status, the flicker of TAR pilot lamp; During duty by the serial line interface configuring simulator, STA pilot lamp and TAR pilot lamp enter blink states fast.
The present invention is connected the Godson processor EJTAG interface of jtag interface of the present invention and target machine by a single data cable, softwares such as software such as Eclipse, Insight or third party's Integrated Development Environment is connected in the network service that provides of the present invention by procotol TCP on any platform, Integrated Development Environment and communication of the present invention are provided satisfy the Remote GDB agreement of standard; The command request bag that softwares such as Integrated Development Environment send is transferred in the main control module of the present invention by Ethernet interface, main control module resolve command request package, by carrying out data communication with CPLD, produce the JTAG control signal sequence of control Godson processor, main control module returns to softwares such as Integrated Development Environment to the result of command request, a command request constitutes software and mutual basic processes of the present invention such as Integrated Development Environment with response, in this process, LED light can be carried out Chang Liang according to debugging mode, extinguish or glimmer, report timely duty of the present invention to debugging person.
The present invention externally provides data communication channel by Ethernet interface, softwares such as Eclipse, Insight or third party's Integrated Development Environment are connected in the network service provided by the invention by the SOCKET interface, the present invention by jtag interface control, obtain the information of Godson processor in the target machine, and result is fed back in the Integrated Development Environment of host platform by Ethernet interface.
The present invention has simplified on line operation with the Godson processor by the RST signal of jtag interface, the present invention is before softwares such as Eclipse, Insight or third party's Integrated Development Environment provide service, enter the EJTAGBOOT state by jtag interface by the Godson processor, send reset signal by the RST signal then, finish allowing the Godson processor enter correct debugging mode.After online the finishing, softwares such as Eclipse, Insight or third party's Integrated Development Environment can be debugged according to the operation steps of software self, and the user need not carry out additional operations, has alleviated user's use burden.
Inventive principle of the present invention is: network communication protocol and host platform are irrelevant, and softwares such as Eclipse, Insight and third party's Integrated Development Environment can be connected in the network service provided by the invention on the host platform arbitrarily.
The integrated Full Featured ELF parsing modules of software such as Eclipse, Insight or third party's Integrated Development Environment, the program code that parsing that can be correct is compiled by the compiler without version, by described Integrated Development Environment can be correct communicate with the present invention, finish the intersection debug process.
Described RST signal is realized by Open Drain mode, can simulate the course of work of user's hand-reset Godson processor.
Compared with prior art, advantage of the present invention has provided a kind of Godson emulator of the Integrated Development Environment of supporting to increase income, make debugging person select softwares such as Eclipse, Insight, JARI-IDE or third party's Integrated Development Environment for use according to self-condition and use habit, the operating system independent that it and user use, it still is Integrated Development Environment on the Linux that the user can freely select Windows; The present invention has simplified the in-line procedure with the Godson processor, has alleviated user's use burden; Adopt the system designer of Godson processor no longer to limit to the cross-compiler that uses particular version, can select the cross-compiler of different editions according to the difference of linux kernel for use, and do not worry there is not suitable exploitation debugging acid, for the widespread adoption of Godson processor provides technical guarantee.
Description of drawings
Fig. 1 is a connection schematic block diagram of the present invention.
Fig. 2 is the main control module schematic block diagram.
Embodiment
Following with reference to accompanying drawing, further describe concrete technical scheme of the present invention, so that those skilled in the art understands the present invention further, and do not constitute restriction to its right.
Embodiment 1.With reference to Fig. 1-2.A kind of Godson emulator terminal.
It comprises main control module, Ethernet interface, serial line interface, jtag interface and LED light;
Described main control module comprises AU1550 processor, SDRAM storer, NOR Flash, CPLD programming device and level transferring chip;
The SDRAM storer is connected on the sdram controller of AU1550 processor;
NOR Flash is connected on the static bus controller of AU1550 processor;
The CPLD programming device is connected on the static bus controller of AU1550 processor by bus mode;
The bus of described static bus controller comprises address bus A[28:23] and A[11:0], data bus D[31:0] and control bus;
Described control bus comprises RBE[3:0] signal, RWE signal, ROE signal, RCS signal and EWAIT signal; Wherein, RBE signal indication byte enable is selected, and low level is effective, and RBE0 is for data bus D[7:0], RBE1 is for data bus D[15:8], RBE2 is for data bus D[23:16], RBE3 is for data bus D[31:24]; RWE signal indication write-enable, low level is effective; ROE signal indication output enable, low level is effective; RCS represents that chip selection signal enables, and low level is effective; EWAIT signal indication external unit needs processor to increase the stand-by period, and low level is effective;
Level transferring chip is connected with the CPLD programming device by the JTAG signal, produces the level signal of 1.2V to 5V; Described JTAG signal comprises TRST signal, TDI signal, TDO signal, tck signal and tms signal;
Jtag interface is connected with level transferring chip by described JTAG signal, and jtag interface also comprises RST signal, power supply input and ground connection input; Described RST signal generates Open Drain output signal by the CPLD programming device, and power supply input and ground connection input are from Target Board; Level transferring chip is input as level reference with power supply, produces and target machine level level signal same;
Ethernet interface is connected with AU1550 processor MAC0 controller by the PHY physical chip;
Serial line interface is connected by the UART0 controller of MAX232 chip and AU1550 processor;
LED light is connected with the CPLD programming device, and it comprises STA pilot lamp and TAR pilot lamp, the Chang Liang by two pilot lamp, extinguishes and the duty of the state representation emulator that glimmers.
Claims (1)
1. Godson emulator terminal is characterized in that:
It comprises main control module, Ethernet interface, serial line interface, jtag interface and LED light;
Described main control module comprises AU1550 processor, SDRAM storer, NOR Flash, CPLD programming device and level transferring chip;
The SDRAM storer is connected on the sdram controller of AU1550 processor;
NOR Flash is connected on the static bus controller of AU1550 processor;
The CPLD programming device is connected on the static bus controller of AU1550 processor by bus mode;
The bus of described static bus controller comprises address bus A[28:23] and A[11:0], data bus D[31:0] and control bus;
Described control bus comprises RBE[3:0] signal, RWE signal, ROE signal, RCS signal and EWAIT signal; Wherein, RBE signal indication byte enable is selected, and low level is effective, and RBE0 is for data bus D[7:0], RBE1 is for data bus D[15:8], RBE2 is for data bus D[23:16], RBE3 is for data bus D[31:24]; RWE signal indication write-enable, low level is effective; ROE signal indication output enable, low level is effective; RCS represents that chip selection signal enables, and low level is effective; EWAIT signal indication external unit needs processor to increase the stand-by period, and low level is effective;
Level transferring chip is connected with the CPLD programming device by the JTAG signal, produces the level signal of 1.2V to 5V; Described JTAG signal comprises TRST signal, TDI signal, TDO signal, tck signal and tms signal;
Jtag interface is connected with level transferring chip by described JTAG signal, and jtag interface also comprises RST signal, power supply input and ground connection input; Described RST signal generates Open Drain output signal by the CPLD programming device, and power supply input and ground connection input are from Target Board; Level transferring chip is input as level reference with power supply, produces and target machine level level signal same;
Ethernet interface is connected with AU1550 processor MAC0 controller by the PHY physical chip;
Serial line interface is connected by the UART0 controller of MAX232 chip and AU1550 processor;
LED light is connected with the CPLD programming device, and it comprises STA pilot lamp and TAR pilot lamp, the Chang Liang by two pilot lamp, extinguishes and the duty of the state representation emulator that glimmers.
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| CN201010553498A CN101989222B (en) | 2010-11-22 | 2010-11-22 | Loongson simulator terminal |
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| CN201010553498A CN101989222B (en) | 2010-11-22 | 2010-11-22 | Loongson simulator terminal |
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| CN101989222B CN101989222B (en) | 2012-10-03 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214132A (en) * | 2011-05-16 | 2011-10-12 | 曙光信息产业股份有限公司 | Method and device for debugging Loongson central processing unit (CPU), south bridge chip and north bridge chip |
| CN102567051A (en) * | 2011-12-14 | 2012-07-11 | 中标软件有限公司 | Method and device for preparing graphical installation system of Loongson platform |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020045952A1 (en) * | 2000-10-12 | 2002-04-18 | Blemel Kenneth G. | High performance hybrid micro-computer |
| CN1564136A (en) * | 2004-04-02 | 2005-01-12 | 清华大学 | Realizing method of cross regulator based on EJTAG components of targeting machine |
| CN101261601A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | Microprocessor debugging method and microprocessor debugging module |
-
2010
- 2010-11-22 CN CN201010553498A patent/CN101989222B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020045952A1 (en) * | 2000-10-12 | 2002-04-18 | Blemel Kenneth G. | High performance hybrid micro-computer |
| CN1564136A (en) * | 2004-04-02 | 2005-01-12 | 清华大学 | Realizing method of cross regulator based on EJTAG components of targeting machine |
| CN101261601A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | Microprocessor debugging method and microprocessor debugging module |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214132A (en) * | 2011-05-16 | 2011-10-12 | 曙光信息产业股份有限公司 | Method and device for debugging Loongson central processing unit (CPU), south bridge chip and north bridge chip |
| CN102214132B (en) * | 2011-05-16 | 2014-07-02 | 曙光信息产业股份有限公司 | Method and device for debugging Loongson central processing unit (CPU), south bridge chip and north bridge chip |
| CN102567051A (en) * | 2011-12-14 | 2012-07-11 | 中标软件有限公司 | Method and device for preparing graphical installation system of Loongson platform |
| CN102567051B (en) * | 2011-12-14 | 2015-03-25 | 中标软件有限公司 | Method and device for preparing graphical installation system of Loongson platform |
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| CN101989222B (en) | 2012-10-03 |
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Address after: Sinpo District of Jiangsu city of Lianyungang province Lian Hai road 222000 No. 42 Patentee after: CSIC Information Technology Co.,Ltd. Address before: Sinpo District of Jiangsu city of Lianyungang province Lian Hai road 222000 No. 42 Patentee before: LIANYUNGANG JARI SHENRUAN TECHNOLOGY Co.,Ltd. |
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Address after: 222000 No. 42, Hailian East Road, Xinpu District, Lianyungang City, Jiangsu Province Patentee after: China Shipbuilding Digital Information Technology Co.,Ltd. Address before: 222000 No. 42, Hailian East Road, Xinpu District, Lianyungang City, Jiangsu Province Patentee before: CSIC Information Technology Co.,Ltd. |