CN101986433A - Bipolar junction transistor based on silicon-on-insulator and manufacturing method thereof - Google Patents
Bipolar junction transistor based on silicon-on-insulator and manufacturing method thereof Download PDFInfo
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- CN101986433A CN101986433A CN2010105183975A CN201010518397A CN101986433A CN 101986433 A CN101986433 A CN 101986433A CN 2010105183975 A CN2010105183975 A CN 2010105183975A CN 201010518397 A CN201010518397 A CN 201010518397A CN 101986433 A CN101986433 A CN 101986433A
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Abstract
The invention discloses a bipolar junction transistor based on a silicon-on-insulator, comprising an SOI substrate, a shallow trench isolation, an active region, a collector region, a base region, dielectric layers and an emitter region, wherein the SOI substrate further comprises a silicon-based substrate and an oxide buried layer formed on the silicon-based substrate; the shallow trench isolation is formed in the SOI substrate; the active region is formed in the SOI substrate by the shallow trench isolation and is positioned in a region between the shallow trench isolations; the collector region is formed in the active region; the base region is formed on the collector region and is positioned on the surface of the active region; the dielectric layers are distributed on the surface of the active region at interval; and the emitter region is formed on the dielectric layer. In the invention, dielectric layers distributed at interval are deposited on the surface of the active region, and a certain interval is formed between the dielectric layers, so that the emitter region formed on the dielectric layer has same emitter region width and satisfies the consistency and the reproducibility of the bipolar junction transistor based on the silicon-on-insulator.
Description
Technical field
The present invention relates to semiconductor device and manufacture method thereof, relate in particular to a kind of bipolar junction transistor and manufacture method thereof based on silicon-on-insulator.
Background technology
(Silicon-On-Insulator, SOI) technology is to introduce one deck between at the bottom of top layer silicon and the backing to bury oxide layer to silicon-on-insulator.By on insulator, forming semiconductive thin film, SOI have body silicon incomparable advantage: can realize the dielectric isolation of components and parts in the integrated circuit, thoroughly eliminate the parasitic latch-up in the body silicon CMOS circuit; Adopt the integrated circuit of SOI made to have also that parasitic capacitance is little, integration density is high, speed is fast, technology is simple, short-channel effect is little, and be specially adapted to advantage such as low-voltage and low-power dissipation circuit.
See also Fig. 3, Figure 3 shows that the structural representation of existing silicon-on-insulator bipolar junction transistor 2.Described silicon-on-insulator bipolar junction transistor 2 comprises the 2nd SOI substrate 20 with second buried oxide layer 201, and the thickness of described second buried oxide layer 201 is 1500 dusts; Be formed on second shallow trench isolation in described second buried oxide layer 201 from 21; At second active area 22 of second shallow trench isolation between 21; Be formed on the 2nd n type collector region 23 in described second active area 22; Be formed on described the 2nd n type collector region 23, and be positioned at the 2nd p type base 24 on described second active area 22 surfaces; At the second p type base 24 and second shallow trench isolation between 21, and be positioned at second on described the 2nd n type collector region 23 than shallow trench isolation from 25; Second active area, 22 places between the 21 and the 2nd n type collector region 23 form the second collector electrode plug 231 at second shallow trench isolation; At the 2nd SOI substrate 20 surface deposition polysilicons, and form second emitter region 26, and carry out spacer medium 27 in described etching polysilicon district and fill by technologies such as patterning and etchings.
Significantly, form in the process of second emitter region 26 in etching, the uncertainty of etch areas must cause described second emitter region 26 to have uncertain emitter region width, finally makes silicon-on-insulator bipolar junction transistor 2 not have consistency and reproducibility.More seriously, reduce the product yield, increase manufacturing cost.
At the problem that prior art exists, this case designer relies on the industry experience for many years of being engaged in, and the active research improvement is so there be bipolar junction transistor and the manufacture method thereof that the present invention is based on silicon-on-insulator.
Summary of the invention
The present invention be directed in the prior art, the emitter region of existing silicon-on-insulator bipolar junction transistor has probabilistic emitter region width, and cause the silicon-on-insulator bipolar junction transistor not have defectives such as consistency and reproducibility, a kind of novel bipolar junction transistor based on silicon-on-insulator is provided.
Another purpose of the present invention is in the prior art, the emitter region of existing silicon-on-insulator bipolar junction transistor has probabilistic emitter region width in manufacture process, and cause the silicon-on-insulator bipolar junction transistor not have defectives such as consistency and reproducibility, a kind of manufacture method of novel bipolar junction transistor based on silicon-on-insulator is provided.
In order to address the above problem, the invention provides a kind of bipolar junction transistor based on silicon-on-insulator, described bipolar junction transistor based on silicon-on-insulator comprises: SOI substrate, described SOI substrate further comprise silicon-based substrate and are formed on buried oxide layer on the described silicon-based substrate; Shallow trench isolation from, be formed in the described SOI substrate; Active area is isolated in the described SOI substrate by described shallow trench and defines, and described active area shallow trench isolation between the zone; Collector region with first conductive ions is formed in the described active area; Base with second conductive ions is formed on the described collector region, and is positioned at described surfaces of active regions; Dielectric layer is distributed in described surfaces of active regions; Emitter region with first conductive ions is formed on the described dielectric layer.Described buried oxide layer is the oxide skin(coating) of Doped n-type ion.The width of described emitter region is decided based on dielectric layer spacing spaced apart.
Optionally, described first conductive ions is a n type ion, and described second conductive ions is a p type ion.
Optionally, described first conductive ions is a p type ion, and described second conductive ions is a n type ion.
Optionally, described dielectric layer is an oxide skin(coating).
Optionally, described oxide skin(coating) is a silicon dioxide layer.
For solving another purpose of the present invention, the invention provides the method for a kind of manufacturing based on the bipolar junction transistor of silicon-on-insulator, described manufacturing comprises based on the method for the bipolar junction transistor of silicon-on-insulator: on the SOI substrate etching shallow trench isolation from, and definition is based on the active area of the bipolar junction transistor of silicon-on-insulator; In described active area, form collector region with first conductive ions; Deposit forms the base with second conductive ions on described collector region; At the surface deposition dielectric layer of active area, described dielectric layer distributes at the spaced surface of described active area; Surface at dielectric layer forms the emitter region with first conductive ions.
Optionally, described first conductive ions is a n type ion, and described second conductive ions is a p type ion.
Optionally, described first conductive ions is a p type ion, and described second conductive ions is a n type ion.
Optionally, described dielectric layer is an oxide skin(coating).
Optionally, described oxide skin(coating) is a silicon dioxide layer.
In sum, the present invention passes through at the surface deposition of active area dielectric layer spaced apart, and has certain interval between the described dielectric layer, just make that the emitter region that is formed on the described dielectric layer has identical emitter region width, satisfy consistency and reproducibility based on the bipolar junction transistor of silicon-on-insulator.
Description of drawings
Fig. 1 is the structural scheme of mechanism that the present invention is based on the bipolar junction transistor of silicon-on-insulator;
Fig. 2 is the manufacturing flow chart that the present invention is based on the bipolar junction transistor of silicon-on-insulator;
Fig. 3 is the structural representation of existing silicon-on-insulator bipolar junction transistor.
Embodiment
By the technology contents, the structural feature that describe the invention in detail, reached purpose and effect, described in detail below in conjunction with embodiment and conjunction with figs..
See also Fig. 1, Figure 1 shows that structural representation based on the bipolar junction transistor 1 of silicon-on-insulator.Described bipolar junction transistor 1 based on silicon-on-insulator adopts the existing integrated circuits manufacturing process to form first shallow trench isolation from 11 on a SOI substrate 10, to define first active area 12 of described bipolar junction transistor 1 based on silicon-on-insulator.
A described SOI substrate 10 comprises silicon-based substrate 101 and is formed on first buried oxide layer 102 on the described silicon-based substrate 101.
In described first active area 12, form a n type collector region 13.In described first active area 12, and the surface that is positioned at a described n type collector region 13 forms a p type base 14.First active area, 12 places between the 11 and the one n type collector region 13 form the first collector electrode plug 131 at first shallow trench isolation.The described first collector electrode plug 131 has severe doped n type ion.The first collector electrode plug 131 of described severe Doped n-type ion is by carry out the preparation of n type ions diffusion from the described first collector electrode plug 131 surfaces to first buried oxide layer 102.The described first collector electrode plug 131 is electrical the contact conducting resistance that provide low of n type collector region 13 with collector electrode (not shown).Between the first p type base 14 and the first collector electrode plug 131, and be positioned at a described n type collector region 13 surface formation first utmost point shallow trench isolations from 15.
Thin film deposition is carried out on surface at a described SOI substrate 10, and forms dielectric layer 16 as shown in Figure 1 by technologies such as etchings.Described dielectric layer 16 covers the surface of first active area 12 at interval, and extends from 14 surfaces, the 15 and the one p type base at first utmost point shallow trench isolation.Described dielectric layer 16 is a silicon dioxide layer.Has certain interval 161 between the described dielectric layer 16.
The polysilicon deposit is carried out on surface at described first active area 12 and described dielectric layer 16, and defines first multi-crystal silicon area 17 and second multi-crystal silicon area 18 by technologies such as etchings.Described first multi-crystal silicon area 17 is carried out n type ion doping, to form first emitter region 171.The width of described first emitter region 171 just is the size at interval 161.Based on the width of the emitter region 171 of the bipolar junction transistor 1 of silicon-on-insulator based on dielectric layer 16 161 spacings that distribute and deciding at interval.Second multi-crystal silicon area 18 is carried out p type ion doping, derive end 181 to form the base.Derive formation dielectric wall 19 between the end 181 in described first emitter region 171 and base.Described dielectric wall 19 is used for first emitter region 171 derives the electrical isolation of end 181 with the base.
See also Fig. 2, the manufacturing flow chart of the described bipolar junction transistor 1 based on silicon-on-insulator of Fig. 2.The manufacturing process of described bipolar junction transistor 1 based on silicon-on-insulator comprises:
Step S11: etching first shallow trench isolation is from 11 on a SOI substrate 10, and definition is based on first active area 12 of the bipolar junction transistor 1 of silicon-on-insulator;
Step S12: in described first active area 12, form a n type collector region 13;
Step S13: deposit forms a p type base 14 on a n type collector region 13; A described p type base 14 is positioned on the described n type collector region 13, and is in the surface of a SOI substrate 10.In the present embodiment, the deposit of a p type base 14 is the vapour phase epitaxy processing procedure.A described P type base 14 adopts the boron plasma to carry out the ion injection or the growth in situ mode prepares.
Step S14: at the surface deposition dielectric layer 16 of first active area 12; Described dielectric layer 16 distributes at the spaced surface of described first active area 12.Has certain interval 161 between the described dielectric layer 16.
Step S15: form first emitter region 171 on the surface of dielectric layer 16; At first, at the surface deposition polysilicon layer of first active area 12; The mode of low-pressure chemical vapor phase deposition (LPCVD) is adopted in the deposit of described polysilicon layer.Then, described polysilicon layer is carried out technologies such as patterning and photoetching, and carry out n type ion and inject to form first emitter region 171.The width of described first emitter region 171 just is the interval 161 between the dielectric layer 16.
In sum, the present invention passes through at the surface deposition of first active area 12 dielectric layer 16 spaced apart, and has certain interval 161 between the described dielectric layer 16, just make that first emitter region 171 that is formed on the described dielectric layer 16 has identical emitter region width, satisfy consistency and reproducibility based on the bipolar junction transistor 1 of silicon-on-insulator.
Those skilled in the art all should be appreciated that, under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (13)
1. the bipolar junction transistor based on silicon-on-insulator is characterized in that, described bipolar junction transistor based on silicon-on-insulator comprises:
SOI substrate, described SOI substrate further comprise silicon-based substrate and are formed on buried oxide layer on the described silicon-based substrate;
Shallow trench isolation from, be formed in the described SOI substrate;
Active area is isolated in the described SOI substrate by described shallow trench and defines, and described active area shallow trench isolation between the zone;
Collector region has first conductive ions, and is formed in the described active area;
The base has second conductive ions, and is formed on the described collector region, and is positioned at described surfaces of active regions;
Dielectric layer is distributed in described surfaces of active regions;
The emitter region has first conductive ions, and is formed on the described dielectric layer.
2. the bipolar junction transistor based on silicon-on-insulator as claimed in claim 1 is characterized in that: the width of described emitter region is decided based on dielectric layer spacing spaced apart.
3. the bipolar junction transistor based on silicon-on-insulator as claimed in claim 1 is characterized in that: described first conductive ions is a n type ion, and second conductive ions is a p type ion.
4. the bipolar junction transistor based on silicon-on-insulator as claimed in claim 1 is characterized in that: described first conductive ions is a p type ion, and second conductive ions is a n type ion.
5. the bipolar junction transistor based on silicon-on-insulator as claimed in claim 1 is characterized in that: described emitter region has n type ion doping.
6. the bipolar junction transistor based on silicon-on-insulator as claimed in claim 1 is characterized in that: described dielectric layer is an oxide skin(coating).
7. the bipolar junction transistor based on silicon-on-insulator as claimed in claim 6 is characterized in that: described oxide skin(coating) is a silicon dioxide layer.
8. the manufacture method of the bipolar junction transistor based on silicon-on-insulator as claimed in claim 1 is characterized in that described manufacturing comprises based on the method for the bipolar junction transistor of silicon-on-insulator:
On the SOI substrate etching shallow trench isolation from, and definition is based on the active area of the bipolar junction transistor of silicon-on-insulator;
In described active area, form collector region with first conductive ions;
Deposit forms the base with second conductive ions on described collector region;
At the surface deposition dielectric layer of active area, described dielectric layer distributes at the spaced surface of described active area;
Surface at dielectric layer forms the emitter region with first conductive ions.
9. the manufacture method of the bipolar junction transistor based on silicon-on-insulator as claimed in claim 8, it is characterized in that: the width of described emitter region is decided based on dielectric layer spacing spaced apart.
10. the manufacture method of the bipolar junction transistor based on silicon-on-insulator as claimed in claim 8, it is characterized in that: described first conductive ions is a n type ion, second conductive ions is a p type ion.
11. the manufacture method of the bipolar junction transistor based on silicon-on-insulator as claimed in claim 8, it is characterized in that: described first conductive ions is a p type ion, and second conductive ions is a n type ion.
12. the manufacture method of the bipolar junction transistor based on silicon-on-insulator as claimed in claim 8, it is characterized in that: described dielectric layer is an oxide skin(coating).
13. the manufacture method of the bipolar junction transistor based on silicon-on-insulator as claimed in claim 12, it is characterized in that: described oxide skin(coating) is a silicon dioxide layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103311272A (en) * | 2012-03-09 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Lateral mosfet with dielectric isolation trench |
| CN104362175A (en) * | 2014-11-20 | 2015-02-18 | 上海华虹宏力半导体制造有限公司 | Partially-depleted silicon-on-insulator triode structure |
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| CN101192536A (en) * | 2006-11-21 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for constructing NPN transistor by selective epitaxy |
| CN101673715A (en) * | 2009-09-25 | 2010-03-17 | 中国电子科技集团公司第二十四研究所 | Method for manufacturing shallow junction complementary bipolar transistor |
| CN101719503A (en) * | 2009-11-10 | 2010-06-02 | 上海宏力半导体制造有限公司 | Co-electrode thin SOI longitudinal bipolar transistor device and manufacturing method thereof |
| CN101719508A (en) * | 2009-11-10 | 2010-06-02 | 上海宏力半导体制造有限公司 | Thin SOI longitudinal bipolar transistor and manufacturing method thereof |
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| US20070001262A1 (en) * | 2005-07-01 | 2007-01-04 | International Business Machines Corporation | SOI bipolar transistors with reduced self heating |
| CN101192536A (en) * | 2006-11-21 | 2008-06-04 | 上海华虹Nec电子有限公司 | Method for constructing NPN transistor by selective epitaxy |
| CN101673715A (en) * | 2009-09-25 | 2010-03-17 | 中国电子科技集团公司第二十四研究所 | Method for manufacturing shallow junction complementary bipolar transistor |
| CN101719503A (en) * | 2009-11-10 | 2010-06-02 | 上海宏力半导体制造有限公司 | Co-electrode thin SOI longitudinal bipolar transistor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103311272A (en) * | 2012-03-09 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Lateral mosfet with dielectric isolation trench |
| CN103311272B (en) * | 2012-03-09 | 2016-09-14 | 台湾积体电路制造股份有限公司 | There is the (Silicon-on-insulator) MOSFET lateral of dielectric isolation groove |
| CN104362175A (en) * | 2014-11-20 | 2015-02-18 | 上海华虹宏力半导体制造有限公司 | Partially-depleted silicon-on-insulator triode structure |
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Application publication date: 20110316 |