CN101192536A

CN101192536A - Method for constructing NPN transistor by selective epitaxy

Info

Publication number: CN101192536A
Application number: CNA2006101185458A
Authority: CN
Inventors: 王乐
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-11-21
Filing date: 2006-11-21
Publication date: 2008-06-04
Anticipated expiration: 2026-11-21
Also published as: CN101192536B

Abstract

The invention discloses a method for using an NPN transistor with a selection extension structure. After wiping off of a photoresist which is on the surface of an oxide layer of a semiconductor substrate, the method selects an N type extension which is grown in a window to form a N<-> epitaxial layer; the oxide layer, a P type heteromorphic silicon layer and the oxide layer are deposited one by one on the epitaxial layer; an active region is formed by chemical wet etching; wet is carried out to etch the oxide layer which is under the P type heteromorphic silicon layer; the P type epitaxial layer grows selectively; the oxide layer on the surface is wiped off and a silicon nitride layer is deposited; after chemical wet etching, a N<+> heteromorphic silicon layer is deposited. The invention can effectively control the width of a base region of bipolar devices, reduces parasitic capacitance and increases the speed of the devices.

Description

Utilize the method for selective epitaxy structure NPN transistor

Technical field

The present invention relates to a kind of process for making of semiconductor integrated circuit, particularly relate to a kind of method of utilizing selective epitaxy structure NPN transistor.

Background technology

Bipolar transistor is one of device architecture that constitutes in modern large scale integrated circuit.The bipolar transistor advantage is that service speed is fast, the output current of unit chip area is big, the conducting voltage change is little, is suitable for making analog circuit.

Along with the continuous development of semiconductor technology, require more and more higher to device performance.In traditional bipolar transistor manufacture craft, usually adopt two step base/emitter region thermal processs to form effective base width, promptly carry out base boron earlier and inject/diffuse to form base stage, the phosphorus that carries out the emitter region again injects/diffuses to form emitter, obtains base width by the depth difference of base stage and emitter.It realizes complex process and poor controllability, is difficult to realize for the technology of base width less than 0.1 micron.Now the semiconductor integrated circuit linewidth requirements is being reduced day by day, existing process method can not adapt to the requirement of this technology trends.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method of utilizing selective epitaxy structure NPN transistor, effectively controls the bipolar device base width, reduces parasitic the appearance, improves device speed.

For solving the problems of the technologies described above, the method for utilizing selective epitaxy structure NPN transistor of the present invention comprises the steps:

Carrying out buried regions on Semiconductor substrate injects and spreads;

Remove the oxide layer that produces when described buried regions forms, then deposit growth layer of oxide layer;

Resist coating, exposure, chemical wet etching form a window on described oxide layer;

Remove photoresist, select the epitaxial growth of N type in described window, to form one deck N then ^-Epitaxial loayer;

Deposited oxide layer, P type polysilicon layer, oxide layer successively on described epitaxial loayer;

Be formed with the source region by chemical wet etching;

Oxide layer under the described P type of the wet etching polysilicon;

Selective growth P type epitaxial loayer;

Remove surface oxide layer, deposit silicon nitride layer then;

Behind this silicon nitride layer chemical wet etching, deposit N ⁺Polysilicon layer.

Adopt method of the present invention, the technology of utilizing the selective low-voltage extension to combine with the polycrystalline base/emitter in conjunction with self-registered technology, make up NPN transistor, can effectively control the bipolar device base width, improve response device speed, parasitic capacitance in the bipolar transistor that reduces to cause by thermal diffusion, and can mate well with the MOS device technology.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 to 10 is method process flow diagrams that utilize selective epitaxy structure NPN transistor of the present invention, by schematic sectional view, expresses the specific implementation of each processing step of one embodiment of the present invention among the figure.

Embodiment

The present invention proposes a kind of method of utilizing selective epitaxy to make up NPN transistor in conjunction with self-registered technology.Shown in Fig. 1～10, specify technological process of the present invention at a preferred embodiment.

The first step as shown in Figure 1, at first, adopts P (100) type silicon materials as Semiconductor substrate, and the method by ion injection and diffusion of impurities on this substrate forms a buried layer.Diffuseing to form in the technology of this buried layer, can form layer of oxide layer (SiO on its surface ₂).

Second step is referring to Fig. 2.Oxide layer described in the removal previous step is rapid adopts thermal oxidation process deposit growth one deck silicon oxide film (SiO on the surface of Semiconductor substrate and buried layer then ₂).

The 3rd step applied photoresist on described silicon oxide film, exposure, photoetching, and this silicon oxide film of etching forms a window (referring to Fig. 3) above described buried layer.

The 4th step, remove photoresist, by selective epitaxial growth, in described window, form N ^-Epitaxial loayer (referring to Fig. 4).This N ^-Epitaxial loayer is as the collector region of NPN transistor.

The 5th step is at described N ^-The surface of epitaxial loayer and silicon oxide film is deposited oxide layer, P type polysilicon, oxide layer (referring to Fig. 5) successively.This P type polysilicon can accurately be controlled little base width as the base region of NPN transistor by selective epitaxy structure base, improves device function.

In the 6th step, by chemical wet etching oxide layer, P type polysilicon, oxide layer, formation is positioned at described N ^-The active area (referring to Fig. 6) of epitaxial loayer top.

In the 7th step, adopt in the described active area of wet etching to be positioned at described polysilicon and N ^-Oxide layer between the epitaxial loayer, the lateral depth of etching should be less than N ^-The width of epitaxial loayer makes active area at N ^-The top of epitaxial loayer is inverse-T-shaped (referring to Fig. 7).

The 8th step, the N in described active area ^-Between epitaxial loayer and the P type polysilicon,, form P type epitaxial loayer (referring to Fig. 8) by selective epitaxial growth.

The 9th step, remove the oxide layer on described P type polysilicon layer surface, deposit one deck silicon nitride (referring to Fig. 9) then, the method for deposit can adopt CVD or other modes commonly used, also can adopt the mode of growth to form.

The tenth step, carry out photoetching, open emitting area, carry out N then ⁺The polysilicon deposit, this N ⁺Polysilicon layer is as the emitter region of NPN transistor.So far, finished the making of NPN transistor.

Only be in order to express the particular content of processing step of the present invention, so and not drawn on scale in accompanying drawing of the present invention.The concrete process that each processing step is realized, needn't spend creative work to one skilled in the art just can implement, for the specific implementation method that provides among the present invention, just describe as embodiment, be not limited thereto when specifically implementing.

Claims

1. a method of utilizing selective epitaxy structure NPN transistor comprises the steps: to carry out buried regions and injects and spread on Semiconductor substrate; Remove the oxide layer that produces when described buried regions forms, then deposit growth layer of oxide layer; Resist coating, exposure, chemical wet etching form a window on described oxide layer; It is characterized in that: also comprise, remove photoresist, select the epitaxial growth of N type in described window, to form one deck N then ^-Epitaxial loayer; Deposited oxide layer, P type polysilicon layer, oxide layer successively on described epitaxial loayer; Be formed with the source region by chemical wet etching; Adopt the oxide layer under the described P type of the wet etching polysilicon layer again; Selective growth P type epitaxial loayer; Remove surface oxide layer, deposit silicon nitride layer then; Behind the chemical wet etching, deposit N ⁺Polysilicon layer.

2. the method for utilizing selective epitaxy structure NPN transistor according to claim 1 is characterized in that: the lateral depth of etching should be less than N during described wet etching ^-The width of epitaxial loayer.