CN101980493A - Method for realizing 2.4GHz digital baseband signal demodulation of wireless sensor network - Google Patents

Abstract

The invention discloses a method for realizing the 2.4GHz digital baseband signal demodulation of a wireless sensor network. A spreading code synchronization and symbol demodulation module detects a modulus continuously exceeding a preset threshold for eight times so as to find the head of a spreading code for synchronization; in addition, a found maximum, namely, the introduction of a maximum likelihood estimation method, simultaneously overcomes the defects of poor demodulation effect caused by the conventional demodulation concept of chip-by-chip demodulation, and the poor demodulation effect caused by the high complexity and the influence and sensitivity of the coherent chip-by-chip demodulation on/to the frequency deviation recovery and phase deviation recovery; and maximum likelihood estimation and demodulation are directly performed on spreading symbols to achieve good demodulation effect which is not influenced by the outside due to sensitivity.

Description

Realize wireless sensor network 2.4GHz digital baseband signal demodulation method

Technical field

The invention belongs to the signal processing technology field of wireless sensor network, be specifically related to a kind of realization radio sensing network 2.4GHz digital baseband signal demodulation method.

Background technology

In recent years, development along with low-cost wireless communication system chip technology, wireless sensor network has obtained application more and more widely, and corresponding 802.15.4 agreement stipulates that its 2.4GHz physical layer adopts the O-QPSK modulation system of direct sequence spread spectrum and semisinusoidal moulding, when transmitting terminal sends data, high 4 order was divided into two symbols after the data of physical frame were hanged down 4 earlier according to every byte, its symbol kind amounts to 16 kinds, then according to the mode band spectrum modulation of direct sequence spread spectrum, every kind of symbol-modulated becomes spreading code, after to the spreading code modulation conversion, carry out the O-QPSK modulation, again the spread spectrum O-QPSK signal after the modulation is carried out the semisinusoidal moulding, and Q road signal is delayed the half-chip duration, can obtain the protocol signal baseband waveform.And receiving terminal is when receiving data, and being about to down-sampled complex signal stream carries out the spreading code that demodulation obtains the symbol correspondence, again it is carried out the O-QPSK demodulation, obtains corresponding symbol, finally obtain earlier low 4 thus after high 4 bytes of stream data.

Said process is at k sampled point complex signal r of the down-sampled complex sampling signal flow of receiving terminal _kFor:

θ wherein _kThe phase place of representing k sampled point, k is the integer more than or equal to 0, ω ₀The expression frequency shift (FS), φ represents skew, T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k sampled point, N ₀And E _SRepresent the power of noise and signal respectively.

O-QPSK demodulation implementation at down-sampled complex sampling signal is mainly coherent demodulation, zero intermediate frequency zero passage detection, angle demodulation and the piece demodulation of adopting by chip at present.Though and the coherent demodulation demodulation effect of pursuing chip is best, frequency deviation is recovered and skew is recovered but do, the complexity height, and performance is subjected to having a strong impact on of residual frequency departure and skew, particularly frequency deviation is recovered and the skew recovery influence sensitivity, bring the shortcoming of demodulation weak effect, and be wanting in the demodulation effect by zero intermediate frequency zero passage detection, angle demodulation and these demodulation modes of piece demodulation of chip.

Summary of the invention

In order to overcome the deficiency that above-mentioned prior art exists, the object of the present invention is to provide a kind of realization radio sensing network 2.4GHz digital baseband signal demodulation method, overcome demodulation thinking in the past and all be basically the shortcoming of carrying out the demodulation weak effect that demodulation brings by chip, also overcome simultaneously coherent demodulation complexity by chip high and to frequency deviation recover and the skew recovery influence the shortcoming that sensitivity is brought the demodulation weak effect, and directly the symbol of spread spectrum is carried out maximal possibility estimation and demodulation, demodulation is effective and can be owing to the responsive ectocine that is subjected to.

In order to achieve the above object, the technical solution adopted in the present invention is:

A kind of realization radio sensing network 2.4GHz digital baseband signal demodulation method, step is as follows:

Step 1: under the driving of synchronizing clock signals, input complex sampling signal enters the conjugation time-delay module that multiplies each other, this conjugation time-delay module that multiplies each other obtains down-sampled complex sampling signal flow by down-sampled mode earlier to the complex sampling signal of input, then according to K value order from small to large, successively one by one to K down-sampled complex sampling signal r _kObtaining the corresponding down-sampled complex sampling signal of delay after postponing a clock cycle, also is K+1 down-sampled complex sampling signal r _K+1, immediately to the individual down-sampled complex sampling signal r of the K+1 of gained _K+1After getting conjugation, again with the K+1 after the conjugation down-sampled complex sampling signal r _K+1K down-sampled complex sampling signal r with its correspondence _kMultiply each other, obtain

Signal, like this

Signal has been formed according to the order from small to large of K value

Signal flow, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 2: the conjugation time-delay is multiplied each other module earlier according to the order from small to large of K value, will

In the signal flow from

Signal arrives

Each signal, send into from right to left among the one dimension shifted data chain of registers A that comprises 32 registers in the corresponding register, and then according to the order from small to large of K value, from

Beginning, every through a clock cycle, data will

In the signal flow each In the register of the leftmost side of signal immigration one dimension shifted data chain of registers A, original in each register of one dimension shifted data chain of registers A

Signal all moves right to adjacent register, and the rightmost side register of one dimension shifted data chain of registers A is original

Signal is removed, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 3: simultaneously, each register that comprises the one dimension shifted data chain of registers A of 32 registers, corresponding one by one with 32 registers among the circulating shift data chain of registers B, reach the symbol demodulation module synchronously by to cyclic shift and be written into register and write the cyclic shift sign or be written under the control of sign at spreading code, 32 registers among cyclic shift and the data register chain B are corresponding cyclic shift pattern or be written into mode operation respectively just, before spreading code is finished synchronously, cyclic shift and data register chain B are under the pattern of being written into, and one dimension shifted data chain of registers A is with its each register

Signal is written in the register of the correspondence among cyclic shift and the data register chain B one by one, and has new signal to move among the one dimension shifted data chain of registers A, just with its each register

Signal Synchronization is written in the register of the correspondence among cyclic shift and the data register chain B one by one, and after finishing synchronously at spreading code, cyclic shift and data register chain B are under the cyclic shift pattern, every through a clock cycle, each register among cyclic shift and the data register chain B Signal all moves right to adjacent register, and its rightmost side register

Signal moves in the register of the leftmost side, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 4: every through a clock cycle under the driving of synchronizing clock signals, with each register among cyclic shift and the data register chain B

Signal moves into corresponding parallel correlator, and corresponding parallel correlator is with each register among the chain of registers B

Signal is respectively with corresponding

Multiply each other, obtain 32 thus

Value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence;

Step 5: whenever obtain described 32 After the value, send into immediately in the summation module of parallel correlator, this summation module is with 32 The value summation that adds up obtains Accumulated value, parallel correlator are just with this

The mould module is asked in the accumulated value input, and this asks the mould module right

Accumulated value is asked mould, obtains

Mould value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence;

Step 6: ask the mould module to incite somebody to action

The mould value is input to spreading code and reaches the symbol demodulation module synchronously, detects when spreading code reaches the symbol demodulation module synchronously

The mould value is continuous when surpassing preset threshold value 8 times, pass through again after continuous 32 clock cycle, to cyclic shift and be written into register and write the cyclic shift sign, thereby cyclic shift and data register chain B are in into the cyclic shift pattern, and wherein the expression formula of K down-sampled complex sampling signal rk is:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence

Step 7: under the driving of synchronizing clock signals, spreading code reaches the symbol demodulation module synchronously and just begins counting, promptly asks the every input of mould module once simultaneously Mould value, spreading code reach the symbol demodulation module synchronously and just count value are increased 1, and the count value initial value is 0, and spreading code reaches the symbol demodulation module synchronously when whenever finishing counting 32 times, just count value is returned 0, then according to asking the mould module to import when these the 32 times countings

Maximum in the mould value is noted the count value when maximum occurring, and notes parallel correlator gained when maximum occurring

The real part of symbol of accumulated value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 1, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kValue for k spread-spectrum code chip of symbol 0 correspondence

Step 8: spreading code reaches the symbol demodulation module synchronously then described count value when maximum occurring is carried out rounding divided by 4 after, and parallel correlator gained when maximum occurring

The real part of symbol of accumulated value can obtain corresponding symbol, and this symbol is exported by high 4 bytes of stream data after hanging down 4 earlier, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence

Step 9: under the driving of synchronizing clock signals, when described symbol is exported, simultaneously to cyclic shift and be written into register and write and be written into sign, thereby cyclic shift and data register chain B are in the pattern of being written into, and after a clock cycle, again to cyclic shift and be written into register and write the cyclic shift sign, thereby cyclic shift and data register chain B are in the cyclic shift pattern, return again in the step 6 and carry out.

In the described step 7 spreading code reach synchronously the symbol demodulation module adopt mould 32 clock counters realize count value increase 1 and count value return 0 operation.

Spreading code reaches the symbol demodulation module synchronously and comprises the maximum logging modle.

The present invention detects by spreading code is reached the symbol demodulation module synchronously

The mould value surpasses preset threshold value continuous 8 times, has finished the physical frame frame head with this and has detected and synchronous two tasks of spreading code, in addition by finding out

Maximum, promptly having introduced maximum Likelihood, to have overcome demodulation thinking in the past all be the shortcoming of carrying out the demodulation weak effect that demodulation brings by chip basically, also overcome simultaneously coherent demodulation complexity by chip high and to frequency deviation recover and the skew recovery influence the shortcoming that sensitivity is brought the demodulation weak effect, and directly the symbol of spread spectrum is carried out maximal possibility estimation and demodulation, demodulation is effective and can be owing to the responsive ectocine that is subjected to.

Embodiment

The present invention will be described in more detail below in conjunction with execution mode.

Realize radio sensing network 2.4GHz digital baseband signal demodulation method, step is as follows:

Step 1: under the driving of synchronizing clock signals, input complex sampling signal enters the conjugation time-delay module that multiplies each other, this conjugation time-delay module that multiplies each other obtains down-sampled complex sampling signal flow by down-sampled mode earlier to the complex sampling signal of input, then according to K value order from small to large, successively one by one to K down-sampled complex sampling signal r _kObtaining the corresponding down-sampled complex sampling signal of delay after postponing a clock cycle, also is K+1 down-sampled complex sampling signal r _K+1, immediately to the individual down-sampled complex sampling signal r of the K+1 of gained _K+1After getting conjugation, again with the K+1 after the conjugation down-sampled complex sampling signal r _K+1K down-sampled complex sampling signal r with its correspondence _kMultiply each other, obtain

Signal, like this

Signal has been formed according to the order from small to large of K value

Signal flow, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 2: the conjugation time-delay is multiplied each other module earlier according to the order from small to large of K value, will

In the signal flow from

Signal arrives

Each signal, send into from right to left among the one dimension shifted data chain of registers A that comprises 32 registers in the corresponding register, and then according to the order from small to large of K value, from

Beginning, every through a clock cycle, data will

In the signal flow each In the register of the leftmost side of signal immigration one dimension shifted data chain of registers A, original in each register of one dimension shifted data chain of registers A

Signal all moves right to adjacent register, and the rightmost side register of one dimension shifted data chain of registers A is original

Signal is removed, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 3: simultaneously, each register that comprises the one dimension shifted data chain of registers A of 32 registers, corresponding one by one with 32 registers among the circulating shift data chain of registers B, reach the symbol demodulation module synchronously by to cyclic shift and be written into register and write the cyclic shift sign or be written under the control of sign at spreading code, 32 registers among cyclic shift and the data register chain B are corresponding cyclic shift pattern or be written into mode operation respectively just, before spreading code is finished synchronously, cyclic shift and data register chain B are under the pattern of being written into, and one dimension shifted data chain of registers A is with its each register

Signal is written in the register of the correspondence among cyclic shift and the data register chain B one by one, and has new signal to move among the one dimension shifted data chain of registers A, just with its each register

Signal Synchronization is written in the register of the correspondence among cyclic shift and the data register chain B one by one, and after finishing synchronously at spreading code, cyclic shift and data register chain B are under the cyclic shift pattern, every through a clock cycle, each register among cyclic shift and the data register chain B

Signal all moves right to adjacent register, and its rightmost side register

Signal moves in the register of the leftmost side, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 4: every through a clock cycle under the driving of synchronizing clock signals, with each register among cyclic shift and the data register chain B

Signal moves into corresponding parallel correlator, and corresponding parallel correlator is with each register among the chain of registers B

Signal is respectively with corresponding

Multiply each other, obtain 32 thus

Value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence;

Step 5: whenever obtain described 32

After the value, send into immediately in the summation module of parallel correlator, this summation module is with 32

The value summation that adds up obtains

Accumulated value, parallel correlator are just with this

The mould module is asked in the accumulated value input, and this asks the mould module right

Accumulated value is asked mould, obtains

Mould value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence;

Step 6: ask the mould module to incite somebody to action The mould value is input to spreading code and reaches the symbol demodulation module synchronously, detects when spreading code reaches the symbol demodulation module synchronously

The mould value is continuous when surpassing preset threshold value 8 times, pass through again after continuous 32 clock cycle, to cyclic shift and be written into register and write the cyclic shift sign, thereby cyclic shift and data register chain B are in into the cyclic shift pattern, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence

Step 7: under the driving of synchronizing clock signals, spreading code reaches the symbol demodulation module synchronously and just begins counting, promptly asks the every input of mould module once simultaneously

Mould value, spreading code reach the symbol demodulation module synchronously and just count value are increased 1, and the count value initial value is 0, and spreading code reaches the symbol demodulation module synchronously when whenever finishing counting 32 times, just count value is returned 0, then according to asking the mould module to import when these the 32 times countings Maximum in the mould value is noted the count value when maximum occurring, and notes parallel correlator gained when maximum occurring

The real part of symbol of accumulated value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 1, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein q _kValue for k spread-spectrum code chip of symbol 0 correspondence

Step 8: spreading code reaches the symbol demodulation module synchronously then described count value when maximum occurring is carried out rounding divided by 4 after, and parallel correlator gained when maximum occurring

The real part of symbol of accumulated value can obtain corresponding symbol, and this symbol is exported by high 4 bytes of stream data after hanging down 4 earlier, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence

Step 9: under the driving of synchronizing clock signals, when described symbol is exported, simultaneously to cyclic shift and be written into register and write and be written into sign, thereby cyclic shift and data register chain B are in the pattern of being written into, and after a clock cycle, again to cyclic shift and be written into register and write the cyclic shift sign, thereby cyclic shift and data register chain B are in the cyclic shift pattern, return again in the step 6 and carry out.

In the described step 7 spreading code reach synchronously the symbol demodulation module adopt mould 32 clock counters realize count value increase 1 and count value return 0 operation.

Spreading code reaches the symbol demodulation module synchronously and comprises the maximum logging modle.The present invention detects by spreading code is reached the symbol demodulation module synchronously

The mould value surpasses preset threshold value continuous 8 times, finds the head of spreading code so that carry out synchronously with this, in addition by finding out

Maximum, promptly having introduced maximum Likelihood, to have overcome demodulation thinking in the past all be the shortcoming of carrying out the demodulation weak effect that demodulation brings by chip basically, also overcome simultaneously coherent demodulation complexity by chip high and to frequency deviation recover and the skew recovery influence the shortcoming that sensitivity is brought the demodulation weak effect, and directly the symbol of spread spectrum is carried out maximal possibility estimation and demodulation, demodulation is effective and can be owing to the responsive ectocine that is subjected to.

Claims (3)

1. realize radio sensing network 2.4GHz digital baseband signal demodulation method for one kind, it is characterized in that step is as follows:

Step 1: under the driving of synchronizing clock signals, input complex sampling signal enters the conjugation time-delay module that multiplies each other, this conjugation time-delay module that multiplies each other obtains down-sampled complex sampling signal flow by down-sampled mode earlier to the complex sampling signal of input, then according to K value order from small to large, successively one by one to K down-sampled complex sampling signal r _kObtaining the corresponding down-sampled complex sampling signal of delay after postponing a clock cycle, also is K+1 down-sampled complex sampling signal r _K+1, immediately to the individual down-sampled complex sampling signal r of the K+1 of gained _K+1After getting conjugation, again with the K+1 after the conjugation down-sampled complex sampling signal r _K+1K down-sampled complex sampling signal r with its correspondence _kMultiply each other, obtain

Signal, like this Signal has been formed according to the order from small to large of K value

Signal flow, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 2: the conjugation time-delay is multiplied each other module earlier according to the order from small to large of K value, will

In the signal flow from

Signal arrives Each signal, send into from right to left among the one dimension shifted data chain of registers A that comprises 32 registers in the corresponding register, and then according to the order from small to large of K value, from

Beginning, every through a clock cycle, data will

In the signal flow each

In the register of the leftmost side of signal immigration one dimension shifted data chain of registers A, original in each register of one dimension shifted data chain of registers A

Signal all moves right to adjacent register, and the rightmost side register of one dimension shifted data chain of registers A is original

Signal is removed, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 3: simultaneously, each register that comprises the one dimension shifted data chain of registers A of 32 registers, corresponding one by one with 32 registers among the circulating shift data chain of registers B, reach the symbol demodulation module synchronously by to cyclic shift and be written into register and write the cyclic shift sign or be written under the control of sign at spreading code, 32 registers among cyclic shift and the data register chain B are corresponding cyclic shift pattern or be written into mode operation respectively just, before spreading code is finished synchronously, cyclic shift and data register chain B are under the pattern of being written into, and one dimension shifted data chain of registers A is with its each register

Signal is written in the register of the correspondence among cyclic shift and the data register chain B one by one, and has new signal to move among the one dimension shifted data chain of registers A, just with its each register

Signal Synchronization is written in the register of the correspondence among cyclic shift and the data register chain B one by one, and after finishing synchronously at spreading code, cyclic shift and data register chain B are under the cyclic shift pattern, every through a clock cycle, each register among cyclic shift and the data register chain B

Signal all moves right to adjacent register, and its rightmost side register

Signal moves in the register of the leftmost side, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively;

Step 4: every through a clock cycle under the driving of synchronizing clock signals, with each register among cyclic shift and the data register chain B

Signal moves into corresponding parallel correlator, and corresponding parallel correlator is with each register among the chain of registers B

Signal is respectively with corresponding

Multiply each other, obtain 32 thus

Value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence;

Step 5: whenever obtain described 32

After the value, send into immediately in the summation module of parallel correlator, this summation module is with 32

The value summation that adds up obtains

Accumulated value, parallel correlator are just with this The mould module is asked in the accumulated value input, and this asks the mould module right

Accumulated value is asked mould, obtains

Mould value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence;

Step 6: ask the mould module to incite somebody to action

The mould value is input to spreading code and reaches the symbol demodulation module synchronously, detects when spreading code reaches the symbol demodulation module synchronously

The mould value is continuous when surpassing preset threshold value 8 times, pass through again after continuous 32 clock cycle, to cyclic shift and be written into register and write the cyclic shift sign, thereby cyclic shift and data register chain B are in into the cyclic shift pattern, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence

Step 7: under the driving of synchronizing clock signals, spreading code reaches the symbol demodulation module synchronously and just begins counting, promptly asks the every input of mould module once simultaneously Mould value, spreading code reach the symbol demodulation module synchronously and just count value are increased 1, and the count value initial value is 0, and spreading code reaches the symbol demodulation module synchronously when whenever finishing counting 32 times, just count value is returned 0, then according to asking the mould module to import when these the 32 times countings

Maximum in the mould value is noted the count value when maximum occurring, and notes parallel correlator gained when maximum occurring

The real part of symbol of accumulated value, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 1, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kValue for k spread-spectrum code chip of symbol 0 correspondence

Step 8: spreading code reaches the symbol demodulation module synchronously then described count value when maximum occurring is carried out rounding divided by 4 after, and parallel correlator gained when maximum occurring

The real part of symbol of accumulated value can obtain corresponding symbol, and this symbol is exported by high 4 bytes of stream data after hanging down 4 earlier, wherein K down-sampled complex sampling signal r _kExpression formula be:

θ wherein _kRepresent the phase place of k down-sampled complex sampling signal, k is the integer more than or equal to 0, ω ₀Represent the frequency shift (FS) of down-sampled complex sampling signal, φ represents the skew of down-sampled complex sampling signal, and T represents chip period, n _kRepresent the additive white Gaussian noise of the unit power of k down-sampled complex sampling signal, N ₀And E _SRepresent the power of noise and signal respectively, and satisfy:

${\mathrm{\θ}}_{k+1}-{\mathrm{\θ}}_k=\left\{\begin{array}{cc}-\mathrm{\π}/2& ,m_k=0\\ \mathrm{\π}/2& ,m_k=1\end{array}\right.$

Wherein

q _kBe represented as the value of k spread-spectrum code chip of 0 symbol correspondence

Step 9: under the driving of synchronizing clock signals, when described symbol is exported, simultaneously to cyclic shift and be written into register and write and be written into sign, thereby cyclic shift and data register chain B are in the pattern of being written into, and after a clock cycle, again to cyclic shift and be written into register and write the cyclic shift sign, thereby cyclic shift and data register chain B are in the cyclic shift pattern, return again in the step 6 and carry out.

2. realization radio sensing network 2.4GHz digital baseband signal demodulation method according to claim 1 is characterized in that: in the described step 7 spreading code reach synchronously the symbol demodulation module adopt mould 32 clock counters realize count value increase 1 and count value return 0 operation.

3. realization radio sensing network 2.4GHz digital baseband signal demodulation method according to claim 1 and 2, it is characterized in that: spreading code reaches the symbol demodulation module synchronously and comprises the maximum logging modle.